IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO.
4, JULY 1997
Switching-Behavior Improvement
of Insulated Gate-Controlled Devices
Salvatore Musumeci, Angelo Raciti, Member, IEEE,
Antonio Testa, Member, IEEE, Agostino Galluzzo, and Maurizio Melito
Abstract— MOSFET’s and insulated gate bipolar transistor
(IGBT) devices are increasingly used in electronic circuits due
to both their easy driving and ability to handle high currents and
voltages at high-switching frequencies. This paper deals with a
new driver technique that allows optimization of the switching
speed, reduction of the energy losses during the switching time,
and limitation of the electromagnetic interference (EMI). First,
an analysis of voltage- and current-switching waveforms of gate-
insulated devices is performed. Then, a method of controlling
voltage and current slopes independently is shown using the “one-
cycle” method or a suitable adaptive-driving technique based
on a phase-locked loop (PLL) approach. These techniques were
adopted in order to allow correct generation of the gate signals
regardless of the operating conditions. Finally, practical results of
the proposed driving circuit obtained using a single IGBT switch
chopper are presented.
Index Terms—Device-switching transients, driver circuit, insu-
lated gate devices, Miller-effect detection.
NOMENCLATURE
Parasitic capacitance between gate and
drain.
Parasitic capacitance between gate and
source.
Parasitic capacitance between gate and
drain.
Input capacitance.
Output capacitance.
Gate-drain capacitance with drain-gate
positive voltage.
Gate-drain capacitance with drain-gate
negative voltage.
Drain-current slope.
Drain-voltage slope.
Forward transconductance.
Drain current.
Drain current at zero-gate voltage.
Maximum value of the drain current on
inductive load.
Gate current.
Load inductance.
Stray inductances.
Gate resistance.
Manuscript received September 30, 1995; revised September 25, 1996.
Recommended by Associate Editor, W. M. Portnoy.
S. Musumeci, A. Raciti, and A. Testa are with the Universita di Catania,
Dipartimento Elettrico Elettronico e Sistemistico, 6 - 95125 Catania, Italy.
A. Galluzzo and M. Melito are with the SGS-Thomson Co.Ri.M.Me
Research Center, 50 - 95121 Catania, Italy.
Publisher Item Identifier S 0885-8993(97)04991-0.
0885–8993/97$10.00  1997 IEEE
645
On-path gate resistance.
Off-path gate resistance.
Control voltage enabling the current gen-
erator at turn-on.
Delayed control voltage enabling the cur-
rent generator at turn-on.
Control voltage enabling the current sink
at turn-off.
Drain-source voltage.
Drain-source on state voltage.
Voltage applied to the gate terminal.
Positive voltage applied to the gate termi-
nal.
Negative voltage applied to the gate ter-
minal.
Supply voltage.
Output voltage from the flip-flop (FF).
Gate-source voltage.
Gate-input control voltage.
Miller voltage.
Ramp voltage.
Output voltage of the group.
Trigger voltage.
Gate-source threshold voltage.
II. INTRODUCTION
T HE GROWING developments of power electronics in in-
dustrial applications have required a remarkable effort in
designing new electronic devices able to handle high currents,
voltages, and frequencies as well as easy drive control and
low-power requirements. Among the innovative electronics
devices, insulated gate bipolar transistors (IGBT’s) and power
MOSFET’s are increasingly used since the existing technol-
ogy can offer a wide range of devices: high-density power
MOSFET for high-current low-voltage applications, IGBT’s
for high-voltage high-current low-frequency applications, and
high-voltage power MOSFET for high-frequency applications
at low-power levels. Moreover, the physical characteristics of
such devices allow a degree of intelligence to be added on-chip
at low cost, providing significant improvements in ruggedness,
reliability, protection, and a reduction in system complexity.
Voltage-controlled devices are easier to drive compared
with current-controlled devices, but better performance can be
achieved by optimal driving techniques [1]. By increasing the
switching speed, it is possible to reduce the power dissipation
of a power device at the cost of both increased generation of
electromagnetic interference (EMI) and diode stress due to the
646 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 4, JULY 1997

peak of current. In fact, as the slope of the current during the

switching transients increases, the level of EMI is increased,
so a compromise between device features, power losses, and
EMI must be found in the design of any power converter.
The switching speed of a MOSFET device is related to
the rate of supply of charge to the gate-input capacitance [1],
[2]. The behavior of an IGBT device is similar to that of a
MOSFET, apart from the current tail present during turn-off
transient.
The aim of this paper is to illustrate a new driver strategy
and a circuit topology, which optimizes the compromise be-
tween switching speed, power dissipation, and electromagnetic
radiation by controlling the gate current during the switching (a)
transients [3]. The description of the new gate driver starts with
an analysis of voltage- and current-switching waveforms of
gate-insulated devices concentrating on those characteristics,
which influence the drain-current slope [4]. From the results
of this analysis, a driving methodology is developed that
allows independent control of voltage and current slopes. In
particular, an original driving technique is proposed, which is
able to act during both turn-on and turn-off, improving the
device performances by means of two approaches [5], [6]: the
circuit implementing the “one-cycle” automatic technique and
the adaptive driver implementing a new driving concept based (b)
on a phase-locked loop (PLL) circuit. Fig. 1. Gate charge of insulated gate devices during a turn-on transient. (a)
Switching transient traces and (b) static characteristics with the corner points
reported in (a).
III. PARAMETERS INFLUENCING THE SWITCHING TRANSIENTS
Switching transients of insulated gate devices are strongly drain voltage causing an increase in the gate-drain capacitance.
related to their stray capacitances and depletion-layer capaci- In addition, the drain voltage exhibits two different slopes due
tance [2]. A simple approach to the analysis of the switching the transition from a highly charged zone to the simple
transients may be performed by considering only two of such depletion of the MOSFET capacitor that exists between the
parasitic capacitances, namely, the gate-source capacitance deep-body cells. As soon as the Miller effect ends, the gate
and gate-drain capacitance (the drain-source capaci- voltage can begin to increase again, reaching its final value
tance having no effect). Moreover, by considering gate bias, at point 5.
gate-unit impedance, and stray-circuit inductances, the device The voltage slope is related to the rate of supply of charge
characteristics in terms of switching speed and power losses to the gate during the Miller-effect zone and to the change of
may be defined. the capacitance value. As a first approximation, we can define
two capacitances and that produce two different
slopes of [2].
A. The Gate-Charge Curve From an analysis of the above transient behavior, the
Useful information about the switching behavior of insu- following conclusions can be drawn.
lated gate devices can be obtained from the gate-charge curve 1) The current slope is related to the rate of supply of
[7], [8]. Even if the previous measuring conditions are different charge to the gate during the first slope of the gate
from the operating ones, the total charge supplied to the voltage, as defined by the following:
gate during the switching transient is the same. The gate-
charge curve shown in Fig. 1, obtained by injecting a constant (1)
current into the gate, can be divided in several phases. At the
beginning, starting from , the drain current remains where is the input capacitance defined as
equal to (ranging between a few A to hundreds of A) (2)
until reaches at point 1. The slope of the gate voltage
is fixed by the gate-input capacitance, which, in this phase, 2) During the turn-on and turn-off transients, the drain-
is constant and equal to . From this point, the device is source voltage is related to the rate of supply of charge
turned on and the drain current flows, reaching its maximum to the gate, while the Miller effect takes place, the slopes
value at point 2, while the drain voltage remains constant being given by the following:
at its maximum value.
Between points 2 and 4, the Miller effect occurs. During first slope (3)
this phase, the input capacitance appears to be infinite since
the gate voltage remains constant even though the gate circuit second slope (4)
is supplying current to the gate. This is due to a decrease of the
MUSUMECI et al.: SWITCHING-BEHAVIOR IMPROVEMENT OF GATE-CONTROLLED DEVICES 647

It should be noted that the curve obtained by injecting

charges into the gate is the mirror image of the one obtained
extracting charges. Hence, for power MOSFET’s, the above
observations also remain valid during turn-off. IGBT devices
require further explanation. As the gate voltage falls below the
threshold level, the electron current ceases in the MOSFET
part of the structure, while the hole current in the bipolar
junction transistor (BJT) part decays with a tail. Thus, due
to their inner structure, the current fall time is strongly related
to the technology used and cannot be improved by the driving
technique. However, the device delay time can be controlled
again, acting on the gate.

B. Gate Driven by Voltage Pulses

The above switching waveforms were generated using a
constant-current generator supplying the gate terminals of
the device. This is not a common case since IGBT’s and
power MOSFET’s are normally driven by voltage pulses. By
considering a step voltage applied to the input terminals
and arranging (1), (3), and (4), the drain-current and drain-
voltage slopes during turn-on and turn-off may be calculated
by means of the following:
(5)
Fig. 2. Parasitic inductances influencing the switching transient.
and ground. In any case, for IGBT’s, it is necessary to
take care of the reverse-bias safe-operating area (RBSOA).
It must be noted that in practical circuits, parasitic induc-
tances are present due to the wiring connections ( , , and
), as shown in Fig. 2. Such inductances affect the switching
transients, in particular, the driving voltage is reduced by
the presence of in the gate-source path. Equation (5) must
therefore be rearranged to account for the parasitic voltage
drop

first slope (6) (9)

second slope (7)

Note that the threshold voltage , input capacitance ,
where and transconductance depend on the specific device, while
(8) the step voltage and stray inductance are fixed by the
circuit. Experimental observations on actual power equipment
reveal that the term in (9) is much larger than the term
and and are the gate-drain ca- , so in order to obtain the desired , particular
pacitance, respectively, when the drain-gate voltage is positive care must be taken in the wiring layout to minimize the
and when such voltage reverses [2]. stray inductances. A good solution can be obtained by hybrid-
From (5), it can be seen that the can be controlled assembling the power devices and gate driver, thus, reducing
by the gate resistance . The selection of this resistance the spread of stray inductance due to the layout of the users.
must trade-off two divergent goals: low-power consumption,
which requires a low , and low-EMI generation, which
IV. GATE-DRIVING STRATEGIES
requires a high value of . In power-circuits design, a
compromise is thus generally found on the value of in The previous section described a simple driving strategy
order to achieve reasonably low-power losses and acceptable consisting of supplying a positive voltage to the gate
EMI levels. Moreover, the drive circuit can be configured to terminal at turn-on and a negative voltage at turn-off.
allow the use of two different values of gate resistance, one for The positive gate-voltage pulse applied to the input terminals
turn-on and the other for turn-off, called and must be selected to obtain a low drain-source on state voltage
(interested readers can find in [7] and [8] a comprehensive . The negative step-gate voltage, which would be
analysis about such resistance calculations). unnecessary to obtain the forward-blocking state during the
The turn-on and turn-off transients are driven by gate turn-off transient, is, however, useful to prevent spurious turn-
voltages and , respectively. The voltage is a on caused by in the input circuit through and to
positive quantity selected to a suitable value to have low also speed up the switching transients.
saturation of the device, while is a negative voltage From an analysis of the switching transient, the following
applied to prevent malfunctions in bridge configurations due conclusions can be drawn.
to the displacement current by the through . For 1) Power losses depend mainly on the rate of increase of
the latter case, a gate voltage of 5 V is quite normal. Perhaps drain current (collector), which affects the peak current
a similar result is obtainable by a low . Obviously, in due to the diode recovery, and, in case of IGBT’s, as
single-switch applications, one power supply can be used with well as the dynamic-saturation voltage phenomenon.
648
2) Switching transients generate conducted EMI with am-
plitudes directly related to the time variation of the drain
current .
In this paper, a new approach is used, which operates by
reducing the switching times of the devices by intervention
during the Miller effect. In this way, it is possible to accelerate
the voltage-drain variation, and thus, the switching speed
without increasing the drain-current slopes and EMI levels.
The proposed drive strategy is based on independent control
of the slopes of the drain (collector) voltage and current by
shaping the gate current. In fact, by supplying gate-current
pulses at the beginning of the Miller effect, it is possible to
quickly charge the input capacitance, speeding up the variation
of the drain (collector) voltage without changing the slope of
the drain (collector) current.
In order to evaluate the feasibility of such an approach, a
quantitative analysis can be outlined with regard to the energy
consumption during a switching transient [4]. The detection
of the Miller zone and enabling of a suitable current-pulse
generator in synchronization with its beginning is very crucial
to minimize the energy losses. Fig. 3 shows the experimental
curves of the variation in energy consumption of a device
during switching transients, comparing the proposed new
approach with a device used in normal conditions, for two
different values of the gate resistance. In detail, the energy
losses (in p.u. of the energy consumption with a traditional
driver circuit) are shown as a function of the intervention
instant (in percentage of the total duration of the Miller-zone
time). At 100% of the Miller stage (without intervention of the
current-pulse generator), no advantages result. As the current-
pulse generator acts before the end of the Miller-zone duration,
the energy saving becomes evident. Due to the particular
shape of the current pulse, ramping toward a peak value
with a suitable rise time, the maximum loss reduction without
collector current variation (any further loss reduction
is accompanied by current-slope variation) is obtained at a
practical delay of about 20% of the total time after the sensing
of the beginning of the Miller zone. In fact, experimental tests
have shown that 20% of the Miller-time duration (calculated
on unconditioned device transient) is the time required to
supply the charge onto the gate circuit, so obtaining the power-
loss reduction. This figure is a trade-off between the peak-
current value and advantages achievable. Further reductions in
power losses can be achieved, accepting a slope variation in
the collector current or by using a current-pulse generator with
a greater peak. In other words, the maximum of power-loss
reduction shown in Fig. 3 is a constrained maximum rather
than an absolute maximum.
At turn-off, the structural difference between power MOS-
FET’s and IGBT’s influences their behavior and leads to
different considerations.
1) Power MOSFET: The gate charge during turn-off, as
explained above, is the mirror image of the turn-on gate charge.
Thus, the proposed driving technique acts with a separate
control of the voltage and current slopes in order to optimize
the power loss and EMI levels.
2) IGBT: At turn-off, the IGBT’s show a tail during the
fall of the collector current due to the time required for the
excess carriers in the epitaxial drain region to recombine. This
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 4, JULY 1997
Fig. 3. Energy losses versus the time intervention of the current-pulse
generator (in percentage of the time duration of the Miller effect).
tail is responsible for large losses, as shown in [10], and is
strongly related to the technology used in the manufacture
of the device. Its effects cannot be reduced by means of the
driving circuit. Turn-off losses can be reduced during both the
Miller-effect and power MOSFET turn-off phases. Moreover,
in order to reduce losses, it is necessary to decrease the
value. As a consequence of the reduction in the value of
the gate resistance, the increases and, thus, losses
decrease. It is also necessary to not allow the RBSOA limits
to be exceeded since the latching current and RBSOA are
strongly related to , i.e., with [9]. The manufacturer
guarantees the RBSOA with a specified minimum value of .
Based only on the above requirements, the gate impedance can
result in a too-high value, which may cause the following.
1) In bridge configurations, a spurious turn-on of the IGBT
is probable if an excessive occurs across one
of the devices in off-state.
2) The turn-off delay time of the device could be very long.
The first problem is commonly solved by activating a low-
impedance gate-emitter path or by applying a negative bias
to the gate after the device turn-off. The proposed gate-
driving technique also solves the second problem by improving
the turn-off behavior while maintaining the same .
Furthermore, a faster reduction of the turn-off delay time and
current fall is obtained due to the power-MOSFET part of the
IGBT structure.
V. IMPROVEMENT OF THE SWITCHING
PERFORMANCES BY A NEW DRIVING TECHNIQUE
The proposed driving circuit, whose circuit is shown in
Fig. 4, has a standard push–pull output stage with separated
turn-on paths designed to energize the gate terminals. The
dynamic characteristics of the power device are improved with
the use of an optimal gate-emitter voltage, a strong current
pulse at turn-on, and a current sink at turn-off. In Figs. 5
and 6, two turn-on switching transients of an SGS-Thomson
TSG50N50DV-IGBT device are shown. In the first case, a
traditional driver circuit is used, while in the second, the power
device is driven by the proposed new circuit. Note from Fig. 6
the crossover time reduction at unchanged .
MUSUMECI et al.: SWITCHING-BEHAVIOR IMPROVEMENT OF GATE-CONTROLLED DEVICES
Fig. 4. Schematic of the new driving circuit.
Fig. 5. Turn-on switching waveforms with a traditional driving circuit. Vgs
(5 V/div), Vds (100 V/div), Id (10 A/div), Ig (0.2 A/div), and t (500 ns/div).
Fig. 6. Turn-on switching waveforms with the proposed driving circuit. Vgs
(5 V/div), Vds (100 V/div), Id (10 A/div), Ig (0.2 A/div), and t (500 ns/div).
As can be observed in Fig. 6, the speed of the gate-voltage
variation is noticeably increased with respect to that obtained
with the traditional driving circuit, while the collector-current
slope is practically the same (100 A/ s). To properly evaluate
649
Fig. 7. Turn-on switching energy enclosed within the instantaneous power
trajectory with a traditional driving circuit. Psw (1000 W/div) and t
(500 ns/div).
Fig. 8. Turn-on switching energy enclosed within the instantaneous power
trajectory with the proposed driving circuit. Psw (1000 W/div) and t
(500 ns/div).
the benefits of the proposed circuit in terms of energy saving,
the switching powers involved in the two transients are also
shown in Figs. 7 and 8. Using the proposed circuit, the lost
energy, given by the area enclosed within the power-loss
line, is reduced by more than 35%, evident from the two
experimental tests. However, a deeper insight on achievable
power-loss reduction during switching transients would require
the measurement of the total energy lost per cycle. Being
that such a task is strongly dependent on the used devices
(MOSFET or IGBT) as well as on the working conditions, a
comprehensive analysis will require further investigations.
Figs. 9 and 10 show the difference in behavior without
and with the intervention of the proposed circuit at turn-off
for TSG50N50DV-IGBT devices. In Fig. 10, we can see the
reduction of the delay time with the same (260 V/ s).
In this case, the total time during the turn-off commutation
decreases.
The results shown are obtained with a specific electronic
circuit that shapes the gate voltage after sensing of the Miller
zone. The approach is to manipulate the first derivative, with
respect to time, of the gate voltage. The slope variations of the
gate-charge curve are converted to positive or negative pulses
by a high-pass filter. The pulse handling, according to the
physics of the device, allows the enabling of the additional
current generators at suitable instants. Note that this -
650 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 4, JULY 1997

Fig. 12. Output voltage detected by the RC network. VRC (1 V/div) and
t (5 s/div).

Fig. 9. Turn-off switching waveforms with a traditional driving circuit. Vgs

(5 V/div), Vds (100 V/div), Id (10 A/div), and t (1 s/div).

Fig. 13. VRC voltage-peak value at turn-on versus the RC -group time
constant.

the driving circuit and to produce a sufficiently large

Fig. 10. Turn-off switching waveforms with the proposed driving circuit.
Vgs (5 V/div), Vds (100 V/div), Id (10 A/div), and t (1 s/div).
signal [3].
The following expression can be used to calculate the
amplitude of the signal across the resistor of the network
at turn-on according to the parameters of the devices used

(10)

The peak values assumed by the voltage at turn-on

Fig. 11. Gate voltage during a turn-on and turn-off of insulated gate devices
Vgs (5 V/div) and t (5 s/div).
network output signal follows the gate-voltage variation in
loaded conditions too. With reference to a whole-cycle switch-
on/switch-off performed on the TSG50N50DV-IGBT device,
Figs. 11 and 12 show the gate voltage and the -network
output voltage (in a suitable x-axis scale to properly show
the voltage pulses) used to detect the Miller zone—the positive
and negative voltage pulses of Fig. 12 clearly evidence the
transient detection.
The main constraints to consider during the design of this
network are as follows.
1) The capacitance must be smaller than the input
capacitance of the device in order to not affect
the dynamic characteristics of the gate voltage.
2) The resistance must be small in order to obtain a high
bandwidth, but must be big enough to not interfere with
versus the value of the group are shown in Fig. 13 for
different IGBT devices with the conditions V,
A, and . Similar considerations
can be applied to the transient behavior occurring at turn-off.
In the case presented in this paper, the time constant has
been selected as 0.5E-7 s, thus, producing a signal of more
than 1.5 V with a good trade-off between large bandwidth and
influence on the driver-circuit performances.
The enabling of both the current-pulse generator and current
sink has been developed in two different ways. The enable
circuit can work based on “one-cycle” switching transients or
based on an adaptive technique.
A. “One-Cycle” Technique
In this method, the enabling circuit was realized by a very
fast circuit that amplifies the detected signal from the high-pass
filter and enables the appropriate paths each cycle at turn-on
and turn-off. Fig. 14 shows the gate voltage and the signal
enabling the current generator at turn-on. Fig. 15 shows
the gate-voltage and signal enabling the current sink at
turn-off. The first pulse reduces the turn-off delay time, while
the second speeds up the fall of the collector current. This
approach has some drawbacks since it is strongly dependent
MUSUMECI et al.: SWITCHING-BEHAVIOR IMPROVEMENT OF GATE-CONTROLLED DEVICES
Fig. 14. Principle of operation at turn-on of the proposed circuit. Vgs
V/div), Vcp (5 V/div), and t (500 ns/div).
Fig. 15. Principle of operation at turn-off of the proposed circuit. Vgs
(5 V/div), Vcs (5 V/div), and t (1 s/div).
on the circuit speed and is sensitive to the electrical noises.
Therefore, it may be useful to use a different strategy with
a self-regulating intervention to generate the correct driving-
current pulses.
B. PLL-Based Circuit
This method has been developed since in the “one-cycle”
technique, it is not easy to directly use the derivative of the
gate voltage to enable the current generators due to noises
and the need for very fast (and, hence, expensive) devices. In
detail, a PLL approach has been selected to control the driving-
current pulses. The above PLL circuit is used to synchronize
the driving-current pulses, both at turn-on and at turn-off, with
the beginning of the Miller effect. This is necessary to obtain
the best results and cannot be simply achieved by imposing a
fixed delay between the driving signal and current generator.
In fact, such delay must be continuously changed according
to the operating conditions.
At turn-on, the proposed drive circuit operates as follows.
1) The initial gate current is fixed by adjusting , previously, in power circuits using IGBT devices, the presence
taking account of both device electrical specifications
and EMI requirements.
2) When the collector current reaches its maximum value,
the collector voltage starts to decrease, and the Miller
effect appears on the gate-emitter voltage. This condition
651
is detected by the Miller-effect sensing circuit, based on
an network.
3) The output of this sensing circuit is then processed by a
PLL circuit that generates suitable triggering signals for
the current-pulse generator.
4) The current generator increases the gate current accel-
erating the collector-voltage fall, thus, eliminating the
dynamic-saturation voltage phenomenon.
The PLL approach quickly reduces the phase difference
between the trigger signal of the current-pulse generator and
the signal corresponding to the begin of the Miller zone. As the
firing time of the gate-current pulses must change according
to the operating conditions and characteristics of the device,
the PLL circuit dynamically adjusts the trigger signals of the
(5
current generator and current sink.
A schematic of the PLL circuit operating at turn-on is shown
in Fig. 16, showing:
1) the Miller-effect sensing block, based on an net-
work;
2) a phase comparator detecting the phase shift between the
output of the network and the signal enabling
the current generator ;
3) a low-pass filter producing a variable threshold ;
4) a time-delaying block used to compensate propagation
delays;
5) a ramp generator triggered by the command signal ;
6) a voltage comparator producing the enabling signal for
the current generator .
In order to synchronize the signal enabling the current
generator with the beginning of the Miller effect at turn-on,
the output of the filter , amplified and squared, is used
to set an FF, as shown in Fig. 16. A suitable reset signal is used
to disable the FF at turn-off to avoid incorrect operation. The
output of FF is then phase compared with obtained
by delaying the signal enabling the current generator, as shown
in Figs. 17 and 18. Such a delay must be chosen in order to
compensate any propagation delay.
The output of the phase comparator is processed by a low-
pass filter, generating a variable threshold . This threshold
is used to modify the firing times of the current pulses at turn-
on in order to match the beginning of the Miller effect. The
signal enabling the current pulses is generated, as shown
in Figs. 16 and 19, by comparing the variable threshold
with a ramp triggered by the command signal . Any
phase difference detected by the phase comparator modifies
the time delay between the command signal and gate-current
pulses in such a way as to reduce the phase difference in the
next switching. After a small number of cycles, related to the
characteristics of the low-pass filter, the signal triggering the
current pulses is correctly synchronized with the beginning of
the Miller effect, as shown in Fig 14.
When using MOSFET devices, similar considerations can
be made for the PLL circuit operating at turn-off. As noted
of the current tail significantly reduces the advantages of the
proposed driving strategy so the PLL circuit at turn-off can
be removed [6].
In the case of dc–dc converters with pulse width modulation
(PWM) control, the minimum “on” time is limited by the
652
Fig. 16. Block diagram of the PLL circuit operating at turn-on.
Fig. 17. Phase comparator inputs at different frequencies.
t (200 ms/div).
Fig. 18. Voltage signal Vcp enabling the current generator and input of phase
comparator Vcpd . V (5 V/div) and t (200 ns/div).
maximum allowed frequency of the used devices and also
by the maximum operating frequency of the PLL-based drive
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 12, NO. 4, JULY 1997
V (5 V/div) and Fig. 19. Voltage comparator inputs. V (5 V/div) and t (200 ns/div).
unit. The realized tests have been obtained with a PLL system
assembled by commercially available discrete components,
and the minimum time required to be effective during the
transients of the used IGBT’s was established at 1.5 s, easily
obtained by the proposed drive unit.
VI. CONCLUSION
The characteristics of an optimal driving circuit for gate-
controlled devices have been analyzed. The development and
experimental evaluation of two methodologies to drive gate-
controlled devices have been presented. In particular, two drive
circuits, one automatic and one adaptive, have been developed.
An experimental evaluation of the device performances has
been carried out with both traditional and new driving circuits,
demonstrating the advantages of the new ones.
The most important results obtained can be summarized as
follows. The automatic detection of the Miller effect makes the
driving circuit independent on the driven device and operating
MUSUMECI et al.: SWITCHING-BEHAVIOR IMPROVEMENT OF GATE-CONTROLLED DEVICES
conditions. At turn-on and turn-off, the circuit permits separate
control of the voltage and current gradients, allowing the
reduction of both power losses and EMI. In addition, the
turn-off delay time can be easily controlled.
Based on the obtained results, it has been found that the new
driving circuit allows better performance obtained from the
devices, resulting in an increase of efficiency and reliability.
The increased complexity and related cost suggest that the
proposed circuit be used mainly in high-power applications.
In conclusion, in the case of driving-circuit integration
separate from the power devices, bipolar or bipolar CMOS
double-diffused MOS (DMOS) technologies can be used. The
integration on the same silicon chip is possible with Vertical
Intelligent Power (VIPower by SGS-Thomson) technologies
using a power-MOSFET output stage, but has not yet been
accomplished using an IGBT output stage.
ACKNOWLEDGMENT
The authors wish to acknowledge the anonymous reviewer
whose precise suggestions, qualified comments, and correc-
tions contributed to the quality of this work.
REFERENCES
[1] A. R. Hefner, “An investigation of the drive circuit requirements for
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[2] B. J. Baliga, Modern Power Devices. New York: Wiley, 1987.
[3] S. Musumeci, A. Raciti, A. Testa, A. Galluzzo, M. Melito, and G.
Belverde, “Switching characteristic improvement of modern gate con-
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and Exposition APEC ’94, Orlando, FL, Feb. 1994, pp. 480–486.
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in Conf. Rec. Power Electronics, Electrical Drives, Advanced Electrical
Motors SPEEDAM ’94, Taormina, Italy, June 8–10, pp. 203–208.
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for power MOSFET circuits,” in Proc. IEEE Power Conversion on
Intelligence Motion, Munich, Germany, 1990, pp. 153–159.
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[9] M. Melito and R. Letor, “Safe behavior of IGBT’s submitted to
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Salvatore Musumeci was born in Giarre, Italy, in
May 1964. He received the Dr. Ing. and Ph.D.
degrees in electrical engineering from the Univer-
sity of Catania, Catania, Italy, in 1991 and 1995,
respectively.
He is currently researching the fields of power
electronics, power devices, and electrical drives.
653
Angelo Raciti (M’93) was born in Catania, Italy,
and received the Dr. Ing. degree in electrical engi-
neering from the University of Catania, Catania.
From 1975 to 1981, he was with Intar Spa, Gen-
ova, Italy, involved in the development of advanced
power-conversion systems. In 1982, he joined the
Department of Electrical Electronic and Systems
Engineering, University of Catania, where he is
now a Researcher and teaches power electronics.
His research interests are in the fields of electrical
machines, power electronics, semiconductor power
devices, and advanced control techniques.
Dr. Raciti is a Member of the Italian Association of Electrical and Electronic
Engineers (AEI).
Antonio Testa (M’91) was born in Catania, Italy,
in 1962. In 1988, he received the Dr. Ing. degree
in electrical engineering from the University of
Catania, Catania.
In 1990, he joined the Department of Electrical
Electronic and Systems Engineering, University of
Catania. In 1991, he was a Visiting Researcher at
the University of Wisconsin, Madison. His major
research interests are electrical drives, digital control
systems, and power converters.
Dr. Testa was a recipient of the SGS-Thomson
Grant on power electronics in 1989.
Agostino Galluzzo received the Dr. Ing. degree
in electronic engineering from the University of
Palermo, Palermo, Italy, in 1979.
After two years with GTE Telecommunications,
he joined the Research and Development Depart-
ment of the Discrete and Standard Logic Group
of SGS-Thomson Microelectronics, Catania, Italy,
in 1982, where he is currently responsible for the
Research and Development Application Laboratory
and is involved with the development of R.F.-
integrated circuits using high-speed bipolar technol-
ogy. He has been closely involved with the development of several SGS-
Thomson power devices families, particularly V.H.V. fast bipolar transistors,
power MOSFET’s, IGBT’s, and VIPower. He is the author of several technical
papers.
Dr. Galluzzo is a Member of the Italian Association of Electrical and
Electronic Engineers (AEI).
Maurizio Melito received the Dr. Ing. degree in
electronic engineering in 1982 from the Polytechnic
of Turin, Turin, Italy.
Since 1984, he has worked at SGS-Thomson
Microelectronics in the Research and Development
Laboratory. His current work is in the Application
Laboratory, which deals with the characterization
and application of discrete-power (power MOS-
FET’s, IGBT’s) and VIPower devices. He has writ-
ten several technical publications on these topics.