IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.
2, MARCH 2008
An IGBT Gate Driver for Feed-Forward Control of
Turn-on Losses and Reverse Recovery Current
Petar J. Grbovic, Member, IEEE
Abstract—This paper addresses the problem of turn on perfor-
mances of an insulated gate bipolar transistor (IGBT) that works
in hard switching conditions. The IGBT turn on dynamics with an
inductive load is described, and corresponding IGBT turn on losses
and reverse recovery current of the associated freewheeling diode
are analysed. A new IGBT gate driver based on feed-forward con-
trol of the gate emitter voltage is presented in the paper. In con-
trast to the widely used conventional gate drivers, which have no
capability for switching dynamics optimisation, the proposed gate
driver provides robust and simple control and optimization of the
reverse recovery current and turn on losses. The collector current
slope and reverse recovery current are controlled by means of the
gate emitter voltage control in feed-forward manner. In addition
the collector emitter voltage slope is controlled during the voltage
falling phase by means of inherent increase of the gate current.
Therefore, the collector emitter voltage tail and the total turn on
losses are significantly reduced. The proposed gate driver was ex-
perimentally verified and compared to a conventional gate driver,
and the results are presented and discussed in the paper.
Index Terms—Gate emitter voltage, insulated gate bipolar tran-
sistor (IGBT) gate driver, reverse recovery current, turn on losses.
NOMENCLATURE
Gate emitter parasitic capacitance.
Gate collector parasitic capacitance.
Collector emitter parasitic capacitance.
Input capacitance.
Gate collector charge.
Parasitic inductance of the IGBT module.
Parasitic inductance of the internal IGBT
power emitter connection.
Parasitic inductance between the auxiliary and
power emitter connections.
Parasitic inductance of the dc bus structure.
Resistance of the dc bus structure.
DC bus voltage.
Load current.
Load inductance.
Load resistance.
Positive gate voltage supply.
Negative gate voltage supply.
Manuscript received February 23, 2007; revised June 14, 2007. Recom-
mended for publication by Associate Editor E. Santi.
The author is with the Research and Development Department, Schneider
Toshiba Inverter Europe, Pacy-Sur-Eure 27120, France (e-mail: petar.gr-
bovic@fr.schneider-electric.com).
Digital Object Identifier 10.1109/TPEL.2007.915621
0885-8993/$25.00 © 2008 IEEE
643
Internal gate emitter voltage.
Reference gate emitter voltage.
External gate emitter voltage.
Gate emitter threshold voltage.
IGBT trans-conductance.
Magnitude of the reverse recovery current
Gate current.
Collector current slope.
FWD current slope.
Collector emitter voltage slope.
Gate emitter voltage slope.
Turn on losses.
Turn on gate resistance.
Turn off gate resistance.
Damping gate resistance.
I. INTRODUCTION
NSULATED gate bipolar transistor (IGBT) modules with
I anti-parallel free wheeling diodes (FWD) are widely used
in power converters such as voltage source pulse width modu-
lated (PWM) inverters in motor drive applications, uninterrupt-
ible power supplies (UPS), and active filters. These converters
employ IGBT modules as active switches which operate in hard
switching conditions. Typical converter topology consists on six
IGBTs with FWD connected in parallel, arranged in a three leg
inverter, whose circuit diagram is depicted in Fig. 1. The FWDs
optimized for hard switching conditions are based on silicon
PiN diodes in controlled axial lifetime (CAL) and hybrid tech-
nology.
A gate driver acts as a link between the converter control unit
and the raw power. The gate driver has to control the IGBT con-
duction state, optimises the switching performances and pro-
vides protection of the IGBT switch. In this paper, we will con-
centrate on the turn on performances; the IGBT turn on losses,
reverse recovery current of the associated FWD, and electro-
magnetic interference (EMI) caused by high during the
switching. Conventional gate drivers widely used in such type
of power converters are based on pure resistive control of the
gate current. The gate resistance is normally selected to achieve
a compromise between turn on losses of the IGBT, magnitude
of the reverse recovery current of the FWD, and EMI emission.
However, a simple resistive controlled gate driver does not pro-
vide full control of the IGBT, and the turn on performances is
sub-optimal.
644
Fig. 1. Application of IGBT modules.
Significant work on this topic has been done in the last
decade, and numerous papers and thesis were published
[1]–[12]. A multi step driving technique which provides reduc-
tion of the reverse recovery current has been proposed in [1].
The gate emitter voltage is applied in two predefined steps; first
step corresponds to the Miller’s voltage, while the second step
is full voltage equals to the positive gate supply voltage.
A three-step gate driver has been proposed in [2]. During
the first step, the gate capacitance is charged with a large gate
current. Hence, turn on delay time of IGBT is reduced. In the
second step, the IGBT operates in the active region and gate
capacitance is charged with relatively small current in order
to limit the collector current slope and reverse recovery cur-
rent as a consequence. During the third step, the gate capac-
itance is charged again with a large current. As a result, the
collector emitter voltage tail and turn on losses are reduced.
The gate driver requires a complex control circuit for accurate
detection of the instances for changes in driving modes and
their duration. A gate driver based on the gate emitter voltage
measurement and the Miller’s plateau detection was analysed
and proposed in [3]–[6]. During the first phase of the commu-
tation, the gate emitter capacitance is charged with relatively
small current. Once the gate emitter voltage reaches the Miller’s
plateau, the detection circuit based on PLL detects the Miller’s
plateau and injects an additional current in the gate. Thus, the
collector emitter voltage tail and switching losses are reduced.
Closed-loop regulation of the collector current slope was pro-
posed and analysed in [7]–[9]. The collector current is sensed
by parasitic inductance between the auxiliary emitter and power
emitter terminals. The inductor voltage is directly proportional
to the collector current slope , which is further used as
the regulated variable. Several techniques have been reported
for providing an additional regulation of the collector emitter
voltage slope [8]–[10]. The device voltage is sensed by a high
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
voltage capacitor connected on the collector terminal. The ca-
pacitor current proportional to the collector emitter voltage rate
is processed and regulated. Such a technique provides
full optimization of the switching performance; minimisation of
the switching losses, reverse recovery current and the collector
emitter over-voltage. Dynamic and static voltage sharing of se-
ries-connected IGBTs in high voltage applications has been dis-
cussed in many publications [11]–[13]. The voltage of each de-
vice in the chain is directly sensed by a passive network, and reg-
ulated by a fast operational amplifier. The proposed technique
provides full control of the collector emitter voltage. The disad-
vantage is, however, lack of control of the collector current rate
during turn on. As a result, the reverse recovery current control
and full optimisation are not possible.
All the existing solutions reported in the literature need the
IGBT state detection (the Miller’s plateau) and the collector cur-
rent measurement circuit. The main drawback of these solutions
is the bandwidth requirement of the detection and regulation cir-
cuits. The detection and feedback circuit has to be very fast, with
bandwidth of more than 20 MHz, even up to 100 MHz. Also,
active circuits used for detection and regulation are sensitive to
strong electromagnetic field in the gate driver environment.
A gate driver with feed-forward control of the turn on dy-
namics is presented in this paper. The gate emitter voltage is
controlled in feed-forward manner. Using this technique the col-
lector current slope can be easily controlled without either active
or passive feedback circuit. Hence, magnitude of the reverse re-
covery current of the associated FWD is also controlled and re-
duced. The collector emitter voltage slope during the final phase
of the commutation is controlled. The total turn on losses are re-
duced independently on magnitude of the reverse recovery cur-
rent. The proposed gate driver is experimentally verified and the
results are presented in this paper.
II. IGBT TURN ON BEHAVIOR UNDER AN INDUCTIVE LOAD
The IGBT dynamics is similar to the MOSFET dynamics
during most of the turn on interval. It could be simply explained
by the majority current phenomena during turn on process
[17]–[19]. The total collector current of the IGBT is composed
of the internal MOSFET electron current and the BJT hole
current. The hole current would be neglected in analysis of the
IGBT turn on dynamics. It is reasonable close to the reality
due to two facts; the internal BJT is normally designed to have
low current gain, and the MOSFET dynamics is dominant
compared to BJT dynamics.
Let us make an overview of the IGBT commutation under
hard switching conditions with an inductive load. As an ex-
ample, we will consider one leg of the three phase inverter.
The simplified circuit diagram is depicted in Fig. 2(a). The
IGBT is represented as a current source . The dc bus
voltage is modeled as an ideal voltage source with the
bus impedance, and . The time constant of
load is assumed to be much greater than switching time of the
IGBT. Thus, the load current is approximately constant
during a short time of the commutation.
We will assume that the IGBT is off, and the FWD conducts
the entire load current .
GRBOVIC: IGBT GATE DRIVER 645

Fig. 3. IGBT simplified linear model.

Since the gate emitter voltage is below the threshold voltage

, the collector current remains zero. The IGBT input
capacitance is assumed to be constant and linear capaci-
tance. This is reasonable close to the reality since the Miller’s
capacitance is small compared to the gate emitter capac-
itance , and the collector emitter voltage remains constant
[14], [17]. We must highlight that these assumptions are valid
only if the gate emitter voltage is below the threshold voltage.
Phase II: Phase II begins at the moment when the gate
emitter voltage reaches the threshold voltage . At this
point the internal MOSFET forms the channel and electron cur-
rent begins to flow. As a result, the total collector current rises
with a slope . The FWD remains forward biased and con-
ducts a part of the load current. Referring to the circuit diagram
given in Fig. 2(a), we can estimate the collector emitter voltage
during this phase of the commutation.

(1)
The inductances and are the module stray induc-
tance and the dc bus structure inductance. The total commuta-
tion inductance and fast increase in the collector current gen-
Fig. 2. (a) Equivalent circuit of an inverter phase and (b) sketch of the wave- erate initial inductive voltage drop , which may reflect as
forms at turn on. the negative gate capacitance and then speed up the gate emitter
voltage. As a result, the collector current increases faster [19].
As the collector emitter voltage is high, the internal MOSFET
After applying turn on command, the load current is com-
operates in the active region. The total collector current of IGBT
muted from the FWD to the IGBT. The relevant waveforms are
strongly depends on the gate emitter voltage , and slightly
sketched and depicted in Fig. 2(b). We will divide the entire
depends on the collector emitter voltage . To facilitate the
commutation process into 4 phases designated as phase I to IV,
analysis, we will neglect the plasma and space charge reaction
and subsequently explain hereafter.
time and consider that the IGBT operates in quasi steady state
Simplified model of an IGBT which operates in active region
[19]. This model is reasonable close to the reality. Hence, the
is depicted in Fig. 3. This model would be used in the analysis.
steady state equations could be used to define the collector cur-
The collector current is represented by a voltage controlled cur-
rent as a function of the gate emitter and collector emitter volt-
rent source . The module interconnections and bond wires
ages, and the IGBT parameters [15], [18], [19]
inductances are represented by and . The parasitic
capacitances are represented by , and .
Phase I: The gate emitter voltage is equal to the negative
gate supply voltage . The turn on command is applied at
the moment , and the gate emitter voltage begins to rise up.
646 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

for

(2)
and

for
(3)
where , and are coefficients dependent on the
device technology, is the emitter base junction voltage, and Fig. 4. Collector gate capacitance versus the collector emitter voltage.
is the gate emitter threshold voltage, [15]. Equation
(3) could be further simplified expanding the collector current
in the Taylor series and then taking just the first term. Now, the where is the gate collector charge, and is the
collector current is simplified as capacitance between the gate and collector. This capacitance is
a strictly decreasing non-linear function of the collector gate and
the collector emitter voltage [14], [18], simplified as

(7)
(4)
where is the IGBT forward Applying (7) into the (6) yields
trans-conductance.
As we mentioned above, the load current is constant (8)
during a short period of the commutation. Therefore, the FWD
current falls with the same slope as the collector current rises
The collector gate capacitance can be further approx-
(5) imated as a two-step function of the collector emitter voltage
(see Fig. 4)
The FWD current falls to zero, and evidently change its sign
due to the stored charge. At the moment , the FWD reverse (9)
recovery current reaches its peak , and then the diode starts
to recover. Since the collector emitter voltage remains at a high Now, the collector emitter voltage slope is approximated as
level and the collector current rises from zero up to the peak
, a large amount of energy is dissipated in the device (10)
in this phase. It is the first part of the total turn on losses.
Phase III: At the moment the FWD pn junction has been
As the collector current is equal to the load current and
cleared from plasma, and the diode begins to block. Then, the re-
the collector emitter voltage decreases from the approximately
verse recovery current falls to zero and the diode voltage builds
dc bus voltage to zero, a large amount of energy is dissipated in
up. This increase in the diode voltage results in rapid decrease
the device during this phase of the commutation. It is the second
of the collector emitter voltage. As the collector current remains
part of the total turn on losses.
constant, supported by the inductive load, and the IGBT still op-
Phase IV: Phase IV begins at the moment , when the col-
erates in the active region, the gate emitter voltage must remain
lector emitter voltage reaches the dynamic saturation voltage,
constant. The gate emitter voltage is defined by the collector
. The IGBT leaves the active region. The negative
current and the trans-conductance . This phenomenon is well
feedback from the collector to the gate due to the Miller’s effect
known as the “Miller’s effect” [18], [19]. The entire gate current
is not present, and the gate emitter voltage increases towards
discharges the gate collector capacitance and supports
the supply voltage . The collector emitter voltage drops
the variation in the collector emitter voltage.
to its final static saturation level defined by the load
Now, we will estimate the collector emitter voltage slope
current and the gate supply voltage .
. Let’s first define the gate current as a function of
the collector emitter voltage and its derivation .
Considering the equivalent model and the convention given III. REVERSE RECOVERY CURRENT AND TURN ON LOSSES
in Fig. 3, and the assumption that the gate emitter voltage is In this section, we will briefly define the reverse recovery cur-
constant , we can define the gate current as rent and turn on losses as a function of the gate driver features.

A. Reverse Recovery Current

Reverse recovery current of a FWD is a non-linear function of
several parameters; the FWD technology, the current slope at the
(6) zero crossing point, junction temperature and forward current
GRBOVIC: IGBT GATE DRIVER
[19]. The reverse recovery current can be expressed in a general
form
(11)
where the functions and are non-linear functions depen-
dent on the FWD technology, the junction temperature and the
bus voltage. The reverse recovery current magnitude is a
strictly positive function of , [19], symbolically ex-
pressed as
(12)
where the gate emitter voltage slope depends on the
gate driving strategy; gate resistance, gate voltage, total and ad-
ditional gate capacitance.
B. Turn on Losses
Now, we will estimate the energy dissipated in the IGBT over
one turn on cycle. We will use the notation turn on losses or turn
on energy . The effects of the commutation inductances
and on the turn on energy will be neglected in the
analysis. As mentioned before, the turn on energy consists
of the two parts; the commutation phase II and the phase III.
The total energy dissipated over the cross-over time during one
single commutation is
(13)
where is magnitude of reverse recovery current which has
been defined in (11). The first part in (13) represents amount of
energy being lost during the commutation phase II. The second
part of (13) represents the energy being lost during the commu-
tation phase III. For simplicity of the analysis, the residual re-
verse recovery current has been neglected in the second part
of the total energy calculation (13). Taking in account the fact
that we do not need accurate calculation of the losses, but just
estimation of the losses trend, we can accept such an approxi-
mation. More accurate calculation of the total turn on losses is
discussed in [16].
Inserting (4), (10), and (11) into (13) gives the turn on energy
as a function of the gate emitter voltage slope , Conventional control of the IGBT is based on a simple gate
gate current , steady state the dc bus voltage and the
load current
(14)
As we may observe from (12) and (14), both the reverse re-
covery current and the turn on losses depend on . An
647
Fig. 5. Conventional gate drive circuit-state of the art.
increase in increases the reverse recovery current and
decreases the turn on losses, and vice verse
and (15)
The gate current discharges the collector gate capacitance
during the phase III (collector emitter voltage fall phase).
This current affects only the turn on losses, but does not affect
the reverse recovery current. An increase in the gate current de-
creases the turn on losses, and vice verse
and (16)
From (15) and (16) it is obvious that independent control of
the gate emitter voltage slope and gate current is es-
sential for optimization of the commutation dynamics and mini-
mization of the reverse recovery current and turn on losses. The
gate voltage slope controls dynamics during the phase
II (the collector current rising phase) and consequently controls
the reverse recovery current, whereas the gate current con-
trols the dynamics and turn on losses in the phase III. It the fol-
lowing section we will compare the turn on performances of an
IGBT driven with a standard gate driver and the new proposed
feed-forward driver (see Fig. 6).
IV. CONVENTIONAL GATE DRIVING METHOD
driver whose block diagram is depicted in Fig. 5. The driver
consist of a gate resistor which is usually split in two resistors
and , low impedance output buffers SW1 and
SW2, a digital control unit which drives the buffers, and the gate
driver power supply , usually 15 V, and , usually 5 to
15 V The gate resistors are utilized to limit the gate current
and adjust switching speed of the IGBT.
At the moment the buffer SW1 turns on. The input gate
capacitance is charged via the resistor and the pos-
itive supply voltage . Thus, the gate emitter voltage
648
Fig. 6. Proposed feed forward gate driving.
increases from the initial negative voltage . To compute the
collector current slope we will refer to the equivalent circuit di-
agram given in Fig. 3 and quasi-steady state model given in (3).
The voltage designated as is voltage across the gate emitter
connection on the chip. In a real circuit, however, there is an in-
ductance between the auxiliary emitter and the emitter con-
nection on the chip level, Fig. 3. It is mostly the inductance of
the bond wires between the chip metallization and the substrate
connection. Therefore, the internal gate emitter voltage sig-
nificantly differs from the gate voltage across the
external gate-emitter terminals. We will take this effect in the
account in the following analysis.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
The external gate emitter voltage is approximated as an
exponential function with time constant
. The gate emitter voltage slope is
(17)
The collector current slope at the moment when the FWD
current changes sign is
(18)
The gate current and the collector emitter voltage slope during
a fall phase of the collector emitter voltage are
(19)
(20)
Inserting (17) and (19) into (14) yields the total turn on energy
as seen in (21), shown at the bottom of the page.
The gate driver with simple resistive control has only one ad-
justable element; the gate resistance . As we may ob-
serve from (17) and (19), both, the gate emitter voltage slope and
the gate current depend on the gate resistance . Hence, it
is obvious that separate control of the collector current and col-
lector emitter voltage slopes is not possible. As a consequence,
the reverse recovery current and turn on losses depend on the
gate resistor
and (22)
The gate resistor is normally selected for trade-off between
the reverse recovery current and turn on losses. The selected gate
resistor, however, does not provide optimization of the IGBT
dynamics and minimization of the reverse recovery current and
turn on switching losses.
V. PROPOSED FEED-FORWARD CONTROL
We already mentioned that the full optimisation of the turn on
performances requires independent control of the gate emitter
voltage slope during the phase II (the current rise phase), and the
gate current during the phase III (the collector emitter voltage
fall phase). The gate driver which provides these features had
been described and proposed in [20]. Fig. 6 illustrates the pro-
posed feed-forward gate driver and sketch of the most impor-
tant waveforms. The gate driver consists of a gate voltage shape
generator, an output buffer and a damping gate resistor . The
gate voltage shape generator provides a reference voltage with
(21)
GRBOVIC: IGBT GATE DRIVER 649

approximately constant slope. The slope is adjusted according to

the required slope of the gate emitter voltage and collector cur-
rent respectively. The output stage in push-pull topology plays
a role of a voltage follower that provides decoupling between
the gate voltage shape generator and the IGBT gate.
The gate resistor is used as a damping resistor to prevent
oscillations and instability of the gate emitter voltage due to
gate inductance and gate capacitance. The resistance should be
selected for reasonable damping, usually 0.7 0.9

(23)

The inductance 50–150 nH is the total gate circuit

inductance, including internal and external inductance. The ca- Fig. 7. Proposed gate voltage shape generator.
pacitance is the gate emitter capacitance. Normally, the
selected gate resistor is significantly smaller than the resistor
recommended by the IGBT manufactures. Therefore, we may desired slope and amplitude. Fig. 7 shows a shape generator
assume that the gate circuit time constant is negligible compared based on a passive RLCD circuit and an output buffer in
to rise time of the reference gate voltage. Therefore, we PUSH–PULL topology. The RLC circuit is slightly damped,
may assume that the is completely independent on the with a damping factor of 0.2 to 0.5. It ensures that the
gate resistor reference voltage has almost a constant slope in voltage range
of our interest; from the to . However, due to
(24) insufficient damping, the capacitor voltage has tendency for
overshoot of 20% to 50%. To limit the overshoot on level of
At the moment the reference voltage begins to rise 5% to 10 % we utilize the clamping zener diodes and .
up. The gate capacitance is being charged and the gate The input voltage which comes from the previous stage
emitter voltage follows the reference voltage with slight is equal to the negative gate supply voltage . The capacitor
delay. The gate emitter voltage reaches the threshold voltage is charged also to the voltage . Now, we will assume that
at the moment and the IGBT begins turning on. the input voltage switches to the positive voltage at the
Referring to the equivalent circuit in Fig. 3, the quasi-steady moment , and excites the RLC circuit. The voltage and the
state model given in (3), and assumption (24) we can define the reference voltage rise up. At the moment the voltage
collector current as a function of time and the gate parameters on the capacitor reaches the zener diode breakdown voltage
and remains constant at the level . The reference
voltage follows the capacitor voltage with an error of
0.7 V. Ratio between the natural frequency of the
(25) RLC circuit and the desired slope of the reference gate emitter
voltage could be found from
The collector current slope is
(27)
(26) where is desired slope of the reference gate voltage
and is an angle at which the reference gate voltage slop has
At the moment , the gate emitter voltage reaches the a maximum. The coefficient 1.05 takes in account the fact that
Miller’s plateau and remains at the constant level de- the reference voltage slope is not constant, but varies roughly
fined by the load current and the IGBT trans-conductance within % around the average value (for the reference voltage
. The reference voltage continues to rise up towards the 5 to 15 V). The angle is calculated from the relative
positive supply voltage . The difference between the refer- damping factor as
ence gate emitter voltage and the gate emitter voltage is compen-
sated by a voltage drop on the gate resistor . As mentioned (28)
before, the gate resistor is small, and therefore the gate cur-
rent increases significantly. Higher the gate current discharges
the collector capacitor more rapidly. As a result, the dura- Selection of the capacitor is based on the IGBT input ca-
tion of the Miller’s plateau and the collector emitter voltage tail pacitance and current gain of the PUSH–PULL
are reduced. buffer. For sufficient decoupling between the gate emitter
voltage and the capacitor voltage , the selected capac-
A. The Shape Generator itor has to satisfy the condition
The key element of the proposed gate driver is a gate voltage
shape generator which provides a reference gate voltage with (29)
650
Fig. 8. Reference gate voltage slope versus gate voltage.
Fig. 9. Experimental set up.
Then, the inductance and resistance of the RLC circuit are
calculated from the desired natural frequency (27) and damping
factor (23)
(30)
(31)
As an example, we have calculated the reference gate voltage
slope versus gate voltage for selected parameters of the
circuit. The graph is depicted in Fig. 8. The gate voltage slope
is approximately constant, with deviation below 10%, for the
gate emitter voltage between 0 and 15 V.
VI. EXPERIMENTAL RESULTS
The experimental results are presented for an IGBT module
using a conventional (standard) gate driver, hereafter called
CGD, and the proposed gate driver, with feed-forward control,
hereafter called FGD. The IGBT used in the tests is a soft punch
through (SPT) dual module, rated at 1200 V and 300 A. Each
IGBT in the module consists of four parallel connected chips.
The IGBT was driven by a conventional and the proposed gate
driver. The turn on performances were analysed and compared.
The test set up is based on a step down converter depicted in
Fig. 9, which represents one leg of a three phase inverter that
operates in hard-switching conditions.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
Fig. 10. Waveforms of the collector emitter and gate emitter voltage and col-
lector current with a conventional gate driver (CGD) and the proposed feed-for-
ward gate driver (FGD).
The collector emitter voltage was measured as a voltage
between auxiliary emitter (point 7) of the lower IGBT, and the
module output terminal (point OUT). The voltage was mea-
sured with a calibrated passive high-voltage probe, with suffi-
cient bandwidth of 400 MHz. The collector current was mea-
sured by a Pearson Current Monitor 9850 and a custom designed
bus bar. The collector emitter voltage and collector current were
recorded and turn on losses calculated. The tests were done at
the junction temperature of 125 C.
Fig. 10 shows turn on waveforms of the collector emitter and
gate emitter voltage, and collector current of the IGBT driven
by a conventional gate driver (CGD), on Fig. 10(a), and the pro-
posed feed-forward gate driver (FGD), on Fig. 10(b). The bus
voltage was set at nominal value of 600 V and the load current
at 300 A. The parameters of the drivers were adjusted to have
a same reverse recovery current in both cases. Turn on gate re-
sistor in CGD was selected to value of 5 . The waveforms of
the collector current and collector emitter voltage were recorded
and losses were calculated.
Fig. 11(a) shows the collector emitter voltage and collector
current waveforms for different turn on gate resistor of 3, 5,
GRBOVIC: IGBT GATE DRIVER
Fig. 11. Turn on waveforms for different parameters using the (a) CGD and (b)
the proposed FGD.
and 11 . It is clearly noticeable that the gate resistor simul-
taneously affects the both, and . In the con-
trast to this, the proposed gate driver controls indepen-
dently on the . From these waveforms we may observe
that the is almost constant at different level of . lower during the Miller’s plateau and last phase of the commu-
The current slope was indirectly controlled by slope of the gate
emitter voltage, which was adjusted by the capacitor in the
gate voltage shape generator (depicted in Fig. 7). The capaci-
tance was 10, 15, and 22nF, respectively.
Comparison of the current and voltage waveforms is depicted
in Fig. 12. As we may observe, the waveforms of the collector
currents are almost overlapped; same slope and magni-
tude of the reverse recovery current . Thus, the area between
the waveforms of collector emitter voltages represents the dif-
ference in turn on losses. This clearly shows the benefit of the
proposed gate driver over a conventional gate driver.
Fig. 13 shows the turn on losses versus the reverse recovery
current for a conventional and the proposed gate driver. As it
may be observed from the graph, the turn on losses obtained by
the proposed gate driver are significantly lower compared to the
losses obtained by the conventional gate driver. The difference
651
Fig. 12. Comparison of the collector emitter voltage and collector current with
a CGD and the proposed FGD.
Fig. 13. Turn on switching losses versus reverse recovery current for a CGD
and the proposed FGD.
in the turn on losses varies from 25% to 45 %, depending on the
reverse recovery current.
Typical waveforms of the gate emitter voltage and gate cur-
rent are depicted in Fig. 14. Conventional gate driver waveforms
are given in Fig. 14(a). The gate current exhibits a large peak
at the beginning of the commutation, whereas it is significantly
tation. The Miller’s plateau duration is approximately 1.5 s.
In contrast to this, the gate current of the proposed gate driver
exhibits two peaks; the first one at the beginning of the com-
mutation and the second one which corresponds to the Millers
plateau. We may observe significant reduction of the Miller’s
plateau duration, which is now approximately 0.75 s.
VII. CONCLUSION
This paper presented a novel IGBT gate driver having capa-
bility to control independently and at turn on
with an inductive load. The turn on losses and reverse recovery
current for a conventional and the proposed driving strategy has
been analysed, compared and presented in the paper. The most
important features of the proposed gate driver could be summa-
rized in the following.
652
Fig. 14. Gate current and gate emitter voltage with a CGD and the proposed
FGD.
• The collector current slope is controlled by pre-
defined slope of the gate voltage during the col-
lector current rising phase. Consequently, the reverse re-
covery current is controlled by control.
• The collector emitter voltage slope and the
Miller’s time are controlled independently from the col-
lector current slope by means of inherent injection of the
gate current during the collector emitter fall phase.
• Independent control of these two allows minimisation of
the reverse recovery current and total turn on losses.
The proposed solution does not need any active or passive
feedback and current measurement circuits. It makes the gate
driver more robust and reliable. An experimental set up had been
made and several tests were carried out in order to verify the
proposed gate driving strategy and compare it with the conven-
tional gate driving strategy. The turn on losses and reverse re-
covery current were measured and compared. The clear benefit
of using the proposed gate driver is a significant reduction in the
turn on losses of 25% to 45% compared to the conventional gate
driver.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008
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Petar J. Grbovic (M’05) received the B.Sc. and
M.Sc. degrees from the School of Electrical En-
gineering, University of Belgrade, Serbia, in 1999
and 2005, respectively, and is currently pursuing the
Ph.D. degree at the Laboratoire d’Électrotechnique
et d’Électronique de Puissance de Lille, l’Ecole
Centrale de Lille, France.
From March 1999 to February 2003, he was
an R/D Engineer with RDA Co, Belgrade. From
November 2000 to June 2001, he was a Consulting
Engineer with CESET Italy (a division of Emerson
Appliance Motors Europe). From March 2003 to April 2005, he was with
the R&D Department, PDL Electronics, Ltd., Napier, New Zealand. Since
April 2005, he has been working with Schneider Toshiba Inverter Europe,
Pacy-Sur-Eure, France, as a Senior R&D Engineer and Power Electronics
Innovation Group Leader. The focus of his research is on high power IGBTs
and JFET SiC active gate driving, advanced power converters topologies and
switching power devices, and EMC problems in power electronics.