ASIC

PROJECT REPORT- SPECTRUM

ANALYZER

RENATO ALVAREZ – JUAN VALVERDE

MASTER ESECA- M2
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INDEX
1. OBJECTIVES...............................................................................................2
1.1 GENERAL OBJECTIVE...................................................................................................2
1.2 SPECIFIC OBJECTIVES..................................................................................................2
2. DEVELOPING THE SYSTEM.........................................................................2
2.1 Choosing the FPGA and the Architecture...................................................................2
2.2 Architecture of the system.........................................................................................3
2.2.1. Components of the system...................................................................................5
2.2.1.1. Clock Wizard..................................................................................................5
2.2.1.2. Processor System Reset.................................................................................5
2.2.1.3. Micro-Blaze controller...................................................................................7
2.2.1.4. Pheripherical Bus Controller – AXI Interconnect...........................................8
2.2.1.5. RAM memory.................................................................................................8
2.2.1.6. General Purpose Input – Output.................................................................10
2.2.1.7. Analog to Digital Converter Driver / XADC Wizard......................................11
2.2.1.7.1. Configuration of the ADC Driver............................................................13
2.2.1.7.2. Resolution of the analog to digital conversion......................................14
2.2.1.7.3. Analog to Digital conversion..................................................................14
2.2.1.8. AXI Timer.....................................................................................................16
2.2.1.8.1. Configuration of the AXI Timer as PWM...............................................16
2.2.1.8.2. Configuring registers TLR 0∧TLR 1 for period and duty cycle of PWM.. .
19
2.2.2. Results.................................................................................................................23
2.2.2.1. Flow Diagram...............................................................................................23
2.2.2.2. C Code..........................................................................................................24
2.2.2.3. Laboratory measurements..........................................................................26
3. BIBLIOGRAPHY........................................................................................27
4. ANNEXES.................................................................................................28
4.1 Constraints file..........................................................................................................28

SPECTRUM ANALYZER - ASIC

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1. OBJECTIVES
1.1 GENERAL OBJECTIVE

1.2 SPECIFIC OBJECTIVES

 To develop a specific ASIC architecture
 To understand how to change code between C/C++ to VHDL with Catapult
 To use the different type of architectures in Catapult to improve the design
 To follow the customer specification rules

2. SPECTRUM ANALYZER ARCHITECTURE

2.1 BRIEF DESCRIPTION
2.2 COMPONENTS

2.2.1. Modulator

2.2.1.1. Description
Inside the modulator we have the sequential modulator and a ROM memory containing the
data of a cosine function, this entity simulates the Analog to Digital Converter in order to
test the interface and all the circuits inside the complete design.

The sequential modulator produces all the addresses to access the data which is steed in
the ROM memory, this block has a synchronization input in order to send address 768d with
a value of 0d when this input “sync_in” is enabled.

The ROM is a memory with 10-bit (1024) addresses and a word of 10-bit (1024 with sign
-512 TO 511).
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Cosine Memory Data

600

400

200
Data

0
3 5 7 1 111 6 52 192 7 33 273 8 14 354 8 95 435 9 76 517 0 57 598 1 38 679 2 19 75
-200

-400

-600
Address

Figure 1. Data inside the memory ROM

2.2.1.2. Block diagram

Figure 2. Modulator clk Block Diagram

rst_n
sync_in
Modulator
 
Table I. Modulator 10 Inputs/Outputs
description data

Signal Type Description / Value

 
rst_n Input If “0” resets modulator and sends 0 to the data output.
clk Input System clock of 50 MHz
If “1” sends zero from data, if “0” sends the waveform
sync_in Input
data value read from the memory
10-bit output, which sends the data stored in the
data Output
memory, according to the sync_in signal.

2.2.1.3. Simulation

On the next graphic, we can see how the modulator sends the data data[9:0] which is
stored inside the memory ROM to de data output, the address addr[9:0] is an inside signal
which allows us to access to the memory ROM in order to take the stored data out from the
modulator.
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Figure 3.Modulator Simulation

2.2.2. Mixer
2.2.2.1. Description
The mixer block has two inputs, the first one comes from the modulator, the other
one is an input with some complex numbers [1, -i, -1, i] in order to obtain the two data
outputs that go directly to the FFT, one output is for real numbers and the other for
imaginary, since the task of the mixer is to combine both real and imaginary frequency
generators. We did this arrangement in order to couple the modulator output to the FFT. In
fact the second input of the mixer is the complex frequency generator.

Figure 4. Mixer behavior

First, the mixer takes the first data x0 which is purely real, mixes this with the first
element of the constant array [1, -i, -1, i] and send it for the real output because the
multiplication is between 2 real numbers. As a second step, the mixer takes the first data x1,
mixes this with the second element of the constant [1, -i, -1, i] and send it for the imaginary
output because the result of the multiplication is imaginary. This process continues as many
times as there are samples in the input.

2.2.2.2. Block diagram

Figure 5. Mixer block diagram

clk
rst_n
data 10
Table II. Mixer Mixer Inputs/Outputs
 
description
20
data_ri

 
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Signal Type Description / Value

rst_n Input If “0” resets modulator and sends 0 to the data output.
clk Input System clock of 50 MHz
10-bit input, in which we receive the data from the
data Input
modulator.
20-bit output, which sends the result of the mixer
operation, this output sends the data to the FFT, the 10
data_ri Output
LSB bits are the real number and the 10 MSB bits are the
imaginary one.

2.2.2.3. Simulation
In the next figure we can observe how the mixer works, it takes the data[9:0] from the input
which is purely real combines it with the imaginary generator and sends this complex
number to the 20 bit output in a fixed arrangement, the first 10 LSB are the real ones,
phase_ri RE on the plot and the second 10-bits MSB are the imaginary ones, phase_ri IM on
the plot.

2.2.3. Digital signal processing and Fast Fourier Transform

After the mixer, for the signal processing unit, we need to develop a system with three
stages: fist, we have a filter, second, is the decimation and, in the third stage, we have the
FFT.
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Figure 6. Block diagram to develop the digital signal processing in Catapult

For filtering we will use standard FIR and symmetric filters with decimation, and for the FFT a
radix 2 FFT of 64 points algorithm will be used.

2.2.3.1. FIR

The finite impulse response (FIR) filter is used in many digital signal processing (DSP) systems
to perform signal preconditioning, antialiasing, band selection, decimation/interpolation,
low-pass filtering, and video convolution functions.

Conventional FIR
The next figure shows a conventional 8-tap FIR filter architecture. This filter has eight 8-bit
registers arranged in a shift register configuration.

Figure 7. Conventional FIR application

Symmetric FIR
For a linear phase response FIR filter, the coefficients are symmetric around the center
values. This symmetry allows the symmetric taps to be added together before they are
multiplied by the coefficients. Taking advantage of the symmetry lowers the number of
multiplies from eight to four, which reduces the circuitry required to implement this filter.
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Figure 8. Adding Symmetric Taps Before Multiplication

Catapult code for filtering

===================================================================================
// Filename: c_filter.hpp
// Description:
// Version: 1.0
// Revision: none
// Compiler: g++
// Author: Mathieu Lebon (ML),
// Company: Thales Alenia Space
===================================================================================

#ifndef __C_FILTER__
#define __C_FILTER__

#ifndef __SYNTHESIS__
#include <cstdlib>
#include <fstream>
#include <iomanip>
#include <sstream>
using namespace std;
#endif

#include <ac_int.h>

#ifdef __SYNTHESIS__
#undef assert
#define assert(x)
#endif

enum filter_mode {
standard,
symmetric
};

//=================================================================================
// Class: c_filter
// Description:
// mode = standard or symmetric
// t_data = type of filter input data
// t_acc = type of filter accumulator
// size = Number of taps
//=================================================================================
template<filter_mode mode, typename t_data, typename t_acc, int size>
class c_filter {

static const int size_div2 = size/2; // Number of taps divided by 2

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t_data reg[size]; // TAPS
t_acc acc; // Accumulator

public:
// ------------------------------------------------
// TAPS registers initialization
// Reset TAPS to 0
// ------------------------------------------------
c_filter() {
// ...
for(int i = 0; i < size ; i++)
reg[i] = 0; //initialization to zero for taps
}

// ------------------------------------------------
// Filter main process
// ------------------------------------------------
template<typename t_coef>
void process(t_data in, const t_coef * coef, t_acc & out) {
shift(in);
if(mode == symmetric) {
mac_sym(coef);
} else {
mac(coef);
}
out=acc;
}

private :
// ------------------------------------------------
// Shift TAPS registers
// ------------------------------------------------
void shift(t_data in) {
// ...
for(int i = size - 1; i > 0; i--)
{
reg[i] = reg[i - 1];
}
reg[0] = in;
}

// ------------------------------------------------
// Multiply Accumulate for symmetric filter
// ------------------------------------------------
template<typename t_coef>
void mac_sym(const t_coef * coef) {
// ...
t_data out; // la sortie
acc= 0;
for (int i = 0; i < size-1; i++) {
acc+= coef[i] * (reg[size-1-i] + reg[i]);
}
out = acc;
}

// ------------------------------------------------
// Multiply Accumulate for standard filter
// ------------------------------------------------
template<typename t_coef>
void mac(const t_coef * coef) {
// ...
acc= 0;
for (int i = 0; i < size; i++) {
acc += coef[i] * reg[i];
}
}
}; // ----- end of class c_filter -----

#endif
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2.2.3.2. FFT

DFT is most widely used technique for converting the samples from time domain to
frequency domain. Fast Fourier Transform performs this operation at a very fast rate and
hence it is known as a n efficient technique for calculating the DFT of signals. It does these
tasks with less overhead in the calculation of complex terms.

Figure 9. Butterfly diagram for FFT designed with a radix 2 FFT of 64 points

Catapult implementation of this FFT

//========================================================================
// Filename: c_fft.hpp
// Description:
// Version: 1.0
// Revision: none
// Compiler: g++
// Author: Mathieu Lebon (ML),
// Company: Thales Alenia Space
// =======================================================================

#ifndef __C_FFT__
#define __C_FFT__
#ifndef __SYNTHESIS__
#include <cstdlib>
#include <fstream>
#include <iomanip>
#include <sstream>
using namespace std;
#endif

#include <ac_int.h>
#include "rnd.h"
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using namespace sp_rnd;

#ifdef __SYNTHESIS__
#undef assert
#define assert(x)
#endif

// =======================================================================
// Class: c_fft
// Description:
// =======================================================================
template<int size, typename t_data_mem, typename t_coef, int
butterfly_lsb_delete>
class c_fft {
t_data_mem mem[size];
static const int size_log2 = ac::log2_ceil<size>::val;
static const int size_div2 = size/2;
typedef ac_complex<int32> t_data_mult;

public:
// ------------------------------------------------
// No internal memory initialization
// ------------------------------------------------
c_fft() {
FFT_Init_Loop:
for ( int i = 0; i < size; i += 1 ) {
t_data_mem dc;
mem[i] = dc;
}
}

// -----------------------------------------------------
// Bit reverse
// -----------------------------------------------------
template<int qt, bool s>
ac_int<qt,s> bit_reverse(ac_int<qt,s> x) {
// ...
x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
return((x >> 16) | (x << 16));
unsigned int v = x;
unsigned int r = v & 1;
const int CHAR_BIT = 8;
int s = sizeof(x) * CHAR_BIT - 1;
for (x >>= 1; x; x >>= 1)
{
r <<= 1;
r |= x & 1;
s--;
}
r <<= s; // shift when v's highest bits are zero
return x;
}

// -----------------------------------------------------
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// Read input channel and write data to process memory

// -----------------------------------------------------
template<typename t_chan>
void read(t_chan & in) {
// Bit reverse read
// ...
t_data_mem mem_reversed;
// in = mem_reversed;
FFT_Read_Loop:
for ( int i = 0; i < size; i += 1 ){
ac_complex<int14> d = in.read();
mem_reversed = bit_reverse(d);
mem[i] = mem_reversed;
}
printf("Reading finished");
}

// -----------------------------------------------------
// Copy result memory to output memory
// -----------------------------------------------------
void write(t_data_mem * mem_out) {
// ...
FFT_Write_Loop:
for ( int i = 0; i < size; i += 1 )
mem_out[i] = mem[i];
//*(mem_out + i) = mem[i];
printf("Writing finished");
}

void process(const t_coef * coef) {

int32 mask1 = 0;
int32 mask2 = - 1;
int32 mask3 = 1;
int32 temp1;
int32 temp2;
int32 index_low;
int32 index_high;
int32 n2 = size;
int32 index_coef;

//################## STAGES LOOP ##################

STAGE_LOOP:
for (int i=0; i<size_log2; i++) {
n2 = n2 >> 1;
index_coef = 0;
printf("Starting loop...");
//################## BUTTERFLY LOOP ##################

BUTTERFLY_LOOP:
for (int j=0; j<size_div2; j++) {
// Update data address

temp1 = j & mask1;

temp2 = (j & mask2) << 1;
index_low = temp1 | temp2;
index_high = index_low | mask3;

// Memory Read
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t_data_mem data_high = mem[index_high];

t_data_mem data_low = mem[index_low];
t_coef data_coef = coef[index_coef];
t_data_mem x;
t_data_mem y;
butterfly(data_high,data_low,data_coef,x,y);

// Memory write
mem[index_high] = x;
mem[index_low] = y;

// Update coef address

if (i != 0 ) {
index_coef = index_coef + n2;
if (index_coef == size_div2) index_coef = 0;
}
}
mask1 += mask3;
mask2 = mask2 << 1;
mask3 = mask3 << 1;
}
printf("Butterfly finished...");
}

void butterfly(t_data_mem data_high, t_data_mem data_low, t_coef coef,

t_data_mem & res_high, t_data_mem & res_low) {
t_data_mult data_mult = mult(data_high,coef);

// Sum
res_high.r() = data_low.r() - data_mult.r();
res_high.i() = data_low.i() - data_mult.i();
res_low.r() = data_low.r() + data_mult.r();
res_low.i() = data_low.i() + data_mult.i();
}

t_data_mult mult(t_data_mem data, t_data_mem coef) {

int32 a_mult, b_mult, c_mult, d_mult;
int32 a_mult_rc, b_mult_rc, c_mult_rc, d_mult_rc;

// Multiplication
a_mult = data.r() * coef.r();
b_mult = data.i() * coef.i();
c_mult = data.r() * coef.i();
d_mult = data.i() * coef.r();

// Round
rnd<butterfly_lsb_delete>(a_mult, a_mult_rc);
rnd<butterfly_lsb_delete>(b_mult, b_mult_rc);
rnd<butterfly_lsb_delete>(c_mult, c_mult_rc);
rnd<butterfly_lsb_delete>(d_mult, d_mult_rc);

// Partial sum
t_data_mult res;
res.r() = (a_mult_rc - b_mult_rc);
res.i() = (c_mult_rc + d_mult_rc);
return res;
}
}; // ----- end of class c_fft -----
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#endif

2.2.3.3. Block
clk in_rsc_lz
19 mem_out_r_rsc_data_in
rst_n
in_rsc_z 10 5 mem_out_r_rsc_addr
in_rsc_vz mem_out_r_rsc_we
DIGITAL mem_out_r_rsc_triosy_lz
SIGNAL mem_out_i_rsc_data_in
19
PROCESSING mem_out_i_rsc_addr
5
mem_out_i_rsc_we
mem_out_i_rsc_triosy_lz

diagram
Figure 10. DSP block diagram

Table III. DSP Inputs/Outputs description

Signal Type Description / Value

rst Input If “0” resets the DSP and sends 0 to the data output
clk Input System clock
in_rsc_z Input 20-bit input, 10-bits for real and 10-bits for imaginary
in_rsc_vz Input If “1” the DSP is enabled, if “0” the DSP is disabled
in_rsc_lz Output
19-bit output, this output gives the data from the FFT
mem_out_r_rsc_data_in Output
transformed
mem_out_r_rsc_addr Output 5-bit output, this output gives the address direction
If “1” the Write Enable is enabled and the data could
mem_out_r_rsc_we Output be stored in an external memory , if “0” the Write
Enable is disabled
When the FFT analysis ends and the data is sent to
mem_out_r_rsc_triosy_lz Output the external memory, a rising pulse is sent through
this output
19-bit output, , this output gives the data from the
mem_out_i_rsc_data_in Output
FFT transformed
mem_out_i_rsc_addr Output 5-bit output, this output gives the address direction
If “1” the Write Enable is enabled and the data could
mem_out_i_rsc_we Output be stored in an external memory , if “0” the Write
Enable is disabled
When the FFT analysis ends and the data is sent to
mem_out_i_rsc_triosy_lz Output the external memory, a rising pulse is sent through
this output
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2.2.3.4. Simulation

Catapult software give us a VHDL file with an implemented code for the FFT, in order to test
the correct work of this block, we introduce the code to Vivado environment and we make a
simulation, we can observe the behavior around this complex entity:

Figure 11. DSP Simulation

Figure 12. Waveform when the DSP finish saving the data in memory

We need to take care about the next signals and the process will be secure in order to
maintain the stability of the system. First, we need to activate the in_rsc_vz bit after we are
going to send the real and imaginary data to the in_rsc_z. Second, when the mem_out_r_rsc
and mem_out_i_rsc_we give us a zero, the data is available to store inside an external
memory. Finally, When the DSP analysis finish and all the data was stored inside a memory,
the DSP sends a rising pulse for the mem_out_r_rsc_triosy_lz and mem_out_i_rsc_triosy_lz.

2.2.4. FIFO

2.2.5. UART

It is a communication hardware interface for universal serial asynchronous receiver-

transmitter communication in which the data format and transmission speeds are
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configurable. The electric signaling levels and methods are handled by a driver circuit
external to the UART.

2.2.5.1. Block
clk rxd diagram
rst_n txd
Figure 13.
tx_data(7:0) 8
UART block diagram
tx_we 8 rx_data(7:0)
cfg_baud_rate(1:0) 2 rx_ready
UART
cfg_par_en par_error
Table cfg_par_pol tx_busy IV. UART
cfg_data_7_8
cfg_stop_1_2

Inputs/Outputs description

Signal Type Description / Value

rst_n Input If “0” resets the DSP and sends 0 to the data output
clk Input System clock 10Mhz
rxd Input Serial data input
txd Output Serial data Output
rx_data(7:0) Output Received data. For 7-bit word transmission, the MSB
(bit 7) is ignored.
The data may change when rx_ready is at '0' but will
be stable when rx_ready = '1'
rx_ready Output Flag indicating that new data is available on the bus
rx_data (7: 0) = '1'
par_error Output Parity error flag. Active at '1'. Inactive when
cfg_par_en = '0'
tx_data(7:0) Input Data to be transmitted. For 7-bit data transmission,
the MSB (bit 7) is ignored. The data is considered
when tx_we = '1'
tx_we Input Request for transmission of the data present on the
bus tx_data (7: 0). Tx_we will only be activated by
the user when tx_busy is set to '0'.
tx_busy Output Flag indicating that the transmission part is not
available for the transmission of data.
cfg_baud_rate(1:0) Input Configuration of the transmission baud
“00” = 1200 bauds
“01” = 2400 bauds
“10” = 4800 bauds
“11” = 9600 bauds
cfg_par_en Input Enabling transmission of parity '0' = Parity not
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Signal Type Description / Value

transmitted '1' = transmitted parity
cfg_par_pol Input Convention for the calculation of parity '0' = Even
parity (even) '1' = odd parity (odd)
cfg_data_7_8 Input Number of bits transmitted '0' = Transmission of 7-bit
words '1' = Transmission of 8-bit words
cfg_stop_1_2 Input Number of stop bits '0' = 1 stop bit
'1' = 2 stop bits

2.2.5.2. Simulation

In order to simulate the complete system, we created a testbench to control this block.

Figure 14. USART waveform simulation

We can see how this block is working, for 9600 bauds one byte takes a little more than 1
millisecond to be send on the txd signal. When we have an 8-bit data to send through the
UART, we need to give a rising edge to the tx_we in order to activate the device, after that,
tx_busy changes the state to one . When the UART finish to send the 8-bit data, the signal
tx_busy changes the state to zero.

3. SIMULATION
4. SYNTHESIS PLACEMENT AND ROUTING
5. CARD TEST