NANOMETRICAL DEVICES - MOSFET SOI AND SOI HI-K in Synopsys Sentaurus

UNIVERSIDAD SAN FRANCISCO DE QUITO
Nano electronics
201720.MN2.4533 - MNEL 6060 Nanometrical Devices – Lionel Trojman
NANOMETRICAL DEVICES
WORK 2: MOSFET SOI AND SOI HI-K
NAME: JUAN VALVERDE
CODE: 00204278
July 5, 2018
Approach:
• Simulate the Work 1 with SOI and compare on the same graph the
FOM and electrical parameter
• Apply 3 different VB for the IV and CV characteristic and comments the
results
•Simulate a high‐k gate stack (not UTEOT)
• For the calibration use the experimental data I provided by the prof.)
• Use the correct mobility model to calibrate and the charge to the interface
and in the bulk (see the User Guide of Sentaurus)
• Consider a junction overlap of 12.5nm on each side
• RS = 140.m
• VFB = ‐ 0.7V
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MOSFET SOI
Design
The SOI MOSFET technology (Silicon on insulator) use of a layered silicon–

insulator–silicon substrate in place of conventional silicon substrates to reduce
parasitic device capacitance improving performance. The silicon junction is
above an electrical insulator.
Doping and materials
Table 1.Materials and doping
Name Material Doping Peak

concentration
Susbstrate.channel Silicon BoronActiveConcentration 1e17
Susbstrate.bulk Silicon BoronActiveConcentration 1e15
Halo.source Silicon BoronActiveConcentration 1E21
Halo.drain Silicon BoronActiveConcentration 1E21
Source Silicon PhosphorusActiveConcentration 1E21
Drain Silicon PhosphorusActiveConcentration 1E21
Box SiO2
Spacer.Drain Si3N4
Spacer.Source Si3N4
Spacer.Dielectric.Drain SiO2
Spacer.Dielectric.Source SiO2
Gate PolySi PhosphorusActiveConcentration 1E21
tox SiO2
Measurements
The measurements for each device are given by the graphs:
For 0.05um we have the mesh design and doping:

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Figure 1. Meshing and dimensions for 0.05um SOI
For 0.1um and 0.2um
Figure 2. Meshing and dimensions for 0.1um and 0.2um SOI
For 0.5um and 1um
Figure 3. Meshing and dimensions for 0.5um and 1um SOI
Plots I -V with 3 different bulk voltages 0V, 0.5V and 1 V

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The next step to model a MOSFET device is simulate and extract the graphs and
data, for the analysis I use the Synopsys tool on the Inspector program for
extract the threshold voltage and the transconductance:
For 0.05um
Idrain [A]
Vgate [V]
Figure 4. I-V curve for SOI 0.05um
Extracting the measurements to a table for this first channel length:
Table 2. Table for Vht and Gm for 0.05um SOI with different Vbulk
L[um] Vb [V] Vth[V] Gm[S]

0.05 0 0.156514062393770 0.000453885157023828
0.05 0.5 0.126706239377036 0.0004452035653200
0.05 1 0.1413629338352899 0.000437735717120388
Table 3. Table for Ioff and Ion for 0.05um SOI with different Vbulk
L[um] Vb [V] Ioff[A] Ion[A]

0.05 0 0.000 0.000253885157023828
0.05 0.5 0.000 0.0002452035653200
0.05 1 0.000 0.000237735717120388
For 0.1um
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Idrain [A]
Vgate [V]
Extracting the measurements to a table for this channel length:

0.1 0 0.4937710510040818 0.0003518370772872448
0.1 0.5 0.4736210510040818 0.0003444857967578657
0.1 1 0.4984267474511825 0.0003344560382069559

0.1 0 0.0000000007710510 0.0002118370772872448
0.1 0.5 0.0000000000040818 0.0002144857967578657
0.1 1 0.0000000004511825 0.0002144560382069550
For 0.2um
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Idrain [A]
Vgate [V]

0.2 0 0.4976392634957996 0.0003104060270912515
0.2 0.5 0.4864049557920509 0.00030949614771
0.2 1 0.4729152868945998 0.000306408112012467

0.2 0 0.000000004976392 0.00018040602709125
0.2 0.5 0. 000000048640495 0.000189496147710
0.2 1 0. 000000047291528 0.0001864081120124
For 0.5um
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Idrain [A]
Vgate [V]

0.5 0 0.8110549194208858 0.000146860101022794
0.5 0.5 0.8927126245196715 0.0001508839299129376
0.5 1 0.8526958413131471 0.0001409849770253854

0.5 0 0.0000000008110549 0.0000814686010102279
0.5 0.5 0. 000000000624515 0.00008150883929912937
0.5 1 0. 00000000058411 0.00008140984977025385
For 1um
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Idrain [A]
Vgate [V]

1 0 1.02013369853776 6.0374322164819e-
05
1 0.5 1.00352931501883 6.6820742164819e-
05
1 1 0.78775137236301 6.48175771287502e-
05

1 0 0.00000000007766 4.0374322164819e-05
1 0.5 0.0000000000.0035 4.6820742164819e-05
1 1 -0.00000000003801 4.4817577128750e-05
Concluding this part, we can see the plots about the Voltage Vth as a function
of the technology:
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Figure 9. Vth for different SOI technologies with Vbulk-=0[V]
Figure 10. Vth for different SOI technologies with Vbulk-=0.5[V]

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Figure 11. Vth for different SOI technologies with Vbulk-=1[V]
We can see the tendency about the Vth, the threshold voltage increments
proportionally to the channel length L, for this situation the threshold voltage
can be changed with the bulk voltage of the MOSFET
About the threshold voltage, on the variation of the bulk voltage, I cannot see
really the tendency because I have three points only and the Vb=0v and the
Vb=1V on the same channel length is practically the same.
About the Gm, we can see the plots about Gm as a function of the technology:
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Figure 12. Gm for different SOI technologies with Vbulk-=0[V]
Figure 13. Gm for different SOI technologies with Vbulk-=0.5[V]

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Figure 14. Gm for different SOI technologies with Vbulk-=1V]
We can see the tendency about the Gm, the transconductance decrements
proportionally to the channel length L, for this situation the threshold voltage
can be changed with the bulk voltage of the MOSFET
About the Gm, on the variation of the bulk voltage, I cannot see really the
tendency because I have three points only and the Vb=0v and the Vb=1V on the
same channel length is practically the same.
Inverse capacitance
For this section, we need the data created by the script for capacitance, we need
to do some mathematical things based on a physical behavior:
We need to plot for each channel length with the next curves:
Plot:
𝐶𝑔𝑐 = −(𝐶𝑔𝑠 + 𝐶𝑔𝑑) (a)

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Plot:
−𝐶𝑔𝑏 (b)
Compare this plot with Cgg curve:
This curve is analyzed only on Vb=0V because it is a physic parameter:
For 0.05um, Vb=0V

Capacitance [F]
Vgate [V]
Figure 15. C-V curve for SOI 0.05um
For 0.1um, Vb=0V

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Capacitance [F]
Vgate [V]
For 0.2um, Vb=0V

Capacitance [F]
Vgate [V]
For 0.5um, Vb=0V

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Capacitance [F]
Vgate [V]
For 1um, Vb=0V

Capacitance [F]
Vgate [V]
Figure 19. C-V curve for SOI 1um
On these graphs we can view how the capacitance peak is increasing with the
channel length. On a SOI MOSFET device the capacitance is bigger than a
normal MOSFET because the SOI has a SiO2 box that increments this physic
parameter.
Capacitance density
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The curves for the capacitance density are given by:

Density of Capacitance [F/cm^2]
Vgate [V]
Figure 20. C-V curve for SOI 1um
For this section I can se that the curve is similar for all the lengths because the
dielectric material putting on the interface between the gate and the channel on all
the lengths is the same: SiO2.
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MOSFET SOI HI-K
High K means High dielectric, this dielectric provides a high capacity on low
space meaning MOSFET devices for high performance and low power
applications. This means a more complex construction of the gate, in our device
is constructed by three materials including the dielectric.
Figure 21. Gate of the MOSFET SOI HI-K
Doping and materials
Table 10.Materials and doping
Name Material Doping Peak

concentration
Susbstrate.channel Silicon BoronActiveConcentration 1e17
Susbstrate.bulk Silicon BoronActiveConcentration 1e15
Halo.source Silicon BoronActiveConcentration 1E21
Halo.drain Silicon BoronActiveConcentration 1E21
Source Silicon PhosphorusActiveConcentration 1E21
Drain Silicon PhosphorusActiveConcentration 1E21
Box SiO2
Spacer.Drain Si3N4
Spacer.Source Si3N4
Spacer.Dielectric.Drain SiO2
Spacer.Dielectric.Source SiO2
Gate.up TiN 1E21
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Gate.down HfO2
tox SiON
(Insulator 1)
Measurements
The measurements for this device are given by the graphs:
Figure 22. MOSFET SOI HI-K
Figure 23 MOSFET SOI HI-K

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For this design I can try to calibrate the experimental data obtained by the Professor
adjusting some parameters and the physics of this semiconductor device.
C-V curve:
First, I need to define the physics for the device adding to the test code the charges
on the interfaces (on the gate),
Figure 24. Physics code for charge on the interface
For calibrate the data I need to move the value of the tox thickness for the amplitude
of the capacitance of the simulate data, the first design had a 0.4nm of tox thickness,
the second 0.9nm of tox thickness and with the fine tuning the tox is 0.6nm now.
For the slope (incline) of the capacitance curve I need to move the charge between
the interfaces because the capacitive effect is involved along the gate, this effect is
given by the physics of the interfaces, I can change the value between 1E13 and
1E11.
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The experimental C-V data have been obtained by the professor in F/cm,
transforming to F (Faradios) and comparing with the simulate data:
Figure 25. C - V graph for Simulated and experimental data
This graph shows that the Simulation data and the experimental data are adjusted
nearly, on the other hand this curve could be fine tuning adjusted with a more
exhaustive analysis.
I – V curve
First, I need to define the physics for the device adding to the test code the charges
on the interfaces (on the gate) and the physics for recombination, mobility, etc.
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Figure 26. Physics code for charge on the interface and mobility, recombination, etc.
For calibrate the data I need to change between the different types of options on the
physics, and I need to move the charge between the interfaces because the charge
of the gate control the drain current and I can change the value of the resistor on the
drain and source terminals.
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The experimental I-V data have been obtained by the professor, comparing with the
simulate data:
Figure 27. I - V graph for Simulated and experimental data
I can see that the simulated and the experimental data amplitude are the same,
but the slope (incline) of the simulated curve could be more approximated with
fine tuning parameters, this procedure would be a little problematic because the
time that I need to experiment with the parameters.
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Results:
SOI:
We can see the tendency about the Vth, the threshold voltage increments
proportionally to the channel length L, for this situation the threshold voltage can
be changed with the bulk voltage of the MOSFET
About the threshold voltage, on the variation of the bulk voltage, I cannot see
really the tendency because I have three points only and the Vb=0v and the
Vb=1V on the same channel length is practically the same.
We can see the tendency about the Gm, the transconductance decrements
proportionally to the channel length L, for this situation the threshold voltage can
be changed with the bulk voltage of the MOSFET
About the Gm, on the variation of the bulk voltage, I cannot see really the
tendency because I have three points only and the Vb=0v and the Vb=1V on the
same channel length is practically the same.
On these graphs we can view how the capacitance peak is increasing with the
channel length. On a SOI MOSFET device the capacitance is bigger than a
normal MOSFET because the SOI has a SiO2 box that increments this physic
parameter.
About the capacitance density, I can see that the curve is similar for all the lengths
because the dielectric material putting on the interface between the gate and the
channel on all the lengths is the same: SiO2.
SOI HI-K:
For the calibration I can see that the simulated and the experimental data would
be approximated nearly with a little more analysis, and doing some fine-tuning
parameters, this procedure would be a little problematic because the time that I
need to experiment with the parameters. For educational purpose, the curves are
fine.

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UNIVERSIDAD SAN FRANCISCO DE QUITO

•Simulate a high‐k gate stack (not UTEOT)

The SOI MOSFET technology (Silicon on insulator) use of a layered silicon–

Doping and materials

Table 1.Materials and doping

Name Material Doping Peak

The measurements for each device are given by the graphs:

For 0.05um we have the mesh design and doping:

Figure 1. Meshing and dimensions for 0.05um SOI

For 0.1um and 0.2um

Figure 2. Meshing and dimensions for 0.1um and 0.2um SOI

For 0.5um and 1um

Figure 3. Meshing and dimensions for 0.5um and 1um SOI

Plots I -V with 3 different bulk voltages 0V, 0.5V and 1 V

Extracting the measurements to a table for this first channel length:

L[um] Vb [V] Vth[V] Gm[S]

L[um] Vb [V] Ioff[A] Ion[A]

Extracting the measurements to a table for this channel length:

L[um] Vb [V] Vth[V] Gm[S]

L[um] Vb [V] Ioff[A] Ion[A]

Extracting the measurements to a table for this channel length:

L[um] Vb [V] Vth[V] Gm[S]

L[um] Vb [V] Ioff[A] Ion[A]

Extracting the measurements to a table for this channel length:

L[um] Vb [V] Vth[V] Gm[S]

L[um] Vb [V] Ioff[A] Ion[A]

L[um] Vb [V] Vth[V] Gm[S]

L[um] Vb [V] Ioff[A] Ion[A]

Figure 9. Vth for different SOI technologies with Vbulk-=0[V]

Figure 10. Vth for different SOI technologies with Vbulk-=0.5[V]

Figure 11. Vth for different SOI technologies with Vbulk-=1[V]

Figure 12. Gm for different SOI technologies with Vbulk-=0[V]

Figure 13. Gm for different SOI technologies with Vbulk-=0.5[V]

Figure 14. Gm for different SOI technologies with Vbulk-=1V]

𝐶𝑔𝑐 = −(𝐶𝑔𝑠 + 𝐶𝑔𝑑) (a)

Compare this plot with Cgg curve:

This curve is analyzed only on Vb=0V because it is a physic parameter:

For 0.05um, Vb=0V

For 0.1um, Vb=0V

For 0.2um, Vb=0V

For 0.5um, Vb=0V

For 1um, Vb=0V

The curves for the capacitance density are given by:

MOSFET SOI HI-K

Figure 21. Gate of the MOSFET SOI HI-K

Doping and materials

Table 10.Materials and doping

Name Material Doping Peak

The measurements for this device are given by the graphs:

Figure 22. MOSFET SOI HI-K

Figure 23 MOSFET SOI HI-K

Figure 24. Physics code for charge on the interface

Figure 25. C - V graph for Simulated and experimental data

Figure 27. I - V graph for Simulated and experimental data

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