1.

set_colors -hierarchy_types all -cycle_color -depth all

2. sizeof_collection [get_ports ] --- Collection of ports
3. sizeof_collection [get_pins ] --- Collection of pins
4. sizeof_collection [get_cells * -filter {ref_name =~ *ULT*}]
5. sizeof_collection [get_cells * -filter {ref_name =~ *LVT*}]
6. sizeof_collection [get_cells * -filter {ref_name =~ *SVT*}]
7. change_selection [get_cells *TAP*] --- Highlight TAP cells
8. change_selection [get_cells *END*] --- Highlight END cells
9. change_selection [get_cells *BOUND*] --- Highlight BOUND
10. change_selection [get_cells SPARE_lo*] ------> it will highlight spare cells
11. change_selection [get_hier_cells ENDCAP*] ---> it will highlight the ENDCAP cells
12. change_selection [all_macro_cells ] ---Select all macros
13. change_selection [all_registers]
14. change_selection [get_cells -hierarchical -filter "ref_name=~*FSDP*"] ----> it will
highlight the flops.
15. change_selection [get_cells -hierarchical -filter "ref_name=~*TIE*"] ---> it will
select the Tie off cells
16. change_selection [ get_cells -hierarchical -filter "design_type == macro"] ----> it
will select all macros in the design
17. get_attribute [get_design] height --- showing height of the design
18. get_attribute [get_design] width
19. get_attribute [get_core_area] area
20. get_attribute [get_selection] height --- showing selection object height
21. get_attribute [get_selection] width
22. get_attribute [get_selection] bbox
23. get_attribute [get_selection ] origin ----> it will give origin of selected cell.
24. get_attribute [get_shapes -of_objects [get_pins <pin_name> ]] mask_constraint ---->
it will show the mask_name of the macro internal pin.
25. get_attribute [get_pins -of_objects [get_selection ]] name ----> it will show the pin
names of particular cells.
26. compute_area [get_attribute [get_selection] bbox]
27. lindex [get_attribute [get_port dfs_clk] location]
28. report_design – it will give design info.
29. all_macro_cell --- it will give all macro names
30. get_cells -hierarchical -filter "is_hard_macro" -------> it will also gives macro
names…(it is accurate, use this command)
31. get_cells -hierarchical -quiet -filter "is_hard_macro == true || is_io == true" ----> it
will also gives macro names…
32. get_attribute -name boundary -objects [current_block] -------> it will give all
boundaries(llx lly, lrx lry, urx ury, ulx uly) of the block
33. compute_area [get_attribute -name boundary -objects [current_block]] -------> it
will give the total area of the block.
34. get_attribute [current_design] name -----> it will give tile name.
35. save_block -as <block_name>/<place or cts> ------> it will save the design.
36. save_interactive_design -design <design_name> --------> it will save the design...
 37. get_lib_cells -of_objects [get_cells <Cell_Name>] ---> find out the library cell
used by particular cell.
38. get_attribute [get_ports -filter "direction == in" ] name --------> it will give the
names of all input ports
39. set_fixed_objects [get_selection] -unfix ------> unfix the selected object.
40. report_placement -hard_macro_overlap ----> it will check the overlapping of
macros…
41. get_attribute [get_selection] layer.pitch ----> it will give the pitch value of the
selected net.
42. get_attribute [get_layers M2/M3] -name pitch/min_width/min_spacing ------> it will
give the values
43. set_attribute [get_cell <cell-name>] origin {llx lly} ------->it will place the macro to
the respected location.
44. get_attribute [get_cells <cell_name>] ref_name
45. set_annotated_delay -net <delay(20)> -from <X1/Z> -to <X2/A> --------> it will
specify the delay to the particular net.
46. get_lib_cells -of_objects [get_cells -hierarchical -filter "@ref_name =~ *BUF* &&
is_physical_only == FALSE"] ----> it will print all library buf cells
47.

1. Macro name list

foreach_in_collection cell [get_cells -hier -filter "@is_hard_macro==true" ] {
set name [get_attribute $cell full_name]
echo $name >> inst_list.txt
}
2. Particular cell identify purpose.
get_flat_cells -hierarchical -filter [get_cell "ref_name == *HDPLVT08_FILL_Y2_3*"]
3. Checking feedthroughs
check_feedthroughs -unused_feedthroughs -reused_feedthroughs -net_constraints -
topo_constraints
4. change_selection [ get_timimg_paths - from <start> -to <end> ]
5. Pin violations
check_pin_placement -shorts true -missing true -pin_spacing true -wide_track true -
wire_track true -self
6. Creating blockages
create_placement_blockage -name <blockage_name> -boundary { {llx lly} {urx ury} } -type
{hard/partial/soft} -blocked_percentage <value> ----> it will add the placement blockage….
create_placement_blockage -name b1 -type partial -boundary {{160.6260 -381.1200}
{193.8000 -283.6800}} -blocked_percentage 30
create_placement_blockage -type soft -boundary {{-326.3820 -494.4010} {-208.6755 -
443.6420}}
create_channel_partial_blockages -percent_util 50 -buffer_only -channel_width 20 -verbose
7. Creating bounds
create_bound -name bpm -type soft -boundary {{-53.5800 75.3600} {-12.4830 115.4400}}
[get_flat_cells bpm/*]
Report_bounds --->it gives the bounds reports…
8. Creating routing guide
create_routing_guide -name rguide4 -boundary {{-192.4045 254.0480} {-119.2040
100.4710}} -horizontal_track_utilization 75 -vertical_track_utilization 75 -layers {M1 M2
M3 M4 M5 M6 M7 M8 M9 M10}
9. Pin-constraints
check_pin_placement -missing true -pin_spacing true -shorts true -wide_track true -
wire_track true -self -filename ../../../check_pinplacement.rpt
write_pin_constraints -file_name ../../../write_pin_constraints.rpt -from_existing_pins -self -
physical_pin_constraint {layer |sides |offset}
read_pin_constraints -file_name ../../../write_pin_constraints.rpt
place_pins -self
10. Removing overlays
change_selection [get_cells -filter "name=~ *ovly*" -hier]
set_attribute [get_selection ] status placed
remove_physical_objects -remove_disconnected
11. Save def
write_def -objects [get_selection ] ~/move_port.def
read_def ~/move_port.def
12. Moving cells, pushdowns as per offset values
set_fixed_objects [get_ports droopdetected] -unfix
set_fixed_objects [get_ports dfs_clk] -unfix
set_fixed_objects [get_cells droopdetect3_ROOT_BUF__PUSHDOWN ] -unfix
move_objects -delta {-209.88 279} -simple -force
write_def -objects [get_selection ] ~/move_port.def
read_def ~/move_port.def
13. Macro orientation should only be: MX MY R0 R180.
get_attribute [get_cells -quiet -hierarchical -filter "design_type == io_pad || design_type == io
|| design_type == macro"] orientation
14. IO buffers are inserted on all input signals
Visual check:
change_selection [get_ports * -filter "direction==in&&full_name!~VDD* &&
full_name!~VSS && full_name!~*FEED*"]
15. All IO pins in tile are placed and on track.
get_ports * -filter "physical_status == unplaced"
Return value should ONLY have Power/Gound net names, no signal pins

16. Keep-Out Margin

create_keepout_margin -type hard -outer {left bottom right top} ------>it will add the halo
create_keepout_margin -type soft -outer {0.5 0.5 0.5 0.5} [all_macro_cells] ----> it will
add halo..
create_keepout_margin -type hard -outer {left bottom right top} [get_cells -within {{llx lly}
{urx ury}} -filter "is_physical_only == false"] -----> it will use for cell padding.
report_keepout_margin ------> it will shows the kepout margin info..
sizeof_collection [get_keepout_margins ] ---> it will give the count of halos..
get_keepout_margins -of [get_cells -hierarchical] -type hard ---> it returns keepout margins
of type 'hard' from all the cells in the design
remove_keepout_margins [get_keepout_margins ] ----> removes all the halos in curren
block..
17. GroupPath
group_path -from [<all_registers/all_macro_cells/get_cells -hierarchical -filter
"is_hard_macro ">] -to [<all_registers/all_macro_cells>] -name <name> -weight <value> ----
> it will create the path groups according to the paths which we give……
group_path -name SOCCLK -weight 4
group_path -name reg_to_macro -from [all_registers ] -to [get_cells -hierarchical -filter
"is_hard_macro "] -weight 8 -priority 4
group_path -name macro_to_reg -from [get_cells -hierarchical -filter "is_hard_macro " ] -to
[all_registers ] -weight 7 -priority 3
group_path -name grp2 -from {
sdma1_body/dma_register/dma_reg_pub/dma_active_fcn_id_reg_2_ } -weight 6
18. Locked cells
set_placement_status locked [get_cells <cell names>] --------------> it will lock the particular
cells (Note: we can use unplaced/placed/legalize_only/fixed/application_fixed options instead
of locked…)
18. get_cells
get_cells -quiet -filter "is_physical_only == true" ------------> it will give physical cells..
get_cells -quiet * -hier -filter "is_integrated_clock_gating_cell == true" -----> it will show
the integreted_clock_gating cells .
get_attribute [get_via_defs -tech [get_techs] -filter "name =~ *_DFM_P*_VIA*"] name -----
> it will show the DFM VIA names
get_pins -of_objects [get_nets -of_objects [get_pins [pin_name]]] ---------------> it will give
drver and sinks of the nets.
sizeof_collection [get_cells -of_objects [get_nets <net_name> ] -------------> it will give
count of the fanouts of that particular net.
19. Connect and Disconnect
add_tie_cells -objects <$cells_to_tie_off > -tie_high_lib_cell
ts07nxpllogl08hdl057f/HDBLVT08_TIE1_1 -tie_low_lib_cell
ts07nxpllogl08hdl057f/HDBLVT08_TIE0_1 ------> it will connect the tile cells.
connect_net <netname> <pin_name> ----> it will connect the net to particular pin.
Disconnect_net <net_name> <pin_name> -----> It will discoonect the net to particular pin
connect_pins -incremental -driver <driver_output_pin> <sink_input_pin> ------> it will
connect the output pin to other cell input pin if two cells are in diiferent hierarchy.
20. Find route length
get_attribute [get_nets <net name>] route_length --> it will give which layer layer routed
which distance(ex: M4{20},M5{30} .. If lower layer routed most distance we can change to
upper layer so, net delay will reduce.
21. Records the fixes (like DRC ).. It won't record cell movement---------
Record_layout_editing –start
<Route the layers…………>
Record_layout_editing –stop -output <name>.tcl
22. To Get Feed through info cmnds:
change_selection [get_ports FE*] ----> it will highlight the feedthroughs
sizeof_collection [get_ports FE*] ---> it will give count of feedthroughs
sizeof_collection [get_ports FE* -filter "physical_status == fixed"] -----> it will give count
of placed feedthroughs
sizeof_collection [get_ports FE* -filter "physical_status == unplaced"] ----> it will give
count of unplaced feedthroughs.

ECO COMMANDS:
add_buffer_on_route <netname/tile_dfx/cts0> <Lib cell name/HDBLVT08_BUF_CK_6> -
repeater_distance 75 -cell_prefix <any name/tranfix_aug1> -net_prefix <any
name/tranfix_aug1> -punch_port ----> It will add the buffers every 75microns
1. split_fanout -max_fanout 8 -net <net_name> -on_route -net_prefix <enet> -
cell_prefix <ecell> -lib_cell <HDBLVT08_BUF_6> ---------> it will split the net according
to the sinks (its usefull)
2. add_buffer_on_route <net_name> <lib_cell> -repeater_distance -cell_prefix -
net_prefix –punch_po rt
3. add_buffer_on_route <net_name> <lib_cell> -repeater_distance _length_ratio <0.5>
-cell_prefix -net_prefix –punch_port
Options: -repeater_distance :we need to specify a distance for this in microns. Tool will lay
down buffers at that ratio
-repeater_distance _length_ratio need to give a ratio (Example 0.1,0.2). If its
0.1 tool will lay buffers for every 10% of route length
-punch_port - This will be useful to connect easily between hierarchies
add_buffer_on_route -cell_prefix tran_fix_sept25 -detect_layer -lib_cell
*/ec0bfn000ab1n16x5 -location {144.001 1.036} [get_nets gti_eucp_dft_ugt] --> add buffer
on routing net at particular location.
add_buffer_on_route gti_eucp_dft_ugt -lib_cell ec0bfn000ab1n16x5 -location {144.001
1.036} -detect_layer -punch_port ---> same above add buffer on routing net at particular
location.
add_buffer_on_route -repeater_distance 60
gtlpdssmpar5_wrap1/msarb_fork_sbus_data_d63788d678d88775d8b5187dff83d59b_START
.sbus_int.eu_sbus_data[178] -lib_cell ec0bfn000ab1n28x5 ---- using repeater distance
add_buffer_on_route -repeater_distance_length_ratio 0.5
gtlpdssmpar5_wrap1/msarb_fork_sbus_data_d63788d678d88775d8b5187dff83d59b_START
.sbus_int.eu_sbus_data[178] -lib_cell ec0bfn000ab1n28x5 ----- using route repeater distance
length distance length ratio.
add_buffer_on_route [get_net
scf__scf_smn__ScfSmnRouterR2_VSOC_ScfSmnTniuSYSTEMHUB0_flit_ReqFlitData[30]
] -first_distance 2 -lib_cell HDBLVT08_BUF_8 -repeater_distance 80 -punch_port -
cell_prefix cksong_drv_1004 ---> it placed the first cell after 2 microns after that every 80
microns it will place the cell…

get_attribute [get_nets <net_name>] route_length

or
change_selection [get_nets <net_name>]
get_attribute [get_selection] route_length ----- This will give route length in each metal
size_cell <cell_name> <lib_cell>
insert_buffer <pin name> <lib_cell>
size_cell
gtlpdssmpar5_wrap1/sc_fl_avs_fork_top1/sc_fl_avs_fork0/target_demux2/demux2/route_opt
_ropt_mt_inst_2680867 ec0bfn000ac1n20x5
insert_buffer
gtlpdssmpar5_wrap1/scunit1/sc_main0/scunitx1/sc_cache1/sc_cache_control1/sc_cache_ebb
_mask_fifo1/gt_fifo_flopped_out_strg/wrdata_f_reg_0_b12_b13_b14_b15_qreg/d1
ec0bfn000ac1n02x3
insert_buffer [get_pins
{n46_oss_sdma_t_G0_SOC_xtrigger_refclk_node/fixhold_18082017_fullchip__11_0/A}]
HDBSVT11_BUF_1 -new_net_names {fct0924_PTECO_HOLD_NET42} -new_cell_names
{fct0924_PTECO_HOLD_BUF42} -location {281.9220 -381.1200} ----> inserting the
buffer in particular location…

split_fanout -lib_cell ec0bfn000ab1n12x5 -max_fanout 16 -net [get_nets

gtlpdssmpar5_wrap1/scandfxgtlpdssmpar5unit1/scandfxgenunit1_overpv_class40/scandfx_e
dt_interp1/scandfx.edt_400ch.inst1/scandfx_8or3_400ch_edt_controller_i/config0_decoder3/
ropt_net_2143431] -cell_prefix eco_data_tran_fix_ww38p2_cell -net_prefix
eco_data_tran_fix_ww38p2_net --> split the load
set_cell_location -coordinates {259.0200 303.1440}
gtlpdssmpar5_wrap1/lbdmunit1/dm_sc_inf0/eco_tran_ww39p3_fix ---> set the particular
location of the cell.
disconnect_net -net eco_net_0_gti_eucp_dft_ugt
diode_on_partition_ports_gti_eucp_dft_ugt/dpd1 --> for net to pin connection problem ,
disconnecting the particular net connection cmd.
connect_net -net gti_eucp_dft_ugt diode_on_partition_ports_gti_eucp_d --> for net to pin
connection problem, connecting the particular net is connect the particular pin.
report_global_timing -delay_type max -separate_all_groups --> it showing setup overall
timing violations
report_global_timing -delay_type min -separate_all_groups --> it showing hold overall
timing violations
write_changes -format icc2 -output ~/example.tcl – for saving .tcl file whatever u changes
Convert buffer to inverter:
set_reference -block [get_lib_cells ec0pp60_bn/ec0inv000rb1n32x5] -pin_map {a a o o1}
[get_cells gtlpdssmpar2_wrap1/sbe_ssbuf1/port[1].sbe_sslat/place_opt_BUFT_RR_829347]
--> convert buffer to inverter pair
Generating netlist
write_verilog -compress gzip -exclude { physical_only_cells scalar_wire_declarations
leaf_module_declarations filler_cells pg_objects } <save path location>.v.gz
PT-Shell
report_global_timing -delay_type max -separate_all_groups --> it showing setup overall
timing violations
report_global_timing -delay_type min -separate_all_groups --> it showing hold overall
timing violations
estimate_eco -type size_cell -lib_cell
ec0pp60gtalpha_bn_p1274d7_tttt_v085_t100_max_ccst_lvf/ec0fuy003ab2n08x5
gtlpdssmpar2_wrap1/sbe_ssbuf1/sbe_ssfrag/ssbe_sbe_req_sender/gt_credit_inf_put_sender/t
ar[0].counter/credits_gte_f_reg[1][0] --> before applying eco it showing after applying eco
how-much we have to get benefit (means estimation of eco).
report_timing -capacitance -nets -input_pins -transition_time -nosplit -delay_type min -
group c1xclk_gtdssm1xspine -pba_mode exhaustive --> general timing command in pba
mode.
get_attribute [get_nets -of_objects [get_pins
gtlpdssmpar5_wrap1/scunit1/sc_main1/st_sc_inf/fifo/gt_fifo.gt_fifo_opt.fifo_inst/gt_fifo_str
g/latched_data_reg_2_b108_b109_b110_b111_qreg/o*]] total_coupling_capacitance ---> it
showing coupling capacitance of pin.

report_analysis_coverage -status_details untested > my_file.txt ---> analysis coverage of

corner
check_timing -verbose -override_defaults clock_crossing ---> Information: Checking
'clock_crossing'.
Insert_buffer pin_name buffer_name ---> insert_buffering
Ex: insert_buffer
gtlpdssmpar5_wrap1/scunit1/sc_main0/scunitx1/sc_cache1/sc_cache_control1/sc_cache_ebb
_mask_fifo1/gt_fifo_flopped_out_strg/wrdata_f_reg_0_b12_b13_b14_b15_qreg/d1
ec0bfn000ac1n02x3
Size_cell cell_name sizeing_cell --> up/down sizing
Ex: size_cell
gtlpdssmpar5_wrap1/sc_fl_avs_fork_top1/sc_fl_avs_fork0/target_demux2/demux2/route_opt
_ropt_mt_inst_2680867 ec0bfn000ac1n20x5
report_timing -from
gtlpdssmpar4_wrap1/maunit2/ma_outarb1/ma_scalable_outarb_inst/EU_REQ[2].ma_rgb_ins
t/euX_obus_queue/fifout_pre_reg[8] -to
gtlpdssmpar4_wrap1/maunit2/ma_clkgatefub1/ma_clock_gate_b_rtl_clk_gate_icg_0 -
transition_time -capacitance -nets -delay_type max -input_pins -pba_mode exhaustive -
path_type full_clock_expanded
all_fanin -to
gtlpdssmpar5_wrap1/scunit1/sc_common1/sc_cache_data1/sc_cache_b0l/SC_CACHE_EBB
0/get_ebb.ebb_inst/prim_row[0].prim_col[0].last.gfxwrapram_ebbinst1/ary_6851212112.ip7
4d6np0vrflp2r1w68x512_inst0/iren0 -flat -startpoints_only -only_cells
all_fanout -from
gtlpdssmpar5_wrap1/gctunit_dop_1xclk_gtdssm1xspine_h_rib7_r292_c307d_gtlpdssmpar5_
c1xclk/clk -flat -endpoints_only -only_cells
report_timing [get_pins -of_objects [all_fanout -from
gtlpdssmpar5_wrap1/gctunit_dop_1xclk_gtdssm1xspine_h_rib7_r292_c307d_gtlpdssmpar5_
c1xclk/clk -flat -endpoints_only -only_cells] -filter "direction==in&&is_clock_pin!=true"]
history ../../../../fix_eco > pt_commands.rpt --> saving file
report_timing -path_type full -delay_type max -max_paths 1 --> report worst timing path
report_timing -path_type full -delay_type max -max_paths 1 -group c1xclk_gtdssm1xspine --
> reports worst timing path at particular group

report_timing -delay_type min -group c1xclk_gtdssm1xspine --> reports hold timing at

particular clock group
report_timing -delay_type max -group c1xclk_gtdssm1xspine --> reports setup timing at
particular clock group
report_timing -group [get_path_groups *] --> reports timing all groups
report_net -connections -verbose
gtlpmsamppar1_wrap1/creunit1/crer1/crerctrl1/crectrl_src_ram[1].ctrl_src_ram/gt_ram_pack
ed_strg/rpdpriv_rdsel_int[42] --> report net connections
report_timing -delay_type max_rise -transition_time -capacitance -nets -input_pins -from
gtlpmsamppar1_wrap1/creunit1/crer1/crerctrl1/crectrl_src_ram[1].ctrl_src_ram/gt_ram_pack
ed_strg/rpd_genram_rdsel_drvr_s1p0_10/o1 ---> reports timing for max rise
write_changes -format icc2 -output ~/example.tcl – for saving .tcl file whatever u changes
eco_netlist eco_netlist -by_verilog_file eco.v \ -compare_physical_only_cells -
write_changes eco_changes.tcl
place_eco_cells
place_eco_cells -legalize_mode minimum_physical_impact \ -eco_changed_cells -
legalize_only -displacement_threshold 10