Internship Schedule – SoC Verification – 6 months (26-weeks) -- Tentative

Week Nos. Activities Category

1 Digital logic design
2 Project Management
3 RTL Coding using Verilog HDL
4 Functional Verification using Verilog HDL Industry
4 Mini project – using Verilog Standard
5 Interface Protocols Training
5 Overview of SoC Architectures
6-8 Advanced FV using SystemVerilog
9 Mini Project – using SV
10-12 Internship Break Break
13 Project Specification
14-16 Project Architecture
17-20 VIP Development In-House Product
21-24 VIP Development Development
25 Documenting the project Projects
25 Technical article submissions to standard Journals
Internal / External Placement assistance, Mock interview
26 Placements
workshops

** Schedule is not necessarily in the same order