THIMMANAGOWDA B M

Summary of Expertise:
Work experience: 1+ Years in RTL Coding and UVM Verification.
Hardware Description Languages : VHDL, Verilog, System Verilog.
Tools: Synopsys VCS, Verdi.

Technical skills:

Simulator Synopsys VCS

HDL Verilog

HVL SV

Programming Basic C

Verification Methodologies UVM

Project Summary:

Project Functional verification of PCIe Gen3 Data Link Layer Transmitter

Description: This project is to understand the concept of PCIe Gen3 and

develop Testbench in UVM Architecture.

1. The primary responsibility of PCI Express Data

My Role Link Layer is to assure that integrity is maintained
when TLPs move between two devices.
2. I am part of the team responsible for module level
verification of Data link layer.
3. Understood PCIe specifications and
4. Developed coverage driven verification.
Tools Synopsys VCS.

Project Functional verification of APB

 Description: APB is a generation of AMBA bus which is intended to address
the requirements of Low-Bandwidth and Low-performance synthesizable
designs. It is a Low-Cost interface that is optimized for minimal power
consumption and reduced interface complexity.
My Role
1. Understood the AMBA APB specifications and
was involved in development of test cases.
2. Written test cases dependent on the test plan
given to cover all functional features.

Tools Synopsys VCS

VIP for verification of a 16x16 Router and DPRAM using System Verilog
Project and UVM
Description: Designed a verification environment for 16x16 router and dpram
My Role in System Verilog and UVM. The verification was performed to get 100%
Functional Coverage.

Tools Synopsys VCS

Education:

Examination Institute/University Year of passing Aggregate

Siddaganga Institute Of
B.Tech 2018 7.21CGPA
Technology
Anubhava Mantapa P U
P.U.C 2014 72%
College
Swami Vivekananda High
S.S.L.C 2012 81%
School