784
3, MAY 2003
Direct Repetitive Control of SPWM Inverter for UPS
Purpose
Kai Zhang, Yong Kang, Jian Xiong, and Jian Chen, Senior Member, IEEE
Abstract—A novel repetitive controller directly combined
with an open loop SPWM inverter is presented in this paper. To
cope with the high-resonant peak of the open loop inverter that
may cause instability, a zero-phase-shift notch filter other than
the inverse transfer function of the inverter or a conventional
second-order filter is incorporated in the controller. The proposed
method has good harmonic rejection and large tolerance to
parameter variations. To further reduce the steady-state error,
low-pass-filter ( ) algorithm is applied. DC bias problem is also
taken into consideration and solved with the repetitive controller
itself. The method is implemented with a digital signal processor
and achieves low THD% (1.4%–1.7%) with nonlinear loads and
fast error convergence (3–5 fundamental periods). It proves to
be a cost-effective solution for common UPS products where
high-quality output voltage is more stressed than fast dynamic
response.
Index Terms—Inverters, pulse-width modulation, repetitive con-
trol, UPS.
I. INTRODUCTION
U NINTERRUPTIBLE power supply (UPS) systems are
widely used for providing emergency power to critical
loads that cannot afford utility failure. The core of a UPS is
a CVCF inverter. High-quality output voltage is required for
these inverters. SPWM technique can greatly improve the
output voltage, and has enjoyed extensive applications because
of easy implementation, low-cost, and reliable operation.
However, the main drawback of an SPWM inverter is large
total harmonic distortion (THD) with nonlinear loads as well
as other nonlinearities within the inverter (dead time, nonideal
switching, etc).
To address this, various instantaneous feedback control
schemes, such as deadbeat control [1], multiloop control [2],
[3], have been proposed. With these methods, both high-quality
output voltage and fast dynamic response can be obtained. The
disadvantages are
1) more variables need to be sensed;
2) high-speed control is required to reject the disturbance.
These inevitably raise cost and make these methods less attrac-
tive to common products.
Repetitive control is a good alternative. It utilizes the repeti-
tive nature of the disturbances while other methods do not. The
Manuscript received December 15, 2000; revised February 11, 2003. This
work was supported by the National Science Foundation of China (NSFC) under
Project 59707007. Recommended by Associate Editor F. Blaabjerg.
The authors are with the Department of Electrical Engineering, Huazhong
University of Science and Technology, Wuhan 430074, China.
Digital Object Identifier 10.1109/TPEL.2003.810846
0885-8993/03$17.00 © 2003 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO.
control mechanism is actually a fundamental-period-based inte-
gral control. The output voltage is the only variable needs to be
sensed, and the control action needs not to be very fast to achieve
high-quality output voltage. Although sub-cycle response is im-
possible, a settling time of several fundamental periods is ac-
ceptable for many applications.
In [7] and [8], repetitive control are combined with dead-
beat control and least-square-error state-feedback control, re-
spectively, with these instantaneous feedback control schemes
serving as the inner loops. While achieving fast response, the
inner loops also improve the dynamics of the inverter, which
eases the repetitive controller design. Nevertheless, introducing
instantaneous feedback control raises cost and complicates the
system.
If a repetitive controller is directly combined with an SPWM
inverter, high-quality output voltage can be achieved at much
lowered costs. This seems more appropriate for common prod-
ucts for which fast response is not the chief consideration. De-
signing a good repetitive controller for an open-loop SPWM in-
verter is no easy work due to bad dynamics of the inverter, espe-
cially at no load. If the parameters of the inverter are precisely
known, the inverse transfer function of the inverter can be syn-
thesized in the repetitive controller, which provides fast and pre-
cise compensation of the distortion [9]. However, this requires
perfect modeling of the inverter, which is difficult in practice.
A nearly parameter-independent method is proposed in [10],
in which a zero-phase-shift low-pass FIR filter is placed in the
feedback path to block off any frequency components above and
filter, thus
around the resonance frequency of the output
safeguarding system stability. As a result, a fundamental-pe-
riod-based PI controller independent of the parameters can
be employed to achieve excellent output voltage in steady state.
Not surprisingly, since even the roughest knowledge of the
parameters is not utilized (except providing the upper limit of
the FIR filter’s cutoff frequency), better timing of the control
action, i.e., phase compensation, becomes difficult, which ham-
pers fast error convergence.
In this paper, a new direct repetitive control scheme is
proposed in which a zero-phase-shift notch filter is employed
to cancel out the resonant peak of the inverter. The notch
filter provides larger tolerance to parameter variations, com-
pared with the inverse transfer function of the filter;
and better harmonic rejection, compared with a conventional
second-order filter. Fast error convergence is achieved with
appropriate time-advance compensation of the delay within the
open-loop system. The method is verified with experiments
and proves to be a cost-effective solution for common UPS
products.
ZHANG et al.: DIRECT REPETITIVE CONTROL OF SPWM INVERTERS 785

The core of the repetitive controller is the modified internal

model , i.e., transfer function of the positive
feedback minor loop ( denotes the number of samples within
one fundamental period). Neglecting for convenience of
analysis, the modified internal model reduces to its original ver-
sion , whose function is to integrate the error on a
fundamental-period basis. The result of the integration, denoted
as , is then processed by the following units to generate .
Fig. 1. Main circuit of the single-phase half-bridge SPWM inverter. 1) : time delay unit. It postpones the control action
by one fundamental period so that time advance unit
II. PLANT MODELING as well as the noncausal zero-phase-shift notch filter
included in can be realized.
A balanced three-phase SPWM inverter can be converted into
2) : compensator. It modifies magnitude characteristic
two decoupled single-phase inverters through ABC- trans-
of the open-loop system for better harmonic rejection.
formation [1]. (Note the load needs not to be balanced since
3) : time advance unit [6]. It advances the control action
the load currents are treated as disturbance inputs.) For conve-
by sample periods in the next fundamental period, so as
nience, this study is carried out on a single-phase half-bridge
to compensate the delay of compensator as well as
SPWM inverter shown in Fig. 1.
the inverter .
Neglecting switching frequency ripples, the dynamics of the
4) : gain. It controls the magnitude of .
inverter are mainly determined by its filter. If there were no
If the system is stable, it will eventually reach an equilib-
dead time in the gating signals, and no loss in the switches, the
rium where all variables settle down, including the waveform
filter and the line connections, then the damping ratio of
of , which means the error must be zero in steady state.
the inverter would be zero and an infinite resonant peak would
This error elimination mechanism is similar to classical inte-
appear in its magnitude–frequency characteristic, which makes
gral control, which can eliminate steady-state error for step dis-
repetitive control fairly difficult. Fortunately, this is not the real
turbances. In this sense, repetitive control can be looked on as
case. Dead time as well as inevitable losses in a real inverter
fundamental-period-based integral control. In practice, a filter
always gives a little damping. The real resonant peak can be
is often incorporated and the resulting modified internal
still high, but not infinite. The damping effects as a whole can
model is no longer a pure integrator. This effectively increases
be modeled as a small resistor (denoted as ) connected in series
stability margin, but at the cost of nonzero steady-state error [5].
with the filter inductor , as shown in Fig. 1.
can be a low-pass filter, with which only high-frequency
Mathematical model of the inverter must be established be-
harmonic rejection is sacrificed. This is acceptable since the
fore the design starts. But the actual damping ratio is quite dif-
filter can attenuate high-frequency harmonics. can also
ficult to determine through theoretical analysis. To circumvent
be a close-to-unity constant, which is easier to implement, but
this difficulty, an experimental approach is taken in this paper
low-frequency harmonic rejection will be weakened as well in
(see Section V), that is, directly measure the frequency response
this case.
of the inverter. Several facts will ease this task.
From Fig. 2, the relationship between error , sine reference
1) Only the magnitude characteristic needs to be measured, , and disturbance can be derived
because the second-order model of the inverter is a min-
imal-phase one.
2) With the proposed method, characteristics above the res-
onance frequency make little difference. So, the work can
be stopped when the gain is found to be declining. (1)
3) Nowadays, most of the inverters are digital-controlled,
which means frequency change can be both convenient A sufficient condition for system stability can be derived with
and accurate. small gain theorem [11]

III. SYSTEM ANALYSE (2)

Basic conceptions of repetitive control can be found in earlier in which
documents [4]–[6]. Shown in Fig. 2 is a plug-in type modified
repetitive controller [4]. All repetitive disturbances that cause
output voltage distortion, such as nonlinear load, dead-time ef- sample time
fect, are summarized as disturbance input . Tracking error is
the input to the repetitive controller. is the resulting repeti- in (2) means while increases from zero to the Nyquist fre-
tive control voltage, which is added to the original sine reference quency, if the end of the vector does
so as to compensate the distortion. It can be seen that if the not exceed the unity circle centered at the end of , then
plug-in repetitive controller is removed, the system reduces to the repetitive control system is sufficiently stable. Shown in
a primitive SPWM inverter. (Function of dc bias detection will Fig. 3 is a geometric explanation of the condition. Fig. 3 also
be discussed in Section V.) reveals that with (plotted here as a close-to-unity constant
786 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 3, MAY 2003

Fig. 2. Block diagram of the repetitive controlled SPWM inverter system.

indicates harmonic rejection capability, and there-

fore is defined as harmonic rejection index in this paper. Note it
is also a function of frequency.

IV. REPETITIVE CONTROLLER DESIGN

Fig. 3. Illustration of the sufficient condition of stability.
for convenience), the center of the unity circle is left-shifted
from (1,0), which prevents vector
from exceeding the left border of the unity circle due to poor
phase compensation at high-frequencies.
Supposing , and the disturbance and the sine ref-
erence to be purely repetitive, i.e., , robust stability. In this paper, magnitude-and-phase cancellation
, the error convergence can be derived from (1)
Equation (3) implies that for the harmonic component of fre-
quency , its magnitude at each fixed sampling point within one
fundamental period is reduced to times the original
value after each fundamental period. Therefore,
called error convergence index [7]. This index is a function of
frequency.
Substituting into (1), and realizing that the steady-
state error consists of harmonics whose frequencies ( ) can only
be multiples of the fundamental frequency , the steady-
state error can be obtained
Equation (4) means in steady state, the reference-tracking error
and the error caused by the disturbance
are all reduced to
times their original values. Magnitude of
A good repetitive controller should firstly ensure stability,
and then it should provide enough harmonic rejection. In addi-
tion, the error convergence should be as fast as possible. From
(2)–(4), it is evident that to meet these requirements simulta-
neously, should be as small as possible, which calls
for perfect cancellation, i.e., . This
is possible if the inverse transfer function of the filter is
employed to substitute , but not appropriate for
practical products.
Although there is always parameter drifts during practical op-
eration, the frequency response of an filter below the reso-
nance frequency is relatively stable. It is the high-frequency be-
havior that is more sensitive to parameter variations. Therefore,
it seems a wise choice to swap high-frequency cancellation for
is carried out below the resonance frequency. Above this fre-
quency, the controller gain falls off quickly to avoid any chance
(3) of breaking the stability condition (2). By doing so, high-fre-
quency harmonic rejection is leaved to the filter. In fact,
even if full range cancellation is carried out, a low-pass-filter
will still weaken high-frequency harmonic rejection.
is A. Cancellation of Resonant Peak
Function of compensator is to cancel out the resonant
peak of the inverter and attenuate high-frequency gains. To en-
sure stability at different load conditions, design of must
be carried out at no load when the resonant peak of the inverter is
the highest (typically 20–30 dB). If a conventional second-order
filter is to serve as , lower-order harmonic rejection will be
adversely affected. The reason is: to give enough attenuation
at the resonance frequency, the cutoff point of the second-order
filter must be set fairly low. This brings unnecessary attenuation
at lower frequencies, which renders high there. Since
(4) the phase angle of will be made small due to phase
compensation, a higher value of definitely means
weaker harmonic rejection according to (4).
The following notch filter shown in (5) at the bottom of the
next page is found more suitable for the choice of . It has
zero phase shift. When the notch point is located at the Nyquist
frequency, it behaves like a low-pass filter and has served as
ZHANG et al.: DIRECT REPETITIVE CONTROL OF SPWM INVERTERS 787

Fig. 4. Bode plots used in the design process. (a) Measured magnitude curve of inverter plant P (z ). (b) Magnitude curve of notch filter (z + 2 + z )=4. (c)
Magnitude curve of compensated plant S (z )P (z ). (d) Phase cancellation of compensated plant S (z )P (z ).

filter in [4]. Otherwise, it has a V-shape magnitude char-
acteristic, with the gain remaining fairly close to unity up to the
neighborhood of the notch point, then falling off abruptly with
a descending rate much greater than that of a second-order filter
[see Fig. 4(b) for an example]. This behavior is suitable for can-
celing out the resonant peak of the inverter without appreciable
attenuation at lower frequencies. To achieve high-frequency at-
tenuation that is essential for stability but the notch filter lacks,
a second-order filter can serve as a complement
B. Controller Design With Constant
The simplest choice of is a close-to-unity constant, typ-
ically 0.95 [8]. In such case the center of the unity cycle in
Fig. 3 is fixed. The following is a proposed design procedure
for . 26 dB. If the stability condition is found violated, the design
Step 1. Measure the magnitude characteristic of the in-
verter.
Step 2. Select an appropriate notch filter and a second-order
filter to form the compensator . The aim is: the gain of
remains close to unity up to the resonance frequency,
than falls off quickly at higher frequencies. This ensures excel-
lent harmonic rejection below the resonance frequency.
Step 3. Select time-advance step size , so that compen-
sates the delay of up to the resonance frequency.
Step 4. Select gain . A higher results in faster error
convergence, lower steady-state error but smaller stability
margin.
Step 5. Check system stability. At low-frequencies, cancel-
lation is easy and stability condition (2) is nearly always met. At
high-frequencies where the loop gain has
dropped below 26 dB(0.05), violation of (2) is also impossible
(see Fig. 3 for a straightforward explanation). Therefore, close
check should be focused on medium frequency range around
the resonance frequency, where phase cancellation has already
begun to deteriorate but the loop gain has not yet dropped below
should be modified.
C. Controller Design With Low Pass Filter
The zero-phase-shift notch filter (5) can also serve as ,
with the notch point assigned at the Nyquist frequency of the

(5)
788 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 3, MAY 2003

system. In this case, the center of the unity circle (see Fig. 3) TABLE I
is no longer static but in constant moving along the real axis, SYSTEM PARAMETERS
which complicates the verification of condition (2). However,
this difficulty can be overcome with help of control system CAD
software like MATLAB. Apart from this, the design process is
largely the same.
Theoretically, conventional first or second-order filter can
also serve as . Since they bring nonzero phase shift, the
locus of the center of the unity cycle will not be restricted
on the real axis, which makes the stability check even more
complicated. Therefore, these cases are not discussed in this
paper.

D. Comparison of Two Choices of

Supposing , , and perfect cancellation,
the harmonic rejection index becomes
(6)
Equation (6) means all harmonic components will be reduced to
1/21 of their original magnitudes.
When is a low-pass filter, harmonic rejection can be
further improved at low-frequencies, because can be
higher than 0.95 at low-frequencies, which renders the nomi-
nator in (6) even smaller. This advantage becomes especially at-
tractive at fundamental frequency, where hence
virtually zero steady-state error is achieved. At high-frequen-
cies, decreases below 0.95, resulting in larger sta-
bility margin but worse harmonic rejection. As for the overall
harmonic rejection, there is usually no significant difference be-
tween these two choices.
E. Impact of
The proposed design method implies a highest of 1.0 for
minimal stability margin. A smaller brings a larger stability
margin.
Change of significantly affects error convergence rate.
Supposing and perfect cancellation, the error con-
vergence index becomes
(7)
It is seen that the error convergence rate is proportional to
in this case. In general, a higher always brings faster error
convergence.
Change of also affects steady-state error. Under the same
assumptions mentioned above, the harmonic rejection index is
(8)
In general, higher brings smaller steady-state error. This
phenomenon is similar to the case of proportional ( ) control.
However, it should be noted that the integral nature of repetitive
control renders a more important role in determining the
magnitude of steady-state error.
V. CASE DESIGN AND EXPERIMENTAL RESULTS
A. Main Circuit and Controller Design
Main circuit of the experimental setup has been shown in
Fig. 1. Key parameters of the system are summarized in Table I.
Measuring of the inverter’s magnitude characteristic is
based on a regular-sampling SPWM program. Reference sine
frequency is changed by varying the step size with which the
program looks up the sine table. 15 points have been measured
within the frequency range [50–2000 Hz]. The results are
marked with small circles in Fig. 4(a), which demonstrates a 22
dB resonant peak at 4400 rad/s. The best second-order model
for this characteristic is found to be
(9)
It has a natural frequency of 4400 rad/s and a damping ratio of
0.045. The latter can be looked as coming from a 0.6 equiva-
lent resistor in series with the filter inductor . The magnitude
curve of (9) is also plotted in Fig. 4(a), and matches the mea-
sured data well.
Compensator is made up of the following zero-phase-
shift notch filter [see Fig. 4(b) for its magnitude curve]
(10)
and the following second-order filter
(11)
has a natural frequency of 4300 rad/s and a damping ratio
of 1.0. Magnitude curve of is shown in Fig. 4(c). It
meets the requirements stated in step-2 of the proposed design
procedures.
The total phase delay of is shown in Fig. 4(d).
With a sample time of 0.0001 s, was chosen as the time ad-
vance unit. Its inverted phase curve is plotted along with that
of to watch the cancellation effect. It shows that
can perfectly cancel out the phase delay of up to
4100 rad/s. From Fig. 4(c) and 4(d), it is seen that good magni-
tude-and-phase cancellation has been achieved up to 4400 rad/s,
suggesting good harmonic rejection in such frequency range.
ZHANG et al.: DIRECT REPETITIVE CONTROL OF SPWM INVERTERS
Fig. 5. Locus of vector K e S (e )P (e ) with Q(z )
Supposing , stability condition (2) can be checked
with Fig. 4(c), Fig. 4(d) and Fig. 3. A computer-generated locus
of vector is also given in Fig. 5. The
locus remains within the unity circle centered at
The following zero-phase-shift low-pass filter is selected as
another choice for : Clearly, dc component in the PWM gating signals is the cause
Its gain is 0.923 at 4000 rad/s. Fig. 6 is the locus of
in this case. The locus remains within the unity circle (note the
margin is even larger). Therefore, the system is stable without
changing other parts of the previous design.
B. System Stability With Parameter Variations
Since the proposed method only carries out cancellation in
medium-and-low-frequency range, enhanced resistance to pa-
rameter variations can be obtained. Shown in Fig. 7 is an illus-
tration of system stability ranges based upon the aforementioned
design data. Note that since (2) is employed as the stability cri-
terion, the system is sufficiently stable within the ranges. It is
shown that low-pass-filter or a smaller results in larger
stability ranges. The system exhibits strong tolerance to the in-
crease of the resonance frequency of the filter, i.e., decrease
of the product of the inductance and the capacitance . This
can be explained by the low-pass nature of the compensator
. Tolerance to the decrease of the resonance frequency can
be further enhanced by reducing the cutoff frequency of
but the harmonic rejection band will also be narrowed accord-
ingly.
C. Countermeasure Against DC Unbalance
For any instantaneous voltage control schemes including
repetitive control, asymmetric control actions in positive and
negative half waves of the output voltage are inevitable due to
random operation conditions. This gives rise to biased PWM
gating signals, which in turn generate dc component in the
output voltage. In many applications, feedback of the resulting
dc component is blocked by an output or detecting transformer,
while for half-bridge inverters such as the one used here, dc
component simply does not appear in the output, even if the
gating signals are heavily dc-biased. In either of the above-men-
789
= 0:95. Fig. 6. Locus of vector H (e ) with Q(z ) = low-pass filter.
tioned cases, the dc unbalance is leaved uncontrolled because of
the absence of a close loop for it. This brings many problems,
such as over current in the output transformer, or uneven
. distribution of the dc bus voltage between the voltage-halving
capacitors in a half-bridge inverter.
of the problems. This issue gets more serious for repetitive con-
trol because of its integral nature, especially when low-pass-
(12)
filter is applied. To solve this problem, 200 control volt-
ages in each fundamental period are summed up to find out the
dc component. This value is then adjusted and subtracted from
the sine reference (see Fig. 2) in next fundamental period. In
this way, the dc component in the gating signals, which can be
looked as a “zero-order harmonic,” is made known to the repet-
itive controller, thus can be eliminated by it through the same
harmonic rejection mechanism. In the experiments this method
has safeguarded even sharing of the dc bus voltage by the two
capacitors.
D. Experimental Results
A bridge rectifier RC load serves as the nonlinear load. The
control scheme is implemented with a TMS320F240 DSP.200
of the DSP’s total 544 RAM units are employed to store the
values of the integrated error within one fundamental period.
Execution of the control program takes less than 10 s. Com-
pared with the 100 s sample time, this suggests enough space
for auxiliary functions for practical products, or the possibility
of increasing switching frequency to further reduce the size of
, the filter.
Shown in Fig. 8 are the waveforms and harmonic spectrums
of the output voltage with nonlinear load. It is observed that with
the proposed repetitive controller, the harmonics below the 15th
have been significantly reduced, as expected in controller design
stage. Lower order harmonics are reduced more significantly
with low-pass-filter than with constant .
Error convergence processes with different settings of
and are shown in Fig. 9. The error converges quickly and
smoothly, and it usually settles down in 3–5 fundamental pe-
riods after the repetitive controller is switched on. Fig. 9 also
shows that a larger brings quicker convergence and lower
steady-state error. Fig. 10 demonstrates dynamic response of the
output voltage with step changes of resistive load. For most ap-
plications, the settling time is acceptable.
790 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 3, MAY 2003

Fig. 7. Stability ranges of the repetitive control system. (a) K = 0:9. (b) K = 0:5.

Fig. 8. Output voltage waveforms and harmonic spectrums with nonlinear load Top: Without repetitive control. Middle: With repetitive control, Q(z ) = 0:95,
K = 0:9. Bottom: With repetitive control,
Q(z ) = low-pass filter, K = 0:9. (voltage: 50 V/div; current: 10 A/div; time: 2.5 ms/div).

Experimental results for different settings of and
are summarized in Table II. The overall harmonic rejection (in-
dicated by THD%) is largely the same for the two choices of
. Magnitude regulation of the output voltage with resistive
load is shown in Table III ( ). Note that there is virtu-
ally no steady-state error for low-pass-filter type . filter. Fast error convergence is achieved with appropriate
VI. CONCLUSION
A novel repetitive controller that can be directly combined
with an SPWM inverter is proposed. The system is simple in
structure because there is no instantaneous feedback inner loop.
High-resonant peak of the open-loop inverter is compensated
withazero-phase-shiftnotchfilter, whichenableslargertolerance
to parameter variations than the inverse transfer function of
the inverter; and makes the harmonic rejection capability less
affected when compared with a conventional second-order
time-advance compensation of the delay within the system.
Theproposedcontrollerdesignmethod enablesrobuststabilityby
restricting the cancellation within medium-and-low-frequency
range while heavily attenuating the high-frequency gains. The
experimental setup exhibits low THD% with nonlinear loads,
low-steady-state error and fast error convergence. The proposed
ZHANG et al.: DIRECT REPETITIVE CONTROL OF SPWM INVERTERS 791

Fig. 9. Error convergence processes (voltage: 5 V/div; time: 50 ms/div). (a) Q(z ) = 0:95, K = 0:9; (b) Q(z ) = 0:95, K = 0:5; (c) Q(z ) = low-pass filter,
K = 0:9 ; (d) Q(z ) = low-pass filter, K = 0 :5 .

Fig. 10. Output voltage during load transients (a) Q(z ) = low-pass filter, K = 0:5 (b) Q(z ) = low-pass filter, K = 0:9 [current (upper trace): 10 A/div;
voltage (lower trace): 100 V/div; time: 50 ms/div].

TABLE II TABLE III

THD% AND ERROR CONVERGENCE TIME MAGNITUDE REGULATION WITH RESISTIVE LOAD

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Kai Zhang was born in Nanyang, China, on
September 20, 1972. He received the B.E., M.E., and
Ph.D. degrees from Huazhong University of Science
and Technology, Wuhan, China, in 1993, 1996, and
2000, respectively.
In 1996, he joined Huazhong University of Science
and Technology as an Assistant Lecturer. He was pro-
moted to a Lecturer in 1998. In 2001, he became an
Associate Professor in the Department of Electrical
Engineering. His research interests include UPS, ac
drives, and the related techniques on system mod-
eling, simulation, controller design, and DSP-based digital control.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 18, NO. 3, MAY 2003
Yong Kang was born in Hubei, China, on October
16, 1965. He received the B.E., M.E., and Ph.D.
degrees from Huazhong University of Science and
Technology, Wuhan, China, in 1988, 1991, and
1994, respectively.
In 1994, he joined Huazhong University of Sci-
ence and Technology as a Lecturer. In 1996, He was
promoted to an Associate Professor. In 1998, he be-
came a Full Professor. His research interest focuses
on power electronic converters, ac drives, and their
digital control techniques. He is the author of over 30
technical papers.
Jian Xiong was born in Wuhan, China, on
September 29, 1971. He received the B.E. degree
from East China Shipbuilding Institute, Zhenjiang,
China, in 1993, and the M.E. and Ph.D. degrees from
Huazhong University of Science and Technology,
Wuhan, China, in 1996 and 1999, respectively.
In 1999, he joined Huazhong University of Science
and Technology, as an Lecturer in the Department of
Electrical Engineering. His research interests include
UPS, ac drives, switch mode rectifiers, and the related
control techniques.
Jian Chen (SM’96) was born in Wuhan, China,
on August 27, 1935. He received the electrical
engineering degree from Zhengzhou Electrical
Engineering School, Zhengzhou, China, in 1954 and
the B.E. degree from the Department of Electrical
Engineering, Huazhong Institute of Technology,
Wuhan, China, in 1958.
He has been working in Huazhong Institute of
Technology (now Huazhong University of Science
and Technology) since 1958. He was promoted to
a Lecturer in 1963 and to an Associate Professor in
1978. He has studied power electronics, microprocessors, and their applications
at the University of Toronto, Toronto, ON, Canada, as a Visiting Scholar,
from 1980 to 1982. In 1985, he became a Full Professor. He is an author
of three textbooks and over 60 technical papers. His main research interests
include various power electronic converters, ac drives, and power electronics
applications in electric power systems.