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  • Computer Architecture and Organization Lab 08 Objective:: Task1: 2 1 Mux Using Case Statement Code: Block Diagram

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    umair khan
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    This document describes a computer architecture lab that teaches students about control statements like for loops and if/else statements. It includes 5 tasks - implementing a 2-1 multiplexer, 3-1 multiplexer, half adder, D-flip flop, and comparator using Verilog code. For each task, the document provides the code, block diagram, test bench code, and output. The conclusion recaps that the lab covered implementing a comparator with always statements and basic logic gates like half adders using case statements inside a cascade multiplexer.

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    COA 08 (2)

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    This document describes a computer architecture lab that teaches students about control statements like for loops and if/else statements. It includes 5 tasks - implementing a 2-1 multiplexer, 3-1 multiplexer, half adder, D-flip flop, and comparator using Verilog code. For each task, the document provides the code, block diagram, test bench code, and output. The conclusion recaps that the lab covered implementing a comparator with always statements and basic logic gates like half adders using case statements inside a cascade multiplexer.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    4 views6 pages

    Computer Architecture and Organization Lab 08 Objective:: Task1: 2 1 Mux Using Case Statement Code: Block Diagram

    Uploaded by

    umair khan
    This document describes a computer architecture lab that teaches students about control statements like for loops and if/else statements. It includes 5 tasks - implementing a 2-1 multiplexer, 3-1 multiplexer, half adder, D-flip flop, and comparator using Verilog code. For each task, the document provides the code, block diagram, test bench code, and output. The conclusion recaps that the lab covered implementing a comparator with always statements and basic logic gates like half adders using case statements inside a cascade multiplexer.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 6

    Computer architecture and organization

    Lab 08
    Objective: In this lab we will learn that
     For Loops
     Conditional statement (if else case)
     Control statement
     Blocking and Non-blocking

    Task1: 2*1 Mux using case statement


    Code: Block Diagram:

    Test bench Output:

    Test Bench :
    Task2: Cascade Mux (3*1)
    Code:

    Block Diagram:

    Test Bench code:

    Output:
    Task3: Half adder using case statement
    Code:

    Block Diagram:

    Test bench code:

    Output:
    Task4: D-flip flop using case statement
    Code:

    Block Diagram:

    TestBenchfile:
    Task5: comparator using always statement:
    Code:

    Block Diagram:

    Conclusion: In the end of the lab


     Comparator using always statement
     Half adder begin case stamen
     Cascade mux (3*1)

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