K84 MLB Schematic: PROD OK2FAB 11/01/2009

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
C 0000813234 PRODUCTION RELEASED 2009-11-01
K84 MLB SCHEMATIC

PROD OK2FAB 11/01/2009
D D
(.csa) Date (.csa) Date (.csa) Date
Page Contents Sync Page Contents Sync Page Contents Sync

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD
1 01/19/2009 49 04/02/2009 101 04/06/2009

1 Table of Contents K24_MLB 36 SMC K24_MLB 71 Memory Constraints K24_MLB
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2 01/19/2009 50 02/04/2009 102 03/30/2009

2 System Block Diagram K24_MLB 37 SMC Support K24_MLB 72 MCP Constraints 1 K24_MLB
3 51 02/15/2009 103 04/06/2009

3 Power Block Diagram 38 LPC+SPI Debug Connector K24_MLB 73 MCP Constraints 2 K24_MLB
4 01/19/2009 52 01/19/2009 104 04/06/2009
4 BOM Configuration K24_MLB 39 K84 SMBUS CONNECTIONS K24_MLB 74 Ethernet Constraints K24_MLB
5 01/19/2009 53 04/06/2009 106 04/06/2009

5 Revision History K24_MLB 40 VOLTAGE SENSING K24_MLB 75 SMC Constraints K24_MLB
6 01/19/2009 54 01/27/2009 107 01/19/2009

6 Revision History K24_MLB 41 Current Sensing K24_MLB 76 K84 SPECIAL CONSTRAINTS K24_MLB
7 02/04/2009 55 02/04/2009 109 01/19/2009

7 FUNC TEST K24_MLB 42 Thermal Sensors K24_MLB 77 K84 RULE DEFINITIONS K24_MLB
8 02/04/2009 56 04/06/2009
8 Power Aliases K24_MLB 43 Fan K24_MLB
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
9 02/04/2009 57 03/04/2009
9 SIGNAL ALIAS K24_MLB 44 WELLSPRING 1 K24_MLB
10 04/06/2009 58 02/25/2009
10 CPU FSB K24_MLB 45 WELLSPRING 2 K24_MLB
11 04/06/2009 59 03/04/2009
11 CPU Power & Ground K24_MLB 46 SMS K24_MLB
12 03/30/2009 60 02/25/2009
12 CPU Decoupling K24_MLB 47 DEBUG SENSORS AND ADC K19_IMLB
13 02/25/2009 61 02/15/2009
13 eXtended Debug Port(MiniXDP) K24_MLB 48 SPI ROM K24_MLB
14 04/06/2009 62 06/09/2009
14 MCP CPU Interface 49 AUDIO: CODEC/REGULATOR
C TABLE_TABLEOFCONTENTS_ITEM
15
15
MCP Memory Interface
K24_MLB
K24_MLB
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
50
63
AUDIO: LINE INPUT FILTER
AUDIO
AUDIO
06/09/2009 C
16 04/06/2009 65 06/09/2009
16 MCP Memory Misc K24_MLB 51 AUDIO: HEADPHONE FILTER AUDIO

17 04/06/2009 66 06/09/2009
17 MCP PCIe Interfaces K24_MLB 52 AUDI0: SPEAKER AMP AUDIO
18 04/06/2009 67 06/09/2009
18 MCP Ethernet & Graphics K24_MLB 53 AUDIO: JACK AUDIO
19 04/06/2009 68 06/09/2009
19 MCP PCI & LPC K24_MLB 54 AUDIO: JACK TRANSLATORS AUDIO

20 04/06/2009 69 02/05/2009
20 MCP SATA & USB K24_MLB 55 DC-In & Battery Connectors K24_MLB
21 03/24/2009 70 02/05/2009
21 MCP HDA & MISC K24_MLB 56 PBUS Supply/Battery Charger K24_MLB

22 04/06/2009 72
22 MCP Power & Ground K24_MLB 57 5V/3.3V SUPPLY

25 04/06/2009 73
23 MCP Standard Decoupling K24_MLB 58 1.5V/0.75V DDR3 SUPPLY

26 04/06/2009 74 03/03/2009
24 MCP Graphics Support K24_MLB 59 IMVP6 CPU VCore Regulator K24_MLB

28 02/15/2009 75 02/15/2009
25 SB Misc K24_MLB 60 MCP CORE REGULATOR K24_MLB
29 04/06/2009 76 02/04/2009
26 FSB/DDR3 Vref Margining K24_MLB 61 CPU VTT(1.05V) SUPPLY K24_MLB
31 02/05/2009 77 03/24/2009
27 DDR3 SO-DIMM Connector A K24_MLB 62 MISC POWER SUPPLIES K24_MLB
32 02/05/2009 78 02/15/2009
28 DDR3 SO-DIMM Connector B K24_MLB 63 POWER SEQUENCING K24_MLB
33 04/06/2009 79 02/15/2009
29 DDR3 Support K24_MLB 64 POWER FETS K24_MLB
34 01/27/2009 90 02/15/2009
30 X16 WIRELESS CONNECTOR K24_MLB 65 LVDS CONNECTOR K24_MLB
37 04/06/2009 93 04/06/2009
31 Ethernet PHY (RTL8211CL) K24_MLB 66 DISPLAYPORT SUPPORT K24_MLB
B TABLE_TABLEOFCONTENTS_ITEM
32
38
39
Ethernet & AirPort Support K24_MLB
04/06/2009
04/06/2009
TABLE_TABLEOFCONTENTS_ITEM
67
94
97
DisplayPort Connector K24_MLB
04/06/2009
02/09/2009
B
33 ETHERNET CONNECTOR K24_MLB 68 LCD Backlight Driver (MC34845) VEMURI_K19I
45 01/19/2009 98 04/06/2009
34 SATA Connectors K24_MLB 69 LCD Backlight Support K24_MLB
46 02/05/2009 100 04/06/2009

35 External USB Connectors K24_MLB 70 CPU/FSB Constraints K24_MLB
A A
DRAWING TITLE
SCHEM,MLB,K84
DRAWING NUMBER SIZE
Schematic / PCB #’s 051-7982 D
Apple Inc. REVISION
R
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

C.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
051-7982 1 SCHEM,MLB,K84 SCH CRITICAL THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
820-2567 1 PCBF,MLB,K84 PCB CRITICAL I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 109
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 77
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1000
U1300 J6950,J6900
INTEL CPU
CORE 2 DUO
XDP CONN
2.26 GHZ PG 13 DC/BATT CONN DC-DC POWER SUPPLIES
PENRYN
PG 55 PG 56-64
PG 10
FSB
D 64-Bit
J5800
TRACKPAD
PG 45
D
1067 MHZ
PG 14
U5515,U5535
J3100,J3200
2 SODIMMS
MAIN
FSB INTERFACE
CPU & MCP THERMAL SENSORS
GPIOs
MEMORY DDR3 1067MHZ
DIMM
PG 15,16 PG 42
PG 27,28
U5920
SUDDEN MOTION SENSOR
PG 46
Misc U6100
CLK
PG 21 SPI
SYNTH CURRENT & VOLTAGE SENSORS
Boot ROM PG 53,54,60
PG 48 J5601
J4501
SPI FAN CONN AND CONTROL

SATA
PG 43
Conn PG 21
PG 34
HD
J4500
NVIDIA
U4900
A B,0 BSA ADC Fan Ser
SATA
J5100
Prt
SATA MCP79 SMC LPC Conn
Conn
PG 34 PG 20
B03 LPC
H8S/2117
Port80,serial
C ODD
PG 19
PG 36,37
PG 38
C
U1400
J9000
PWR
LVDS
CONN LVDS OUT CTRL
PG 65
RGB OUT
J3401 J5800 J9000 J4600,4610
DP OUT
J9400
Bluetooth TRACKPAD/ EXTERNAL
CAMERA
KEYBOARD USB 2.0
HDMI OUT Connectors
MINI DISPLAY PORT PG 30 PG 45 PG 65
PG 35
CONN
DVI OUT
9
(UP TO 12 DEVICES)
8
PG 67
TMDS OUT
7
USB
PG 20
PG 18
6
5
4
3
2
1
UP TO 20 LANES3
0
PCI-E
PG 17
B B
SMB
PG 21
RGMII PCI HDA

(UP TO FOUR PORTS) DIMMS MIKEY SMC
PG 18
PG 19 PG 21
U6201
Audio
Codec
CIRRUS LOGIC CS4206

PG 49
U6500
HEADPHONE/LINE OUT
Amp
U6610,U6620,U6630
U3700 PG 51
LINE-IN
A GIGABIT
10/100/1000M E-NET
MIC
U6700
Speaker
SYNC_MASTER=K24_MLB SYNC_DATE=01/19/2009 A
Amps PAGE TITLE
RTL8211CL
PG 31
LINE-IN/LINE OUT
MUX
PG 52 System Block Diagram
PG 53 DRAWING NUMBER SIZE
Apple Inc. 051-7982 D

J3401 J3900 REVISION
MINI PCI-E J6700,J6701,J6702,J6703,J6704

R
C.0.0
E-NET NOTICE OF PROPRIETARY PROPERTY: BRANCH
Audio
AirPort THE INFORMATION CONTAINED HEREIN IS THE
Conn PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PG 30 Conns THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PG 33
PG 53 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 109
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP18V5_DCIN_CONN
K84 POWER SYSTEM ARCHITECTURE
D6905
02
PPVIN_G3H_P3V42G3H ENABLE
3.425V G3HOT 03 SMC RESET "BUTTON" 04
PP3V42_G3H_REG
D6905 PBUS_VSENSE LT3470 NCP303LSN
VOUT
U6990 U5000
D 7A FUSE V Q5315 23
0.01 OHM
R5492 PPCPUVCORE_VTT_ISNS
D
PPVBAT_G3H_CHGR_REG PPBUS_G3H PPCPUVCORE_VTT_ISNS_R
01 F7000
02 PPVIN_S0_CPUVTTS0
VIN
CPUVTTS0_EN PPCPUVTT_S0_REG
CHGR_EN EN_PSV VOUT
(S5) (S0)
F6905 CPUVTT (7.2A MAX CURRENT)
6A FUSE ENABLES (1.05V)
AC DCIN(16.5V) MCP79 06-1
ADAPTER VIN
TPS51117
VOUT U7600 PWRBTN*
IN
31
PBUS SUPPLY/ PGOOD
CPUVTTS0_PGOOD
BATTERY CHARGER PLTRST* LPC_RESET_L
PPVIN_S5_CPU_IMVP
RSMRST*
ISL6258AHRTZ MCP_PS_PWRGD
U7000 01 V SMC_CPU_VSENSE PS_PWRGD
CPUPWRGD(GPIO49)
CPU_PWRGD
CPU VCORE 29
02 PPVCORE_S0_CPU_REG
26 30
VOUT
VIN (44A MAX CURRENT)
J6950 U2850 CPU_RESET#
FSB_CPURST_L
ISL9504BCRZ
U1400
IMVP_VR_ON VR_ON
3S2P Q7050 28
BATT_POS_F PPVBAT_G3H_CHGR_OUT 25 PGOOD VR_PWRGOOD_DELAY
(9 TO 12.6V)
C U7400 06
P1V05ENET_EN 1.05V SO CPU
C
PP1V05_ENET_FET
FETS
CHGR_BGATE 22 PWRGOOD
(Q3841,Q3840) 4.5V AUDIO
PPVIN_S3_5VS3/PPVIN_S5_3V3S5
VIN TPS71745
PP4V5_AUDIO_ANALOG
EN 1.05V (S5) U6200
EN VOUT RESET*
VIN ISL8009B U1000

06 PP1V05_S5_REG 32
MCP79 11 11-1 U7750 VOUT
P3V3S3_EN RC
P1V05_S5_EN
PM_SLP_S4_L 08 PP5V_S3_REG Q7940
DELAY
SMC 02 PP5VRT_S0_FET
P16
15
VIN
SLP_S3# 11-3 04 P5VS3_EN_L 5V PP5V_S3_REG PP5V_S3
U4900 EN1 VOUT1 17 P5VS0_EN
(RT) (10A MAX CURRENT)
RC
DDRREG_EN SMC_PM_G2_EN
U1400 P60 05
DELAY (S5) Q7800 PP3V3_S5_REG PP3V3_S5 Q7948
VOUT2 07
PP3V42_G3H_REG P3V3S5_EN_L (4A MAX CURRENT) PP5VLT_S0_FET
EN2 3.3V
PCI_RESET0#
Q7910
TPS51125
PPBUS_S0_LCDBKLT_PWR 02 PP3V3_S3_FET
11-2 U7200
15-1
SMC_PM_G2_EN
EN0 13 P5VS0_EN
RC
P5VS3_EN_L PGOOD1,2 VREG3
DELAY VIN
P3V3S3_EN
MC34845 P5V3V3_PGOOD
U9700 PPVOUT_S0_LCDBKLT
VOUT
B 24 SMC
RSMRST_OUT(P15) PM_RSMRST_L
10
B
Q7930 ALL_SYS_PWRGD
AP_PWR_EN Q3801,Q3805 16 PWRGD(P12) 99ms DLY
18 IMVP_VR_ON
NAND PP3V3_S0_FET IMVP_VR_ON(P16) 25
GATE 09 RSMRST_PWRGD
PM_WLAN_EN_L RSMRST_IN(P13)
04-1 SMC_ADAPTER_EN Q3801,Q3805
PLT_RST*
OR SMC_ONOFF_L
GATE PWR_BUTTON(P90)
PM_SLP_S3_L P3V3S0_EN PM_PWRBTN_L
P17(BTN_OUT)
05
Q3810
15 SMC_RESET_L
P3V3_ENET_FET RST*
P1V05S0_LDO_PGOOD
P5V3V3_PGOOD
SLP_S5_L
P3V3ENET_EN_L SLP_S5_L(P95)
MCPCORESO_PGOOD SLP_S4_L
SLP_S4_L(P94)
CPUVTTS0_PGOOD
SLP_S3_L
SLP_S3_L(P93)
PP3V3_S0_PWRCTL
PPVIN_S5_1V5S30V75S0 S3 TO S0
S0PGOOD_PWROK U4900
PP1V5_S0_FET PP1V5_S0 21
FETS
02
(Q7901 & Q7971) 1.8V LDO
VIN TPS62202 PP1V8_S0_REG
19-1
=DDRREG_EN 1.5V PP1V5_S3_REG U7760
S5 VOUT1
(13A MAX CURRENT) RST*
PM_SLP_S3_L =DDTVTT_EN 14
S3 0.75V PP3V3_S0 V1
VOUT2 PP0V75_S0_REG
PP1V5_S0
(1A MAX CURRENT) V2
A RC
DELAY
P1V8S0_EN
16-4 TPS51116
U7300
PP1V05_S0
V3 LTC2909
A
PAGE TITLE
20
PPMCPCORE_S0_R R7525
U7870 Power Block Diagram
RC MCPDDR_EN MCP_CORE VOUT PPMCPCORE_S0_REG DRAWING NUMBER SIZE
RC P3V3S0_EN
DELAY
16-2
DELAY
16-3 MCPCORES0_EN
EN (13A MAX CURRENT) Apple Inc. 051-7982 D
REVISION
RC CPUVTTS0_EN 16-1 ISL6263D

R
C.0.0
16-6 PBUSVSENS_EN NOTICE OF PROPRIETARY PROPERTY: BRANCH
DELAY
U7500 THE INFORMATION CONTAINED HEREIN IS THE
(S0) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PPVIN_S0_MCPCORE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VIN
RC MCPCORES0_EN
16-5 P5VS0_EN
16-1 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
3 OF 109
DELAY 02 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
(S0)
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants
TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS

TABLE_BOMGROUP_ITEM
Bar Code Labels / EEE #’s
639-0035 PCBA,MLB,FOX DDR CONN,K84 K84_COMMON,CPU_2_0GHZ,FOX_DDR_CONN,EEE_8CG
TABLE_BOMGROUP_ITEM
639-0254 PCBA,MLB,MLX DDR CONN,K84 K84_COMMON,CPU_2_0GHZ,MLX_DDR_CONN,EEE_A36
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:8CG] CRITICAL EEE_8CG
TABLE_BOMGROUP_ITEM
085-0748 K84 MLB DEVELOPMENT BOM K84_DEVEL_ENG

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:A36] CRITICAL EEE_A36
TABLE_BOMGROUP_ITEM
639-0554 PCBA,MLB,FOX DDR CONN,PVT K84 K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:CXR] CRITICAL EEE_CXR
TABLE_BOMGROUP_ITEM
639-0555 PCBA,MLB,MLX DDR CONN,PVT K84 K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:CY1] CRITICAL EEE_CY1
TABLE_BOMGROUP_ITEM
085-1076 K84 MLB DEVELOPMENT PVT K84_DEVEL_PVT
D BOM Groups
TABLE_BOMGROUP_HEAD
D
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
K84_COMMON COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_ENG,K84_PROGPARTS
TABLE_BOMGROUP_ITEM
K84_COMMON_PVT COMMON,ALTERNATE,K84_MCP,K84_MISC,K84_DEBUG_PROD,K84_PROGPARTS
TABLE_BOMGROUP_ITEM
K84_MCP MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC
TABLE_BOMGROUP_ITEM
K84_MISC ONEWIRE_PU,DP_ESD,MIKEY,LDO_NO,MEM_SENSE,1P05_HIGH_SIDE_SENSE,MCP_T_DIODE_SENSOR,MCPSMC_DIGITEMP_YES
TABLE_BOMGROUP_ITEM
K84_PROGPARTS BOOTROM_PROG,SMC_PROG,WELLSPRING_PROG
TABLE_BOMGROUP_ITEM
K84_DEBUG_ENG DEVEL_BOM,SMC_DEBUG_YES,XDP
TABLE_BOMGROUP_ITEM
K84_DEBUG_PVT DEVEL_BOM_PVT,SMC_DEBUG_YES,XDP,NO_VREFMRGN
TABLE_BOMGROUP_ITEM
K84_DEBUG_PROD SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN
TABLE_BOMGROUP_ITEM
K84_DEVEL_ENG DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN
TABLE_BOMGROUP_ITEM
K84_DEVEL_PVT XDP_CONN,LPCPLUS
Module Parts
337S3769 1 PDC,SLGVT,2.26,25W,1066,R0,3M,BGA,P7550 U1000 CRITICAL CPU_2_0GHZ
338S0710 1 IC,GMCP,MCP79,35X35MM,BGA1437,B03 U1400 CRITICAL MCP_B03
516S0706 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA J3200 CRITICAL FOX_DDR_CONN
C 516-0201 1 CONN,204P,SODIMM,P=0.6MM J3100 CRITICAL FOX_DDR_CONN

C
516S0790 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,NON/SC J3200 CRITICAL MLX_DDR_CONN
516-0213 1 CONN,204P,SODIMM,P=0.6MM,HF J3100 CRITICAL MLX_DDR_CONN
452-1708 4 SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97 SCREW1,SCREW2,SCREW3,SCREW4 CRITICAL
514-0704 1 CONN,RCPT,RJ45,PLASTIC,HF,K83/K84 J3900 CRITICAL
514-0705
514-0706
2
1
CONN,RCPT,USB,4P,PLASTIC,HF,K83/K84
CONN,RCPT,MDP,20P,PLASTIC,HF,K83/K84
J4600,J4610
J9400
CRITICAL
CRITICAL
K84 BOARD STACK-UP
514-0718 1 CONN,RCPT,S/PDIF,TX,HF,CFR,K83/K84 J6700 CRITICAL
353S2718 1 IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8 U7870 CRITICAL

Top SIGNAL
870-1885 4 POGO PIN,MED,NOISE-IMPROVED,K84 ZS0900,ZS0901,ZS0902,ZS0903 CRITICAL
870-1885 3 POGO PIN,MED,NOISE-IMPROVED,K84 ZS0908,ZS0909,ZS0911 CRITICAL 2 GROUND

870-1886 5 POGO PIN,TALL,NOISE-IMPROVED,K84 ZS0904,ZS0905,ZS0906,ZS0907,ZS0910 CRITICAL
870-1886 5 POGO PIN,TALL,NOISE-IMPROVED,K84 ZS0912,ZS0913,ZS0914,ZS0915,ZS0919 CRITICAL

3 SIGNAL(High Speed)
870-1887 3 POGO PIN,THIN,NOISE-IMPROVED,K84 ZS0917,ZS0918,ZS0916 CRITICAL
104S0033 4 RES,MF,1/4W,6.8OHM,5%,0805,SMD R6612,R6617,R6630,R6633 CRITICAL
518S0774 1 CONN,RCPT,60P,P=0.4,STK HT 1.0 J1300 CRITICAL XDP_CONN 5 GROUND

353S2718
514-0704
IS
IS
NEW INTERSIL PART FOR FIXING B4
CLOUD GREY 4/LB3 PLASTIC W/PDNI
DONGLE ISSUE
PLATING VERSION OF 514-0692 PART FOR RJ45 CONNECTOR
6 POWER
B 514-0705
514-0706
IS
IS
PLATING VERSION
PLATING VERSION
OF
OF
514-0689
514-0691
PART
PART
FOR
FOR
USB CONNECTORS
MINI DP CONNECTOR 7 POWER B
514-0718 IS CLOUD GREY 4/LB3 PLASTIC W/PDNI PLATING VERSION OF 514-0694 PART FOR AUDIO CONNECTOR
DEVELOPMENT BOM 8 GROUND

085-0748 1 K84 MLB DEVELOPMENT BOM DEVEL CRITICAL DEVEL_BOM
085-1076 1 K84 MLB DEVELOPMENT PVT DEVEL_PVT CRITICAL DEVEL_BOM_PVT
Programmable Parts
338S0563 1 IC,SMC,HS8/2117,9X9MM,TLP,HF U4900 CRITICAL SMC_BLANK 11 GROUND
341S2485 1 IC,SMC,K84 U4900 CRITICAL SMC_PROG
335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK

BOTTOM SIGNAL
341S2487 1 IC,PRGRM,EFI BOOTROM,UNLOCK,K84 U6100 CRITICAL BOOTROM_PROG
337S2983 1 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 U5701 CRITICAL WELLSPRING_BLANK
341S2491 1 IC,WELLSPRING CONTROLLER,K84 U5701 CRITICAL WELLSPRING_PROG
LOCKED BOOTROM APN IS 341S2488
Alternate Parts
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM
A 152S0693
152S0796
152S0778
152S0685
ALL
ALL
DALE/VISHAY, MAGLAYERS AS ALTERNATE
CYNTEC AS ALTERNATE
TABLE_ALT_ITEM
PAGE TITLE
157S0058 157S0055 ALL DELTA AS ALTERNATE

TABLE_ALT_ITEM
BOM Configuration
TABLE_ALT_ITEM
DRAWING NUMBER SIZE

138S0603 138S0602 ALL MURATA AS ALTERNATE
TABLE_ALT_ITEM

128S0093 128S0218 ALL KEMET AS ALTERNATE REVISION
152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE

TABLE_ALT_ITEM
R
C.0.0
TABLE_ALT_ITEM
152S0847 152S0586 ALL MAGLAYERS AS ALTERNATE THE INFORMATION CONTAINED HEREIN IS THE
TABLE_ALT_ITEM

104S0018 104S0023 ALL DALE/VISHAY AS ALTERNATE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
4 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Revision History NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
1/19/2009:INITIAL RELEASE 0.0.1-
- ALL PAGES SYNC’ED FROM K24
- REPLACED K24 REFERENCES WITH K84 3/20/2009: RELEASE 7.1.0 (MAJOR)- 3/25/2009: RELEASE 7.3.0 (MAJOR)-
- UPDATED SCHEMATIC AND PCB PART NUMBER INFO
- PAGE 31 & 32: PIN SWAPS ON THE DDR3 CONNECTOR PAGES FOR ROUTING PURPOSES (REFER TO RON’S EMAIL) - DELETED PAGE 71 (5V S3 LT POWER SUPPLY) AS THERE IS NO NEED OF A SEPARATE 5V S3/S0 SUPPLY
1/21/2009: RELEASE 0.0.2- - PAGE 7: DELETED PP5VLT_S3 NETS
- DELETED PAGES 41,42,43,48,97,98,105 [FIREWIRE, IR CONTROLLER, BACKLIGHT CKT] ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.0.0*** - PAGE 7: RENAMED PP5VRT_S3 TO PP5V_S3 ["LT" & "RT" NOMENCLATURE CLEAN-UP]
- UPDATED BOM CONFIGURATIONS - PAGE 8: COMBINED 5V S3 LT AND RT ALIASES INTO ONE =PP5V_S3_REG AND RENAMED NETS
- DELETED IR SPECIFIC NETS ON SATA CONNECTOR -PG. 67, DELETED R6726 (LT & RT NOMENCLATURE CLEAN-UP)
-PG. 66, CHANGED C6610/11/30/31 TO 0.015UF - PAGE 8: DELETED =PPVIN_S3_5VLTS3, =PP5VLT_S3_V5IN NETS
1/21/2009: RELEASE 0.0.3- -PG. 68, ADDED MIKEY MIC LOAD COMPARATOR CKT - PAGE 9: ADDED ALIAS MCP_GPIO_4 FOR MIKEY MIC LOAD DETECT CIRCUIT
- CORRECTD BOM CONFIG TABLES -PG. 68, ADDED R6873 - PAGE 21: UNSTUFFED R2143 PU ON MCP_GPIO_4 AS THERE IS ALREADY A 100K PU ON AUDIO PAGE
-PG. 68, CORRECTED CODEC OUTPUT SIGNALS TABLE COMMENTS - PAGE 45: ADDED APN TEXT NOTE FOR SIL CONNECTOR
1/21/2009: RELEASE 0.0.4- - PAGE 55: ADDED BC846BM NPN TRANSISTOR (APN 372S0129) TO MCP T-DIODE SENSOR CIRCUIT SIMILAR TO
- CORRECTED BOM CONFIG TABLE (ADDED BACK BKLT_ENG) THAT IN CPU T-DIODE SENSOR AND STUFFED C5540
- ADDED BACK PAGES 97-98 (LCD BACKLIGHT DRIVER AND SUPPORT CKT) 3/24/2009: RELEASE 7.2.0 (MAJOR)- - PAGE 72: RENAMED NETS AND NOTES TO REMOVE REFERENCES TO RT POWER SUPPLY
- DELETED KB BACKLIGHT DRIVER/DETECTION CKT - PAGE 72: REPLACED L7260 WITH APN 152S0959 AS PER DAYU
- PAGE 4: CHANGE THE CPU TO NEW APNB 337S3704 - PAGE 72: ADDED C7282 APN 128S0218 IN PARALLEL WITH C7280 AS PER DAYU
1/23/2009: RELEASE 0.0.5- - PAGE 7: DELETED PPBUS_R_G3H AS NO NEED OF TWO PPBUS BRANCHES - PAGE 73: REPLACED Q7320 AND Q7321 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU
- UPDATED PAGES 72-73 : 5V/3.3V & DDR3 POWER SUPPLIES AS PER FLO’S RECOMMENDATIONS - PAGE 8: COMBINED TWO SEPARATE PPBUSA/B BRANCHES INTO ONE =PPBUS_G3H - PAGE 74: REPLACED C7433 AND C7431 WITH 0.001UF CAPS APN 132S1035
- SET SOURCE SYNC OF AUDIO PAGES (62-63, 65-68) FROM LENG’S AUDIO PAGES - PAGE 9: ADDED LVDS HOLE APN 998-1521 - PAGE 75: REPLACED C7576 WITH 0.022UF APN 132S0102 CAP TO INCREASE THE SLEW RATE
- PAGE 34: CHANGED J3401 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA - PAGE 75: ADDED A NOTE OCP=14.5A TO R7575
D 1/27/2009: TMLB FIRST RELEASE 0.0.1-
- NAME CHANGED TO TMLB. SO CALLING IT RELEASE 0.0.1
- UPDATED SCHEM AND PCBF PART NUMBER INFO
- PAGE 45: MIRROR’ED J4500 AND RECONNECTED PINS AS PER NEW PIN OUT DESCRIPTION FROM DIANA
- PAGE 45: CHANGED J4501 ROUTING CONNECTIONS AS PER NEW PIN OUT DESCRIPTION FROM DIANA
- PAGE 50: DELETED SMC_PPBUSA_ISENSE ALIAS AND STUFFED R5055
- PAGE 75: REPLACED Q7560 AND Q7565 WITH CSD58858 APN 376S0790 MOSFETS AS PER DAYU
- PAGE 76: CORRECTED MAX OUTPUT NOTE TO REFLECT 7.2A INSTEAD OF 8A
- PAGE 76: REPLACED Q7620 WITH 2 CSD58858 APN 376S0790 MOSFETS AS PER DAYU
D
- UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_PROD AND BLANK PROGRAMMED PARTS. ALSO, DELETED BMON_ENG BOM OPTION - PAGE 54: DELETED U5470 INA210 CIRCUIT AS THERE IS NO NEED - PAGE 77: ADDED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL VIA A 0 OHM RESISTOR TO PIN 3 (PG) OF THE LDO
- PAGE 54: REMOVED BMON CURRENT SENSE CIRCUIT - PAGE 70: REMOVED R7080 SENSE RESISTOR AND RENAMED =PPBUSB_G3H TO =PPBUS_G3H AS NO NEED - PAGE 78: DELETED P5V_LTS3_PGOOD AS THERE IS NO 5V LT POWER SUPPLY ANYMORE
- REMOVED ALS SPECIFIC NETS (PAGE 34 & 52) TO HAVE TWO PPBUS BRANCHES - PAGE 78: RENAMED =P5VRTS3_EN_L TO =P5VS3_EN_L
- PAGE 70: DELETED R7050 CONNECTION BETWEEN CHGR_AGATE AND CHGR_LOWCURRENT_GATE - PAGE 78: ROUTED P1V05S0_LDO_PGOOD POWER GOOD SIGNAL TO THE WIRED AND CIRCUIT
2/5/2009: RELEASE 0.0.2 - AS PER DAYU
- COPIED TMLB OVER TO MLB AS K84 WILL BE PENRYN SKU WHILE K83 WILL BE ATOM SKU - PAGE 70: ADDED R7050 (6259_YES) CONNECTION FROM PIN 4 (VREF) TO PM_SLP_S3_L AS PER DAYU
- UPDATED THE SCHEMATICS, PCBF AND PCBA PART NUMBER INFO - PAGE 70: AS PER DAYU, ADDED:
- REPLACED TEXT TMLB WITH MLB THROUGH OUT THE SCHEMATICS R7051 (6259_YES) CONNECTION BETWEEN CHGR_PIN26 AND CHGR_LOWCURRENT_GATE; 3/26/2009: RELEASE 7.4.0 (MAJOR)-
- PAGE 4: UPDATED BOM OPTION TABLE TO REFLECT K84_DEBUG_ENG FOR K84_COMMON BOM GROUP R7052 (6259_NO) CONNECTION BETWEEN CHGR_PIN26 AND GND_CHGR_SGND;
- PAGE 4: UPDATED EEE NUMBER - 8CG R7053 (6259_YES) CONNECTION BETWEEN CHGR_PIN6 AND PIN 12 (VHST); - PAGE 60: REPLACED DUAL PACKAGE OPA330 OPAMPS WITH SINGLE PACKAGE ONES - APN 353S2179
- PAGE 4: ADDED 085 DEVELOPMENT BOM VARIANT & K84_DEVEL_ENG, K84_DEVEL_PVT BOM GROUPS R7054 (6259_NO) CONNECTION BETWEEN CHGR_PIN6 AND GND_CHGR_SGND [U6030, U6031, U6040, U6041]. ALSO, ADDED C6031 & C6041
- PAGE 7: DELETED IR_RX_OUT, PP5V_S3_IR_R, KBDLED_ANODE, SMC_KBDLED_PRESENT_L - PAGE 73: RENAMED TEXT NOTE FOR =PP1V5_S3_REG NET TO VOLTAGE=1.5V - PAGE 9: DELETED EXTRA MEDIUM POGO PIN ZS0912 AND SCREW HOLES Z0908, Z0909
- PAGE 8: DELETED FIREWIRE, IR AND BMON SPECIFIC NETS - PAGE 97: STUFF R9716 AS PER KIRAN’S FEEDBACK
- PAGE 9: DELETED R0950 PCIE_FW_PRSNT_L ’S PD RESISTOR 3/26/2009: RELEASE 7.5.0 (MAJOR)-
- PAGE 9: ADDED UNUSED FIREWIRE LANE NETS AS TEST POINTS
- PAGE 9: CHANGED ALIAS OF FW_PME_L TO TP_FW_PME_L - PAGE 73: ADDED SHORT XW7304 FROM PIN 1 OF C7300 TO POWER GND (PIN 18)
- PAGE 9: ADDED SMC_SYS_KBDLED TP ALIAS - PAGE 72: REPLACED C7282 WITH OSCON APN 128S0248 IN PARALLEL WITH C7280 AS PER DAYU
- PAGE 55: REPLACED CPU/MCP THERMAL SENSORS U5515 ANDB U5535 WITH THE CHEAPER VERSION APNB 353S2573
- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 & C7240 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS
- PAGE 72: REPLACE Q7220 WITH SIZ700DT 3/26/2009: RELEASE 7.6.0 (MAJOR)-
- PAGE 73: REPLACE 16V INPUT SIDE CAPS C7331 WITH 39UF APN 128S0248 AS PER DAYU’S RECOMMENDATIONS
- PAGE 76: REPLACE Q7620 WITH SIZ700DT - ADDED PLACEMENT NOTES TO XW SHORTS AS PER DAYU
- ADDED OMIT BOM OPTION TO ALL THE XW SHORTS
2/6/2009: MAJOR RELEASE 0.1.0 - - ADDED DIDT=TRUE ATTRIBUTE TO BOOT/VBST SIGNALS OF ALL THE SWITCHING SUPPLIES
- NO CHANGES SINCE LAST MINOR RELEASE 0.0.2 - PAGE 8: DELETED =PP3V42_G3H_BATT AS THERE IS NO BIL CONNECTOR
- PAGE 8: ADDED =PP3V42_G3H_HALL FOR THE HALL EFFECT CONNECTOR
2/6/2009: WEEKLY RFA BOM RELEASE 1.0.0- - PAGE 8: ADDED =PP3V3_S3_AUDIO ALIAS NET FOR CASEY’S NEW CHANGES BELOW
- NO CHANGES SINCE LAST MAJOR RELEASE 0.1.0 - PAGE 8: DELETED =PP3V42_G3H_PPBUSAISNS AS PPBUS SENSE CIRCUIT HAS BEEN REMOVED
- PAGE 8: RENAMED ALIAS =PP5V_S3_P5VS0FET TO =PP5V_S3_P5VLTS0FET AS THIS GOES TO 5V LT S0 FET CIRCUIT
2/15/2009: RELEASE 2.0.0 (WEEKLY RFA)- - PAGE 8: ADDED =PP5V_S3_P5VRTS0FET ALIAS, GOING TO 5V RT S0 FET CIRCUIT
1. PAGE 3: POWER BLOCK DIAGRAM - ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR. ALSO, ADDED SENSE RESISTOR ON PPBUS - PAGE 8: ADDED PLACEMENT NOTE TO Q5502
2.CKT
E PAGE 8: ADDED TWO ALIASES OF PPBUS (PPBUSA_G3H & PPBUSB_G3H). PPBUSA_G3H FEEDS CORE REGULATORS: CPUVTT, MCP VCORE, CPU VCORE & DDR, WHILE PPBUSB FEEDS 5V/3.3 V SUPPLY, LCD BKLT & PPBUS VOLTAGE SENS - PAGE 9: ADDED OMIT ATTRIBUTE TO THE LVDS HOLE
3. PAGES 31, 32: REPLACED 0.1UF 0204 TYPE DDR3 DECOUPLING CAPS WITH 0402 TYPE CAPS ( APPLE P/N : 132S1059) - PAGE 69: ADDED HALL EFFECT CONNECTOR CIRCUIT J6955 APN 516S0787
4. PAGE 34: REPLACED AIRPORT CONNECTOR WITH PN 516S0580 AND UPDATED CONNECTIONS ACCORDINGLY - PAGE 79: RENAMED INPUT VOLTAGE NETS OF 5V S0 FET CIRCUITS TO REFLECT RT AND LT
5. PAGE 34: REPLACED SCHMITT’S TRIGGER WITH PN 311S0449 (MATCHES UPDATED ALIASES ON PAGE 8)
6. PAGE 45: REPLACED SATA HDD CONNECTOR WITH APPLE PN 516S0350 AND UPDATED CONNECTIONS ACCORDINGLY
7. PAGE 45: ADDED 2 PIN CONNECTOR (APPLE PN 518S0519) FOR SIL
8. PAGE 46: REPLACED ESD DIODES WITH CHEAPER PN 377S0066 ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 7.5.0***
9. PAGE 54: ADDED BOM OPTION- DEBUG_SENSE- TO CPU 1.05V/CPU VCORE HIGH SIDE CURRENT SENSE AND MCP MEM VDD CURRENT SENSE CIRCUITS FOR DEVELOPMENT BOM -PG. 67, ADDED R6725
10. PAGE 4: ADDED DEBUG_SENSE BOM OPTION TO THE K84_DEVEL_ENG BOM GROUP -PG. 67 ADDED =PP3V3_S3_AUDIO NET
11.
UPDATED
PAGE THESE
58: DELETED
NET NAMES
IPD ON
FLEX
PAGE
CONNECTOR
7 ALSO J5800. RENAMED PP18V5_S3, PP3V3_S3_LDO_R, PP3V3_S3_LDO TO PP18V5_S3_LDO, PP3V3_S3_IPD_R AND PP3V3_S3_IPD RESPECTIVELY TO MATCH WITH NEW ADDED PAGE 60 NET NAMES. -PG. 67, DELETED L6706
12. ADDED PAGE 60 AND COPIED OVER ZEPHYR2 SCHEMATICS PAGE FROM M97 IPD_FLEX_WELLSPRING. DELETED THE IPD BOARD CONNECTOR. CALLING IT WELLSPRING 3 -PG. 67, ADDED XW6702
13. PAGE 69: REPLACED BATTERY CONNECTER WITH PN 518S0540 AND BIL CONNECTOR WITH PN 518S0588. UPDATED CONNECTIONS ACCORDINGLY -PG. 66, UPDATED 5V S3 ALIAS NOTES
14. PAGE
POWER) ALIAS
70: ON
DIVIDED
PAGE 8
PPBUS INTO TWO BRANCHES - PPBUSA & PPBUSB. ADDED SENSE RESISTOR R7080 (2 MOHMS) ON PPBUSA. ALSO ADDED INA210 AMPLIFIER CKT ACROSS SENSE LINES. ADDED PP3V42_G3H_PPBUSAISNS (IN210 -PG. 67, NO STUFFED R6724
15: PAGE 97: REPLACED BKLT DRIVER CKT WITH THAT OF FREESCALE PART, SIMILAR TO K19I
16. PAGE 69: MOVED THE DECAP C6908 TO CORRECT PART U6901.5 ( SIMILAR TO K24)
17. PAGE 4: REMOVED BKLT_ENG BOM OPTION
3/29/2009: RELEASE 8.0.0 (RFA)-
***PAGES SYNC’ED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 1.0.0***
1. REPLACED MIKEY CD3272 WITH CD3282 - PAGE 7: SCRUBBED THROUGH THE FUNCTIONAL TEST POINTS AGAINST TOM’S SPREADSHEET
C 2. ADAPT JACK INSERT DETECT CIRCUIT TO CD3282 JACK INSERT DETECT FUNCTION.
3. REMOVED JACK EXTRACT CIRCUITRY, FUNCTION IS TAKEN OVER BY CD3282
4. REMOVE FM ANTENNA NET.
3/6/2009: RELEASE 6.0.0 (RFA:)-
- PAGE 4: ADDED 152S0693 AS ALT FOR 152S0778 FOR SUPPLY REDUNDANCY
- PAGE 7: RENAMED RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR
- PAGE 7: DELETED BATT SIGNAL CONN AND ADDED HALL EFFECT CONNECTOR TEST POINTS
- PAGE 7: DELETED THERMAL FUNC_TEST SECTION
C
- PAGE 4: ADDED 138S0603 AS ALT FOR 138S0602B FOR SUPPLY REDUNDANCY - PAGE 9: ADDED TP_ ALIASES FOR - CARDREADER_RESET, USB_CARDREADER_N/P, AND
***PAGES SYNC’ED FROM K24 SINCE LAST RELEASE 1.0.0*** - PAGE 4: ADDED CYNTEC ALTERNATES FOR 107S0074 --> 107S0138 [R7020] AND 107S0075 USB_IR_N/P
1. PAGE 75: MCP VCORE INDUCTOR CHECK FOR PD: CHANGED L7560 TO 152S0966 AND THEN TO 152S0867. BUT NOW IT IS BACK TO 13A PART FOR NOW [R7008] --> 107S0139 - PAGE 9: FIXED BAD_TP_NC NETS - TP_RTL8211_CLK125, TP_PP3V3_ENET_PHY_VDDREG
2. ADDED DIDT TO ALL THE GATE AND PHASE NETS - PAGE 4: ADDED DALE/VISHAY ALTERNATES FOR 104S0023 --> 104S0018 - PAGE 9: DELETED Z0912 MLB MOUNTING HOLE AS NO LONGER NEEDED
- PAGE 4: ADDED BOM OPTION 6259_NO TO THE TABLE UNDER K84_MISC BOM GROUP - PAGE 34: RENAMED TITLE: RIGHT CLUTCH CONNECTOR TO X16 WIRELESS CONNECTOR
- PAGE 7: DELETED SMC_BIL_BUTTON_L NET FROM BATT SIGNAL CONN GROUP AS BIL IS NO LONGER A POR - PAGE 50: REPLACED R5030 WITH APN: 114S0114,(IT’S A 1% TOL, 1/16W, 0402, 84.5OHM RESISTOR)
2/25/09: WEEKLY RFA RELEASE (3.0.0) - PAGE 8: DELETED =PP3V42_G3H_AUDIO AS IT IS NO LONGER USED - PAGE 66: FIXED UNNAMED NETS CONNECTED TO - R6632
- ADDED DIDT ATTRIBUTE - PAGE 8: DELETED =PP3V3_S0_TPAD AS THERE IS NO KEYBOARD BACKLIGHT DRIVER - PAGE 74: FIXED UNNAMED NETS CONNECTED TO - XW7401, XW7402, XW7403 AND XW7404
- PAGE 4: REMOVED SUPERCAP_NO BOM OPTION. ADDED DEBUG_ADC BOM OPTION UNDER K84_DEVEL_ENG - PAGE 8: DELETED =PP3V42_G3H_5V3V3_EN AS IT IS NO LONGER USED - PAGE 78: FIXED BAD_TP_NC NETS - TP_DDRREG_PGOOD
(THIS IS FOR NEW SENSOR PAGE 60) - PAGE 9; ADDED 3 ADDITIONAL TALL POGO PINS AS PER NEW MCO AND DELETED ZS0909 SHORT POGO AS IT WAS EXTRA - PAGE 76: REPLACED L7620 WITH ITS REPLACEMENT - APN 152S0518
- PAGE 4: CORRECTED APN FOR PROGRAMMED PARTS - SMC, BOOT ROM, WELLSPRING - PAGE 9: ADDED TP ALIASES TO IMVP6_VR_TT AND IMVP6_NTC - PAGE 69: CHANGE PIN OUTS OF J6955 AS PER CHINMAY
- PAGE 4: REMOVED LDO_YES BOM OPTION - PAGE 34: ADDED LC FILTER (L3406 AND C3432) ON PP3V3_S3_BT POWER RAIL AS PER JOHN SCHEN’S FEEDBACK
- PAGE 8: DIVIDED PP5V_S0_FET INTO TWO BRANCHES - PP5VRT_S0_FET & PP5VLT_S0_FET (FOR ROUTING PURPOSE, - PAGE 34: REPLACED THE AIRPORT CONNECTOR WITH 1.8 MM HEIGHT CONNECTOR APN 516S0582
5V S3 IS DIVIDED INTO RT AND LT POWER SUPPLY AND WILL HAVE CORRESPONDING S0 FETS) - PAGE 39: REPLACED ETHERNET CONNECTOR WITH THAT OF M97A/K24 PART APN 514-0636 (SYNC’ED WITH K24) 3/31/2009: RELEASE 9.0.0 (RFA)-
- PAGE 8: DIVIDED PP5V_S3_REG INTO TWO BRANCHES - PP5VRT_S3_REG & PP5VLT_S3_REG - PAGE 45: RENAMED =PP5V_S0_HDD_R TO PP5V_S0_HDD_R (AS PER UNALIASED.LST REPORT)
- PAGE 8: ADDED PP5V_S3_DEBUG_ADC_AVDD/DVDD & PP5V_S3_DEBUG_ISNS ALIASES FOR NEW SENSOR PAGE 60 - PAGE 50: ADDED UNUSED NET ALIAS FOR SMC_BIL_BUTTON_L (NC_SMC_BIL_BUTTON_L) - PAGE 4: DELETED DEBUG_SENSE BOM OPTION AND ADDED MEM_SENSE AND
- PAGE 8: ADDED PP3V3_S3_BT ALIAS FOR BLUETOOTH ON RIGHT CLUTCH CONNECTOR PAGE - PAGE 52: DELETED TERM BIL FROM SMC BATTERY & BIL CONNECTIONS 1P05_HIGH_SIDE_SENSE OPTIONS UNDER K84_COMMON BOM GROUP
- PAGE 8: ADDED ALIAS PPVIN_S3_5VLTS3 UNDER PPBUSB - PAGE 57: ADDED PLACEMENT NOTES TO C5702 AND C5704 AS PER JOHN SCHEN’S FEEDBACK - PAGE 4: ADDED MCP_T_DIODE_SENSOR, MCPSMC_DIGITEMP_NO BOM OPTIONS UNDER
- PAGE 8: ADDED ALIAS PP5VLT_S3_V5IN UNDER PP5VRT_S3_REG - PAGE 59: REPLACED SMS PART WITH THE NEW BOSCH BMA141 ANALOG PART. ADDED R5923 10K PU RESISTOR ON K84_COMMON BOM GROUP
- PAGE 28: REMOVED RTC POWER SOURCES CIRCUIT AND SUPERCAP_NO BOM OPTION FROM R2820 SEL1 SIGNAL AND REMOVED 10K PD ON ST PIN. REPLACED C5926 WITH 0.01UF CAP AS PER DATA SHEET. AND, - PAGE 4: ADDED SHORT POGO PIN 870-1699 AS ALTERNATE FOR THE MEDIUM ONES
- PAGE 34: SINCE X16 AIRPORT CARD SOLUTION IS BEING USED, PP5V_S3_WLAN IS REPLACED BY PP3V3_S3_WLAN REPLACED C5923-C5925 CAPS WITH 0.033 UF VALUES FOR CUT-OFF FREQUENCY OF ~146HZ - PAGE 4: UPDATED DESCRIPTION FOR THE CPU
(GOING TO Q3450). ALSO, REPLACED PP5V_WLAN WITH PP3V3_WLAN ON PAGE 6 (FUNCTIONAL TEST POINTS) - PAGE 60: CORRECTED PLACEMENT NOTE ASSOCIATED TO XW6080 TO REFLECT D9710 INSTEAD OF D9701 - PAGE 7: UPDATED TPS AS PER NEW UPDATE FROM TOM (SPREADSHEET ATTACHED TO THE RADAR)
- PAGE 34: R3453 IS MODIFIED TO 110K RESISTOR, R3454 IS NOSTUFF AND R3453 IS PULLED UP TO PP3V3_WLAN_F. - PAGE 69: CHANGED L6995 TOB APN 152S1017 FOR COT SAVING AND EFFICIENCY - PAGE 12: REPLACED C1260 WITH APN 128S0267 AS PER DAYU
THIS IS TO ENSURE 3.3V LEVEL AT THE INPUT OF U3402 AND MAINTAIN 100MS DELAY SPEC BETWEEN 3.3V POWER - PAGE 69: REMOVED BIL CIRCUIT AS IT NO LONGER A POR [R6960, C6954, D6951, C6953, C6952, J6955, C6951] - PAGE 34: DELETED TEXT NOTE ASSOCIATED WITH J3401
TO THE CARD GETTING STABLE AND AIRPORT GETTING OUT OF RESET - PAGE 70: MOVED C7028 TO PPVBAT_G3H_CHGR_REG AS PER JOHN SCHEN’S FEEDBACK - PAGE 45: ADDED VOLTAGE, MIN LINE AND NECK WIDTH FOR PP5V_S0_HDD_FLT
- PAGE 34: DISCONNECTED PP5V_S3_BTCAMERA_F POWER RAIL FROM THE CONNECTOR AND REPLACED IT WITH PP3V3_S3_BT - PAGE 70: ADDED PLACEMENT NOTE TO C7027 AS PER JOHN SCHEN’S FEEDBACK - PAGE 52: ADDED 0 OHMS STUFFING OPTION TO CONNECT MIKEY SMBUS CONNECTIONS TO MCP SMBUS 0.
(SIMILAR TO M96). CAMERA SIGNALS ARE ROUTED VIA LVDS CONNECTOR. MOVED PP5V_S3_BTCAMERA POWER CIRCUIT - PAGE 70: REPLACED R7080 WITH APN 107S0142 WHICH IS TRUE 4-TERMINAL SENSE RESISTOR WITH SMALLER PACKAGE ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0 OHMS
ALONG WITH THE USB CAMERA SIGNALS TO LVDS PAGE. ALSO, RENAMED THIS POWER RAIL TO PP5V_S3_CAMERA ON LVDS (DAYU’S RECOMMENDATION) - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN MIKEY AND MCP SMBUS 1 CONNECTIONS.
PAGE - PAGE 70: ADDED BOM OPTION 6259_YES TO R7050 AND 6259_NO TO U7060 AND AMON PULLDOWN LOGIC AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_NO WITH THESE 0 OHMS
- PAGE 34: ADDED SENSE RESISTOR R3452 ON PP3V3_WLAN SIGNAL CIRCUIT COMPONENTS. TURNED ON 6259_NO, FOR NOW, ON PAGE 4 TABLE - PAGE 52: ADDED 0 OHMS STUFFING OPTION BETWEEN SMC B SMBUS AND MCP SMBUS 1
- PAGE 34: ADDED CHOKES ON PCIE TX/RX SIGNALS. UPDATED PAGE 6 (FUNCTIONAL TEST POINTS) ACCORDINGLY - PAGE 72: CONNECTED SMC_PM_G2_EN SIGNAL TO EN0 PIN 13 OF U7200 VIA A 100K RESISTOR FOR KEEPING THE POWER SUPPLY CONNECTIONS. AND, ASSOCIATED BOM OPTION MCPSMC_DIGITEMP_YES WITH THESE 0
- PAGE 34: REPLACED L3404 WLAN INDUCTOR WITH LOW DCR 0603 PART - APN 155S0367 OFF IN CASE IF SMC TURNS OFF OHMS
- PAGE 39: REPLACED ETHERNET CONNECTOR WITH APN 514-0668 (SIMILAR TO K36B) - PAGE 72: ADDED PLACEMENT NOTE TO C7230 AS PER JOHN SCHEN’S FEEDBACK - PAGE 52: ADDED BOM OPTION MCPSMC_DIGITEMP_NO TO R5230 AND R5231
- PAGE 72: REMOVED NOSTUFF’ED C7251 AS PER DAYU - PAGE 54: REPLACED DEBUG_SENSE BOM OPTION WITH MEM_SENSE FOR MCP MEMORY VDD
- PAGE 45: CHANGED SATA HDD CONNECTOR TO APN 516S0616 - PAGE 73: REPLACED C7307,C7308 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY) CURRENT SENSE CIRCUIT AND WITH 1P05_HIGH_SIDE_SENSE FOR CPU 1.05V AND
- PAGE 45: ADDED SENSE RESISTORS R4598 AND R4599 ON 5V ODD AND 5V HDD RAILS RESPECTIVELY - PAGE 73: ADDED PLACEMENT NOTE TO C7333 AS PER JOHN SCHEN’S FEEDBACK CPU VCORE HIGH SIDE CURRENT SENSE CIRCUIT
- PAGE 50: UNSTUFFED R5055 AND USED SMC_NB_MISC_ISENSE SIGNAL PORT (SMC) FOR CONNECTING PPBUSA ISENSE SIGNAL. - PAGE 73: DELETED NOTES AT THE BOTTOM RIGHT AFTER CONSULTING WITH DAYU - PAGE 55: ADDED MCP_T_DIODE_SENSOR BOM OPTION TO THE MCP T-DIODE THERMAL
ADDED ALIAS ON THIS PAGE - PAGE 73: MOVED C7344 NEXT TO R7350 AND ADDED PLACEMENT NOTE (JOHN SCHEN WANTED IT TO BE NEXT TO L7320 SENSOR CIRCUIT
- PAGE 51: REPLACED TWO DEMUX SOLUTION WITH A SINGLE DEMUX 1X2 SOLUTION. APN USED - 353S2220 DAYU PERFERRED IT TO BE AFTER THE SENSE RESISTOR - PAGE 59: DELETED R5923 FROM THE TEXT NOTE
[ONLY CHIP SELECT IS BEING DEMUXED] - PAGE 74: ADDED PLACEMENT NOTES TO C7419,C7422 AND C7423 AS PER JOHN SCHEN’S FEEDBACK - PAGE 60: MANUALLY UPDATED RESISTORS VALUES (VOLTAGE DIVIDERS,AMPLIFIER GAINS, RC) TO MATCH WITH
- PAGE 51: R5156, R5157 AND R5158 ARE NOW 0 OHM ISOLATION RESISTORS PLACED ON SPI BUS NEXT TO THE LOCATION WHERE - PAGE 74: STUFFED C7432 AS PER DAYU K19I UPDATES, EXCEPT VOLTAGE DIVIDER FOR PP3V3_WLAN [K19I USES 5V RAIL]. FOR
IT BRANCHES INTO TWO - ONE GOING TO MLB SPI ROM AND THE OTHER GOING TO LPC CONNECTOR. THESE RESISTORS ARE - PAGE 74: REMOVED C7400, C7402, R7451 AND R7452 AS PER DAYU PP3V3_WLAN, R6010 HAS BEEN CHANGED TO 634K TO GET VDIVIDER = ~2V
PLACED ON THE LPC CONNECTOR BRANCH. THIS IS TO AVOID STUBS IN PRODUCTION - PAGE 75: ADDED PLACEMENT NOTE TO C7563 AS PER JOHN SCHEN’S FEEDBACK - PAGE 75: ADDED C7590 (2.2UF) APN 138S0579 IN PARALLEL WITH C7563 AS PER DAYU
- PAGE 52: ADDED SENSOR ADC CONNECTION BLOCK UNDER ’SMC 0 SMBUS CONNECTIONS’ SECTION - PAGE 74: CHANGE L7400 AND L7401 TO 152S1019 AS PER DAYU FOR COST SAVING. ALSO, UPDATED ASSOCIATED TEXTS - PAGE 102: ADDED CONN_PCIE_MINI_R2D_P/N AND CONN_PCIE_MINI_D2R_P/N NETS IN THE
- PAGE 54: MOVED PBUS INA210 CIRCUIT TO THIS CURRENT SENSOR PAGE. RENAMED REF DES AS PER THIS PAGE 54 - PAGE 75: MOVED C7569 TO PPMCPCORE_S0_R AS PER JOHN SCHEN’S FEEDBACK CONSTRAINT SET
- PAGE 55: DELETED J5590 CONNECTOR (CONNECTED TO HEAT-PIPE TEMPERATURE DETECTION RAILS) - PAGE 90: ADDED EMI CAPS (C9017-C9025) ON I2C, LED_RETURNS AND LCD_BKLT POWER RAILS GOING TO LVDS. - PAGE 70: ADDED TP TO PIN 13
- PAGE 55: REPLACED U5515 & U5535 WITH CHEAPER APN 353S2571 ADDED PLACEMENT NOTES TOO - PAGE 4: ADDED MIKEY_LOAD_DET BOM OPTION UNDER K84_MISC BOM GROUP
- PAGE 60: REMOVED WELLSPRING 3 PAGE (GOING BACK TO K24 SOLUTION) AND REPLACED IT WITH K19I DEBUG SENSOR PAGE (SCHUTIL SYNC) - PAGE 94: REPLACED C9486 WITH APN 138S0654 (ADDS ADDITIONAL AVL FOR SUPPLY REDUNDANCY)
- PAGE 61: RENAMED SPI SIGNALS TO MATCH WITH CHANGES ON PAGE 51 ***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 8.0.0***
- PAGE 69: ADDED BOM OPTION NOSTUFF TO D6950 FOR NOW ***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 5.0.0*** - CHANGED R6211 & R6212 FROM 39 OHMS TO 22 OHMS
B - PAGE 69: ADDED D6951 ESD DIODE ON BIL SMBUS SIGNALS (NOSTUFF FOR NOW)
- PAGE 69: REPLACED BATTERY CONNECTOR J6950 WITH APN 518S0540 (M96) CONNECTOR
- PAGE 70: ADDED BYPASS 0 OHM RESISTOR R7050 (NOSTUFF FOR NOW) OPTION FOR NEW CHIP WHICH WON’T REQUIRE U7060 SOLUTION
-PG. 67, CHANGED U6700 CB INPUT TO BE CONTROLLED BY CS4206 GPIO0.
-PG. 62, CHANGED TP_AUD_GPIO_0 TO AUD_GPIO_0.
-PG.66, REPLACED THE LM48310’S (U6610/20/30) WITH LM48311’S
- DELETED NOTE ABOVE U6500
- ADDED BOMOPTION = MIKEY_LOAD_DET ATTRIBUTE TO R6870, R6871, C6870,
- UPDATED SIGNAL PATH CHART TO INCLUDE MCP79 GPIO ASSIGNMENTS
B
- PAGE 71: ADDED NEW PAGE FOR PP5V_LT_REG POWER SUPPLY. UPDATED ALL THE REF DES AS PER THE PAGE NUMBER -PG. 67, CONNECTED HP OUTPUTS TO NC OF U6700 AND LINE INPUTS TO NO OF U6700. - ADDED BOMOPTION = MIKEY ATTRIBUTE TO R6860, C6860, Q6802, R6864, R6865, & R6861
- PAGE 72: REPLACE 16V INPUT SIDE CAPS C7280 WITH 68UF OSCON CAP (APN 128S0275) & C7240 WITH 39UF (APN 128S0248) -PG. 68, CHANGED AUD_PORTB_DET_L TO AUD_PORTA_DET_L. C6871, U6870, C6872, R6872, & R6873
- PAGE 71: CHANGED C7160 TO 39UF OSCON CAP (APN 128S0248) -PG. 68, CHANGED AUD_PORTG_DET_L TO AUD_PORTB_DET_L. - REMOVED NOTE RE: ROUTING TO MCP79 GPIO ABOVE U6870
- PAGE 72: REPLACE Q7220 WITH SIZ700DT AND L7260 WITH SMALLER 10A PART (APN 152S0778) -PG. 67, SET MIN. LINE AND NECK WIDTHS FOR AUD_CONN_L AND AUD_CONN_R - REMOVED BOMOPTION = NOSTUFF ATTRIBUTE FROM R6724
- PAGE 73: ADDED SENSE RESISTOR R7350 ON 1.5V DDR3 SUPPLY RAIL - ADDED BOMOPTION = NOSTUFF ATTRIBUTE TO R6725
- PAGE 77: REMOVED 1.05V S0 PLL LDO CIRCUIT. AND, REMOVED LDO_NO BOM OPTION FROM R7745 ***PAGES SYNCED FROM K24 SINCE LAST RELEASE 5.0.0***
- PAGE 75: CHANGED C7571 & C7560 TO 68UF OSCON CAPS (APN 128S0275) - PAGE 25: CHANGED C2500,C2501,C2502,C2503,C2515,C2520,C2528,C2540,C2580,C2582,C2584,C2586,C2588,
- PAGE 78: RENAMED P5VS3_EN_L TO P5VRTS3_EN_L (RT POWER SUPPLY ENABLE) AND ADDED R7814, C7814 S3 ENABLE CIRCUIT C2595 TO 138S0653 4/1/2009: RELEASE 9.1.0 (MAJOR)-
FOR GENERATING P5VLTS3_EN ENABLE SIGNAL FOR LT POWER SUPPLY - PAGE 26: CHANGED C2615,C6210 TO 138S0653
- PAGE 78: ADDED P5V_LTS3_PGOOD POWER GOOD SIGNAL (WIRED AND WITH OTHER S0 RAILS PGOOD) CORRESPONDING TO 5V LT - PAGE 77: CHANGED U7740 TO 500MA 1.05V LDO - PAGE 4: CHANGED MCP P/N TO 338S0702 AS PER CHALLEE
POWER SUPPLY - PAGE 52: FIXED SENSOR ADC SMBUS CONNECTIONS (BOTH SCL AND SDA WERE WRONGLY CONNECTED
- PAGE 78: ADDED 0 OHM ISOLATION RESISTORS ON POWER GOOD SIGNALS (BEFORE WIRED AND) TO SMB_0_S0_DATA NETS
- PAGE 79: ADDED 5V LT S0 FET AND UPDATED NET NAMES FOR BOTH RT AND LT S0 FET CIRCUITS ACCORDINGLY 3/17/2009: RELEASE 7.0.0 (RFA)- - PAGE 69: REFRESHED HALL EFFECT SENSOR WITH THE NEW SYMBOL
- PAGE 90: UPDATED LVDS CONNECTOR CONNECTIONS AS PER STEVE’S RECOMMENDATION. ADDED CAMERA SIGNALS - ADDED PLACEMENT NOTES (ATTRIBUTE) TO ALL XW SHORTS - PAGE 90:RE-ROUTED LED_RETURN SIGNALS FOR LAYOUT FEASIBILITY(CHIP WAS MOVED TO TOP SIDE)
- PAGE 97: ADDED BOM OPTION - NOSTUFF- TO R9702 AS PER K19I - PAGE 4: DELETING ENTRIES FOR 107S0138 AND 107S0139 FROM ALTERNATES PARTS TABLE AS THEY WOULD BE REPLACING - PAGE 90: ADDED C9017 (1000PF) CAP AS PER JOHN SCHEN
- PAGE 8: DELETED PP5V_S0_BKL, RENAMED PP1V05_S0_MCP_PLL_UF_R TO PP1V05_S0_MCP_PLL_UF THE 107S0074/75 PARTS - PAGE 97: FIXED THE LCDBKLT_VIN SIGNAL NAME ASSOCIATION TO THE CORRECT NET INSTEAD OF
- PAGE 8: DELETED PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_BKL_VDDIO, PP3V3_S0_MCP_PLL_VLDO - PAGE 7: RENAMED PP5V_S3_BTCAMERA_F WITH PP3V3_S3_BT_F R9730 PIN
- PAGE 8: RENAMED PPVIN_S5_1V5S3_0V75S0 TO PPVIN_S5_1V5S30V75S0 - PAGE 7: DELETED PP5V_S0, PP5V_S3 AND ADDED PP5VRT_S0,PP5VLT_S0, PP5VRT_S3, PP5VLT_S3 DEBUG - PAGE 97: DISCONNECTED PGND (OF CAPS) FROM XW9700 AND ADDED A SEPARATE XW9701
- PAGE 28: DELETED FW_RESET_L SIGNAL VOLTAGE TEST POINTS SHORT TO ISOLATE NOISY PGND FROM THE SYSTEM GND. NAMED IT
- PAGE 58: DELETED KB BKLT CIRCUIT - PAGE 7: ADDED PPBUS_R_G3H DEBUG VOLTAGE TEST POINT GND_LCDBKLT_PGND AND ASSIGNED MIN_LINE/NECK_WIDTH ATTRIBUTES
- PAGE 60: UPDATED WLAN DIVIDER CIRCUIT WITH 3V3 POWER RAIL INSTEAD OF 5V - PAGE 8: DELETED ALIAS =PP1V05_S0_SMC_LS AS IT IS NO LONGER NEEDED - PAGE 97: RENAMED GND_LCDBKLT TO GND_LCDBKLT_SGND
- PAGE 73: UPDATED 1.5V/0.75V POWER SUPPLY WITH CORRECT NET NAMES REFLECTING 1.5V/0.75V INSTEAD OF 1.8V/0.9V AND - PAGE 9: REMOVING 2 EXTRA TALL POGO PINS (ZS0911, ZS0912) AS PER NEW MCO - PAGE 97:DISCONNECTED PINS 2 AND 5 FROM GND PINS(13,19,21)AND CONNECTED SEPARATELY TO
IN SYNC WITH PAGE 8 ALIASES - PAGE 9: REPLACED 5 SHORT POGO PINS WITH MEDIUM ONES AND ADDED THREE EXTRA MEDIUM ONES (TOTAL MEDIUM SYSTEM GND
- PAGE 4: REMOVED 152S0778 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE SINCE L7260 AS HAS BEEN REPLACED WITH THIS PART POGO PINS = 8) AS PER NEW MCO - PAGE 97: REPLACED D9710 WITH 40V PART- APN 371S0580 AS PER DEREK
- PAGE 4: REMOVED 104S0018 ALTERNATE PART ENTRY FROM THE ALTERNATE PARTS TABLE - PAGE 34: REPLACE Q3450 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 - PAGE 97: STUFFED R9726 AND SWAPPED C9705 AND R9705 AS PER FREESCALE FOR COMPENSATION.
- PAGE 45: REPLACE Q4590 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24 ALSO, CHANGED R9705 TO 10K 1% VALUE - APN 114S0315
- PAGE 52: DELETE J6955 REFERENCE AS THERE IS NO BIL CONNECTOR
***PAGES SYNCED FROM K24 SINCE LAST RELEASE 2.0.0*** - PAGE 52: REMOVED REFERENCES TO THE LED BACKLIGHT AS FREESCALE PART DOESN’T HAVE I2C BUS ACCESS 4/2/2009: RELEASE 9.2.0 (MAJOR):
- PAGE 54: REPLACING R5492 WITH APN 107S0139 PART FOR COST SAVING - PAGE 7: SCRUBBED TPS AS PER UPDATE FROM TOM
- PG 50: SWAPPED THE PART NUMBER AND THE ALTERNATE PART NUMBER FOR VR5020. MADE ISL60002 THE ALTERNATE PART - PAGE 59: REMOVING R5923 AND ONLY 1 PU ON SEL LINES IS ENOUGH - PAGE 49: FIXED PLACEMENT NOTE ASSOCIATED WITH C4907 (SHOULD BE: PLACE NEAR PIN E1)
- PAGE 70: REPLACING R7020 WITH APN 107S0138 PART FOR COST SAVING - PAGE 49:FIXED PLACEMENT NOTES ASSOCIATED WITH R4999,C4920(SHOULD BE:PLACE NEAR PIN M12)
***PAGES SYNCED FROM LENG OOI’S AUDIO_MLB SINCE LAST RELEASE 2.0.0*** - PAGE 70: REPLACING R7008 WITH APN 107S0139 PART FOR COST SAVING - PAGE 51: FIXED PLACEMENT NOTE ASSOCIATED WITH R5146 - PLACE NEAR U5110 INSTEAD OF SMC
- CHANGED SPEAKER AMPS TO LM48310, PLACEHOLDERS FOR LM48311. LM48311 IS THE CSP VERSION OF THE LM48310. - PAGE 70: R7080 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH SMBUS_SMC_B_S0_SCL/SDA
- CHANGED LDO TO B LP5900. - PAGE 73: R7350 PIN SWAP (MIRRORED HORIZONTALLY) AS PER LAYOUT ENGINEER - PAGE 97: RENAMED SINGLE PIN NET GND_LCDBKLT TO GND_LCDBKLT_PGND
- REMOVED OPTIONAL STUFFING RESISTORS AROUND THE RE-TASKING JACK ANALOG SWITCH. - PAGE 79: REPLACE Q7940 AND Q7948 WITH TPCP8102 APN 376S0778 PART, SIMILAR TO K24
- PAGE 90: REMOVED EMI CAPS [C9017-C9025] ON LED_RETURN, I2C AND LCD_BKLT POWER NETS
2/26/2009: RELEASE 4.0.0 (RFA RELEASE): - PAGE 90: UPDATED LVDS CONNECTOR PINOUT CONNECTIONS AS PER STEVE’S NEW SPREADSHEET
- PAGE 4: ADDED LDO_NO BOM OPTION - PAGE 97: ADDED DIDIT=TRUE ATTRIBUTE TO THE SWITCHING NODE PINS 3 & 4
- PAGE 8: RENAMED PP1V05_S0_MCP_PLL_UF BACK TO PP1V05_S0_MCP_PLL_UF_R - PAGE 97: CHANGED C9711 FROM 0.1UF TO 1.0UF 0603 TYPE CAP AS PER FREESCALE FEEDBACK
- PAGE 8: ADDED BACK - PP1V5_S0_MCP_PLL_VLDO, PP3V3_S0_MCP_PLL_VLDO - PAGE 97: CHANGED C9715 AND C9716 TO 50V CAPS FOR COST SAVING AND AS PER FREESCALE FEEDBACK
- PAGE 13: REPLACED XDP CONNECTOR WITH MINI XDP CONNECTOR APN 516S0625 - PAGE 97: CHANGED R9717 - R9722 FROM 0.1% TO 1% PARTS FOR COST SAVINGS AND AS PER FREESCALE FEEDBACK
- PAGE 34: ADDED NOTE WITH REGARD TO SMBUS CONNECTIONS TO THE AIRPORT CONNECTOR - PAGE 97: NO STUFF’ED C9721 - C9726 AS PER FREESCALE FEEDBACK
- PAGE 34: ADDED NOTE WITH REGARD TO 100 MS DELAY REQUIREMENT BETWEEN 3.3 WLAN - PAGE 97: FOR 25KHZ OPERATION, CHANGE R9726 TO NO STUFF, INTERCHANGE R9705(6.8K) WITH C9705
POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET AS IN K19I
- PAGE 54: REMOVED NOTE ON AMON AND BMON - PAGE 97: CHANGED R9710 TO 6.65K APN 114S0298 AND R9716 TO 226K APN 114S0445 PARTS AS PER
- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH APN 518S0738 FREESCALE FEEDBACK
- PAGE 77: ADDED BACK - 1.05 PLL LDO CIRCUIT - PAGE 107: ADDED CONSTRAINTS FOR FOLLOWING SENSOR NETS: ISNS_HDD_P/ISNS_HDD_N; ISNS_ODD_P/ISNS_ODD_N;
- PAGE 90: REFRESHED THE SYMBOL OF U9000, PART NUMBER CHANGED TO 353S2603 ISNS_AIRPORT_P/ISNS_AIRPORT_N; ISNS_1V5_S3_P/ISNS_1V5_S3_N;
A 3/4/2009: RELEASE 5.0.0 (RFA)-
- PAGE 34: ADDED A TEXT NOTE THAT J3401 (AIRPORT CONNECTOR) COULD CHANGE TO 1.8MM HEIGHT APN 516S0582
- PAGE 57: REPLACED KEYBOARD CONNECTOR WITH THAT OF K24 (APN 518S0637) - SYNC’ED FROM K24
ISNS_LCDBKLT_P/ ISNS_LCDBKLT_N
- PAGE 107: REMOVED FOLLOWING SENSOR NETS CONSTRAINTS: ISNS_P1V5S0MCP_P/ISNS_P1V5S0MCP_N;
ISNS_PVCORES0MCP_P/ISNS_PVCORES0MCP_N
- PAGE 74: ADDED XW7401-XW7404 SHORTS ACROSS L7400 AND L7401
- PAGE 69: REPLACED BATTERY CONNECTOR WITH THAT OF K24 (APN 518-0359) PAGE TITLE
- PAGE 69: DELETED NOTE REGARDING INDUCTOR FILTER REQUIREMENT ON BATT_POS_F (AS PER JOHN SCHEN)
- PAGE 70: CHANGED Q7050 TO 376S0761 AS PER DAYU & K24 DESIGN
- PAGE 70: CHANGED Q7000 AND Q7001 CHEAPER TO 376S0667 (HAT1128) AS PER DAYU’S RECOMMENDATION
***PAGES SYNCED FROM CASEY HARDY’S AUDIO_MLB SINCE LAST RELEASE 6.0.0***
-PG. 67, DELETED R6725 AND NET =PP3V42G3H_AUDIO
-PG. 66, ADDED R6613/14/15/16/17
Revision History
- PAGE 71: DISCONNECTING EN_PSV (PIN 34) FROM P5VLTS3_EN SIGNAL AND CONNECTING IT TO -PG. 66, ADDED C6612/13 DRAWING NUMBER SIZE
PP5VLT_S3_V5IN (5VRT PS) -PG. 66, ADDED R6631/2/3/4/5
- PAGE 72: L7220 CHANGED TO 152S0778 FOR COST SAVING AS PER DAYU
- PAGE 73: ADDED ONE MORE OSCON 39UF CAP ON INPUT SIDE
-PG. 66, ADDED C6634/5
-PG. 66, CHANGED C6610/11 TO 0.022UF Apple Inc. 051-7982 D
- PAGE 73: MOVED THE SENSE RESISTOR NEXT TO INDUCTOR -PG. 66, CHANGED C6630/31 TO 0.022UF REVISION
- PAGE 74: REMOVED UNUSED NETWORK ON U7400 PIN 5 AND PIN 6 AS PER DAYU [R7406, C7410, R7427, R7426] -PG. 65, DELETED R6521
- PAGE 74: STUFF R7413 AS PER DAYU
- PAGE 74: CHANGED Q7400 AND Q7402 TO 376S0772 AS PER DAYU
-PG. 65, ADDED R6523/4
-PG. 62, ADDED PLACEMENT COMMENT ATTR. TO XW6200/1
R
C.0.0
- PAGE 74: CHANGED Q7401 AND Q7403 TO 376S0771 AS PER DAYU -PG. 67, ADDED PLACEMENT COMMENT ATTR. TO XW6700/1/10/11 NOTICE OF PROPRIETARY PROPERTY: BRANCH
- PAGE 75: CHANGED R7525 TO 107S0132 FOR COST SAVING AS PER DAYU -PG. 68, ADDED PLACEMENT COMMENT ATTR. TO XW6851/80
- PAGE 78: DELETING P5VLTS3_EN RC CIRCUIT AS IT IS NO LONGER NEEDED (SEE ABOVE). ALSO UPDATED ASSOCIATED TEXT NOTE -PG. 66, REPLACED U6610/30 WITH LM48556 CKTS THE INFORMATION CONTAINED HEREIN IS THE
- PAGE 97: FIXED CONNECTION POINT (DOT) FOR LCDBKLT_VIN -PG. 67, DELETED C6760/1/2/3. PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
- PAGE 97: ADDED 0 OHMS SERIES RESISTOR ON LCD_BKLT_PWM FOR DEBUGGING PURPOSES -PG. 67, CHANGEED J6703 TO TWO PIN CONN. THE POSESSOR AGREES TO THE FOLLOWING: PAGE
- PAGE 97: RENAMED LCD_BKLT_PWM TO LVDS_IG_BKL_PWM -PG. 67, ADDED J6704
- PAGE 97: CHANGED VOVP VALUE TO 6.9V AS PER FREESCALE FEEDBACK
- PAGE 97: ADDED R9726 (22K) AND SWAPPED C9705 AND R9705 LOCATIONS FOR NOISE REDUCTION AS PER FREESCALE RECOMMENDATION
-PG. 62, REPLACED C6225 WITH APN: 128S0216 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
5 OF 109
- PAGE 97: DELETED C9712 AS IT IS REDUNDANT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
- PAGE 97: ADDED PLACEMENT NOTE ATTRIBUTE TO C9713 AND C9710 FOR PLACING THOSE NEAR L9710
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Revision History NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.
4/2/2009: RELEASE 9.3.0 (MAJOR):
- PAGE 4:B ADDED 5.95MM SANYO PART 128S0288 AS ALTERNATE TO 128S0271
- PAGE 4:B ADDED 5.95MM SANYO PART 128S0286 AS ALTERNATE TO 128S0248 05/08/2009: RELEASE 12.12.0 (MAJOR & WEEKLY ECO):
- PAGE 4: DELETED 152S0694 ALTERNATE ENTRY FOR 152S0138 AS IT IS NOT USED 08/31/2009: RELEASE 16.1.0 (MAJOR)-
- PAGE 50: REPLACED DUAL Q5032 FET WITH TWO SINGLE Q5032 & Q5033 (APN 376S0612) - PAGE 4: DELETED SANYO 6.00MM OSCON CAPS 128S0248 & 128S0271 FROM THE
N-CH FETS FOR ROUTING PURPOSES (SIL ANODE SIGNAL) ALTERNATE TABLE (MAKING ALTERNATES AS PRIMARY) - PAGE 4: REMOVED 138S0606 FROM THE ALTERNATES TABLE AS IT DOESN’T PERTAIN
- PAGE 54:B CHANGED R5412 TO 118OHM (114S0127) - PAGE 4: TURNING ON BOM OPTION MCPSMC_DIGITEMP_YES AS POR IS TO CONNECT TO K84
- PAGE 72: ADDED MIN_LINE/NECK_WIDTH ATTRIBUTES TO 5V_S3_DRVL, 3V3S5_VBST, MIKEY TO MCP79 SMBUS 0 INSTEAD OF SMBUS 1 AND TO CONNECT - PAGE 4: REPLACED CPU APN 337S3704 WITH 337S3769 IN MODULE PARTS TABLE AND
3V3S5_DRVL (FIXED THE NET NAME- ADDED UNDERSCORE) SMC B SMBUS TO MCP79 SMBUS 1 REMOVED 337S3704 FROM THE ALTERNATE PART TABLE AS POR IS 337S3769
- PAGE 75: CHANGED L7560 TO APN 152S0526 - 0.68UH, 3.5MOHM,16A - AS PER DAYU - PAGE 4: ADDED A TEXT NOTE STATING THAT ADC CAN ONLY WORK IN S0 STATE AS (P7550)
- PAGE 75: CHANGED R7569 TO 11.3K APN 114S0319 FOR SETTING THE CORRECT OCSET AS PER DAYU IT HAS I2C BUS PU TO S0 POWER RAIL - PAGE 4: REMOVE 870-1794, 870-1698 & 870-1820 FROM THE ALTERNATES TABLE AS
- PAGE 97: CHANGED MIN_NECK_WIDTH ASSOCIATED WITH PPVOUT_S0_LCDBKLT TO 0.24MM - PAGE 37: CHANGED C3714 AND C3715 TO 2.2UF APN 138S0642 TO FIX ETHERNET POR IS LOW NOISE POGO PINS
AS THAT’S THE PIN WIDTH JITTER ISSUE - PAGE 4: ADDED LOW NOISE POGO APNS 870-1885 (IN PLACE OF 870-1794),
- PAGE 97: CHANGED MIN_LINE/NECK_WIDTH ASSOCIATED WITH GND_LCDBKLT_SGND TO - PAGE 50: CHANGED R5030 TO 63.4 OHMS APN 114S0102 TO INCREASE THE SIL 870-1886 (IN PLACE OF 870-1698) & 870-1887 (IN PLACE OF
0.6/0.24MM CURRENT PER RDAR://PROBLEM/6752822 870-1820) IN MODULE PARTS TABLE
- PAGE 50: CHANGED R5714 TO 0 OHM APN 116S0004 PER - PAGE 4: ADDED NEW INTERSIL ISL6258A (WITH IMPROVED CHARGE CURRENT ACCURACY
***PAGES SYNCED FROM DAVID’S AUDIO_MLB SINCE LAST RELEASE 9.2.0*** RDAR://PROBLEM/6752822 LIMITS) APN 353S2811 AS AN ALTERNATE FOR APN 353S1832
- REMOVED R6725 AND =PP3V3_S3_AUDIO CONNECTION TO MAX14504 ANALOG SWITCH - PAGE 52: CHANGED R5200, R5201, R5260 & R5261 TO 2K APN 116S0073 - PAGE 4: REMOVED 998S APN FROM THE ALTERNATES TABLE PERTAINING TO I/O
- PAGE 72: REPLACED C7252, C7291 & C7292 WITH 5.95MM SANYO APN CONNECTORS AS THEY ARE NO LONGER POR FOR DVT
4/2/2009: RELEASE: 9.4.0 (MAJOR): 128S0288 - PAGE 4: REMOVED 514-0706, 514-0705 AND 514-0718 FROM THE ALTERNATES TABLE
- PAGE 97: ADDED A 1000PF CAP (C9727) ON LCDBKLT_VIN NEAR PIN 1 - PAGE 72: REPLACED C7240 & C7282 WITH 5.95MM SANYO APN AND ADDED TO MODULE PARTS TABLE AS THEY ARE NOW POR I/O CONNECTORS
- PAGE 97: REPLACED C9717 WITH 1000PF CAP APN 132S0147 AND ADDED PLACEMENT NOTE 128S0286 - PAGE 9: ADDED OMIT BOM OPTION ON ALL THE POGO PINS
D AS PER JOHN SCHEN - PAGE 73: REPLACED C7331 & C7345 WITH 5.95MM SANYO APN
128S0286
- PAGE 77: CHANGED C7771 TO 47UF APN 138S0659 TO FIX ETHERNET JITTER ISSUE
- PAGE 46: ADDED OMIT BOM OPTIONS TO J4600 & J4610 USB CONNECTORS
- PAGE 67: ADDED OMIT BOM OPTION TO J6700 AUDIO CONNECTOR
- PAGE 94: ADDED OMIT BOM OPTION TO J9400 MINI DP CONNECTOR
D
4/2/2009: RELEASE: 9.5.0 (MAJOR): - PAGE 97: UPDATED SCHEMATIC NOTE RELATED TO TARGET AND ACTUAL ISET & OVP
- PAGE 9: REPLACED Z0906,Z0907,Z0910 AND Z0911 MLB MOUNTING HOLES WITH 2.7 MM NUMBERS AS PER KIRAN’S EMAIL
DIAMETER PLATED HOLES - APN 998-1584 05/10/2009: RELEASE 12.13.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL):
- PAGE 60: CHANGED R6003 AND R6004 TO 10 OHMS 5% RESISTOR VALUES
RDAR://PROBLEM/6834630 09/16/2009: RELEASE 17.0.0 (FAB)-
4/3/2009: RELEASE: 9.6.0 (MAJOR):
- PAGE 4: UNDER K84_PROGPARTS BOM GROUP, REPLACED BLANK P/N WITH
PROGRAMMED P/N 05/11/2009: RELEASE 12.14.0 (MAJOR & WEEKLY ECO - THRU’ EMAIL): - FINAL DVT OK2FAB RELEASE
- PAGE 8: ADDED GLOBAL DIGITAL GROUND NET WITH MIN_LINE/NECK_WIDTH
AND VOLTAGE ATTRIBUTES - PAGE 57 : CHANGED R5714 TO 165 OHMS APN 114S0141 AS PER
- PAGE 9: REPLACED Z0905 AND Z0913 MLB MOUNTING HOLES WITH 2.7 MM RDAR://PROBLEM/6875543
DIAMETER PLATED HOLES - APN 998-1584 - PAGE 72 : CHANGED C7252, C7291 & C7292 BACK TO ORIGINAL APN 128S0271 09/21/2009: RELEASE A.0.0 (FAB)-
- PAGE 9: DELETED GND MIN_LINE/NECK_WIDTH AND VOLTAGE ATTRIBUTES
FROM FAN STANDOFF - FINAL PVT OK2FAB RELEASE
05/20/2009: AGILE RELEASE PROTO 2 OK2FAB 13.0.0 (FAB): - PAGE 4: ADDED APN 104S0033 (6.8 OHMS, 1/4W) RESISTORS IN MODULE PARTS
**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.5.0*** TABLE FOR R6612, R6617, R6630 & R6633
- REMOVED OPTIONAL STUFF-AROUND RESISTORS FOR ANALOG SWITCH - FINAL PROTO 2 OK2FAB RELEASE ADDED APN 518S0774 FOR XDP CONNECTOR J1300 (TO REPLACE 998-2515)
- CONNECT AUDIO JACK SHIELD TO DIGITAL GROUND. - UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS - PAGE 13: ADDED OMIT TO J1300
- PAGE 50: CHANGED R5030 SIL RESISTOR TO 80.6 OHMS APN 114S0112 AS PER ID
05/22/2009: AGILE RELEASE PROTO 2 OK2FAB 14.0.0 (FAB)- - PAGE 53: REPLACED APN 376S0545 WITH 376S0820 @ Q5315 - PER ECO#0000737172
4/3/2009: RELEASE: 10.0.0 (RFA): - PAGE 66: ADDED BOMOPTION OMIT TO RESISTORS R6612, R6617, R6630 & R6633
- PAGE 9: ADDED 7 EXTRA TALL POGO PINS FOR EMI - 4 STUFFED AT THE BOTTOM, ***RETRY***
3 UNSTUFFED ON THE TOP - FINAL PROTO 2 OK2FAB RELEASE
- PAGE 28: DELETED MAKE_BASE=TRUE ASSOCIATED WITH PCIE_RESET_L - UPDATED PAGE BORDERS TO NEW E4 DSIZE STANDARDS
- PAGE 52: FIXED DUPLICATION OF MAKE_BASE=TRUE ASSOCIATED WITH 10/12/2009: RELEASE B.0.0 (FAB)-
I2C_MIKEY_SCL/SDA_R
- PAGE 69: REFRESHED J6955 SYMBOL - APN 516S0787 06/09/2009: RELEASE 14.1.0 (MAJOR)- - PROD_DEBUG (POST FIRST 5K UNTIL 1 MONTH INTO PRODUCTION) OK2FAB RELEASE
- PAGE 78: DELETED MAKE_BASE=TRUE ASSOCIATED WITH ALL_SYS_PWRGD - PAGE 4: REMOVING CHGR_6259_NO BOM OPTION AS ISL 6259 IS NOT POR - PAGE 4: ADDED 1 NEW POR BOMS 639-0554, 639-0555 AND 1 NEW DEVELOPEMENT BOM
- PAGE 78: DELETED SYNONYMS AS THEY ARE NOT NEEDED ANYMORE - PAGE 4: ADDED NEW ISL PART APN 353S2718 AS AN ALTERNATE TO FIX B4 DONGLE 085-1076 FOR INITIAL RAMP
(DUE TO 0 OHMS) ISSUE - PAGE 4: UPDATED BOM GROUPS TABLE TO REFLECT AFOREMENTIONED CHANGES. NEW
- PAGE 9: REPLACED ALL MEDIUM POGO PINS WITH APN 870-1794 (2 MM) AND DEVELOPMENT BOM ONLY HAS XDP CONNECTOR AND LPCPLUS COMPONENTS
**PAGES SYNCED FROM LENG’S AUDIO_MLB SINCE LAST RELEASE 9.6.0*** ZS0916-ZS0918 WITH THINBC APN 870-1820 (2 MM) ONES - PAGE 4: ADDED 2 NEW EEES TO ATTACH WITH AFOREMENTIONED NEW 639 BOMS
- ADDED 100PF EMC CAP ON THREE SPEAKER CONNECTORS. - PAGE 59: ADDED R5922 10 OHMS SERIES R ON VDD SUPPLY TO FIX SMS NOISE - PAGE 4: DELETED 353S2811 ENTRY FROM THE ALTERNATES TABLE
- CHANGED MIN_WIDTH OF CODEC HP OUT NETS. ISSUE - PAGE 70: REPLACED U7000 WITH THE NEW INTERSIL SCREENED PARTS APN 353S2811
- PAGE 67: CHANGED J6704 TO A THREE PIN CONNECTOR 518S0520
- PAGE 69: REFRESHED J6955 SYMBOL (HALL EFFECT CONNECTOR)
- PAGE 70: REMOVED CHGR_6259_YES/NO BOM ATTRIBUTES AS ISL 6259 IS NOT POR
4/5/2009: RELEASE 10.1.0 (MAJOR): - PAGE 70: DELETED R7051 & R7053 CHGR_6259_YES BOM OPTIONS COMPONENTS 11/01/2009: RELEASE C.0.0 (FAB)-
- PAGE 70: REPLACING R7052 & R7054 CHGR_6259_NO BOM OPTION COMPONENTS - PROD (POST 1ST MONTH OF PRODUCTION) OK2FAB RELEASE
- PAGE 4: ADDED CHGR_6258 BOM OPTION UNDER MODULE PARTS TABLE WITH XW SHORTS- XW7052 & XW7054 - PAGE 2: UPDATED SYSTEM BLOCK DIAGRAM
AND TO K84 MISC BOM GROUP. THIS IS TO STUFF ISL6258 PART - PAGE 70: REMOVED R7050 CHGR_6259_YES COMPONENT AS IT IS NOT NEEDED - PAGE 3: UPDATED POWER SYSTEM BLOCK DIAGRAM
- PAGE 9: ADDED ONE MORE TALL POGO PIN ON BOTTOM SIDE WITH ISL 6258 (PM_SLP_S3_L DIRECTLY CONNECTS TO ISL 6258 PIN) - PAGE 4: UPDATED BOM TABLES TO NOT INCLUDE ANY 085 DEVELOPMENT BOMS. AND,
- PAGE 13: FIXED THE NOTE ON THE XDP PAGE- REPLACING 920-0620 ADAPTER - PAGE 94: STUFFED C9485 AND CHANGED IT TO 22UF (APN 138S0654),CHANGED K84_DEBUG_PROD BOM GROUP IS TURNED ON
BOARD WITH 920-0782 ADAPTER FLEX C9400 & C9481 TO 4.7UF (APN 138S0618) & CHANGED C9480 TO 22UF
- PAGE 34: RENAMED P5VWLAN_SS NET TO P3V3WLAN_SS (APN 138S0654): TO FIX B4 DONGLE ISSUE
- PAGE 46: DELETED TEXT NOTE RELATED TO R4691 & R4690 AS IT IS NA TO K84
- PAGE 52: MOVED THE R5251 CONNECTION TO SENSOR ADC TO THE RIGHT SIDE ***PAGES SYNCED FROM CASEY HARDY?S AUDIO_MLB SINCE LAST RELEASE 14.0.0***
TO SHOW A SEPARATE CONNECTION FOR CLARITY - ADDED R6862 PULL-UP RESISTOR TO PERPH. DETECT CKT.
- PAGE 52: DELETED TEXT NOTE ON BATTERY LED DRIVER AS IT IS NA TO K84
- PAGE 69: PUT R6961 BEFORE C6955 TO GET RC FILTER. ALSO, FOR NOW,
C REPLACED R6961 WITH A 0 OHM RESISTOR AND NOSTUFF’ED C6955
- PAGE 70: ADDED OMIT BOM OPTION TO U7000 AS THIS PART WILL GET STUFFED
WITH EITHER ISL6258 OR ISL6259 DEPENDING UPON PAGE 4 BOM TABLE
06/10/2009: RELEASE 14.2.0 (MAJOR)-
- PAGE 4: ADDED APN 138S0661 LOW NOISE MURATA CAPS AS ALTERNATE FOR
C
- PAGE 70: FIXED Q7001 DRAIN-SOURCE ORIENTATION C9715 & C9716 TO FIX LCD BKLT AUDIBLE NOISE ISSUE
- PAGE 49: ADDED 0.1UF CAPS ON SMS_X_AXIS, SMS_Y_AXIS & SMS_Z_AXIS
NETS TO FIX NOISE ISSUE
4/6/2009 - RELEASE 10.1.1 (MINOR): - PAGE 77: CHANGED R7780 TO 25.5K APN 114S0354 & R7781 TO 80.6K APN
114S0402 AS PER DAYU
**SCHEMATIC AND BOM CLEAN-UP**
- PAGE 4: DELETED CHGR_6258 AND RENAMED 6259_NO TO
CHGR_6259_NO. REPLACED CHGR_6258 WITH CHGR_6259_NO 06/11/2009: RELEASE 14.3.0 (MAJOR)-
IN MODULE PARTS TABLE - PAGE 77: ADDED 0 OHMS BOM OPTIONS R7782 BETWEEN PIN 4 OF U7750
- PAGE 4: DELETED ENTRIES IN THE ALTERNATE BOM TABLE FOR THE FOLLOWING APN: (SKIP PIN) AND POWER RAIL AND R7783 BETWEEN PIN 4 AND GND.
516-0213 AND 516S0709 R7782 WILL BE NOSTUFF FOR NOW. THIS IS AS PER DAYU TO FIX
- PAGE 8: DELETED =PP3V3_S3_AUDIO ALIAS AS IT IS NO LONGER APPLICABLE ETHERNET JITTER ISSUE
- PAGE 57: DELETED NO_TEST = TRUE ATTRIBUTE FROM Z2_SCLK AND
Z2_MOSI AS THEY CONFLICT WITH FUNC_TEST ATTRIBUTE ON PAGE 7
- PAGE 69: RENAMED 6259_NO/YES TO CHGR_6259_NO/YES 06/11/2009: RELEASE 14.4.0 (MAJOR)-
- PAGE 49: REPLACED C4950-C4952 WITH 1UF APN 138S0640 CAPS
- PAGE 78: DISCONNECTED P1V05_S5_PGOOD FROM PIN 3 OF U7840 AND
4/6/2009 - RELEASE 11.0.0 (OK2FAB): CONNECTED IT TO PIN 1 (RSMRST_PWRGD) TO FIX LEAKAGE ISSUE
- NO CHANGE SINCE LAST MINOR RELEASE 10.1.1
06/12/2009: RELEASE 14.5.0 (MAJOR)-
- PAGE 9: ADDED ONE MORE EXTRA TALL POGO PIN AS PER EMC RECOMMENDATION
: ZS0920
4/7/2009 - RELEASE 12.0.0 OK2FAB (RFA): - PAGE 78: ADDED 0 OHM BOM OPTION R7895 BETWEEN 1V05_S5_PGOOD
- NO CHANGE SINCE LAST RFA RELEASE 11.0.0. AND RSMRST_PWRGD FOR DEBUG PURPOSES
***THIS IS A RESUBMIT AS PREVIOUS RFA DIDNT GO THROUGH***
06/22/2009: RELEASE 14.6.0 (MAJOR)-
4/23/2009 - RELEASE 12.1.0 (MAJOR): - PAGE 4: ADDED CPU APN 337S3769 AS ALTERNATE TO 337S3704
- PAGE 4: ADDED METAL PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO - PAGE 9: ADDED NOSTUFF BOM OPTION TO ZS0920
ADDED CORRESPONDING NOTES- - PAGE 50: CHANGED R5030 TO 48.7 OHMS APN 114S0091 (SIL CURRENT TO 12MA)
514-0691 ALTERNATE FOR 514-0690; - PAGE 57: CHANGED R5714 TO 113 OHMS APN 114S0125 (KB LED CURRENT TO 8.5MA)
514-0689 ALTERNATE FOR 514-0688 - PAGE 97: ADDED CRITICAL ATTRIBUTE TO C9715 & C9716
- PAGE 13: REPLACED J1300 XDP CONNECTOR WITH MORE ROBUST CONNECTOR - PAGE 97: CHANGED R9710 TO 7.68K APN 114S0304 (LCD BKLT CURRENT TO 20MA)
APN 998-2515
- PAGE 39: REPLACED J3900 ETHERNET CONNECTOR WITH POR PLASTIC CONNECTOR
APN 514-0692 06/25/2009: RELEASE 14.7.0 (MAJOR)-
- PAGE 46: REPLACED J4600 & J4610 USB CONNECTORS WITH POR PLASTIC CONNECTOR
APN 514-0688 - PAGE 70: DELETED OMIT BOM OPTION FROM U7000 AS ISL6259 HAVE BEEN
- PAGE 75: CHANGE Q7560 AND Q7565 TO SIS426 APN 376S0749 PER REMOVED
RDAR://6812904
- PAGE 75: CHANGE R7565 TO 1OHM APN 113S0023 PER RDAR://6812904
- PAGE 76: CHANGED THE CPU VTT OVER CURRENT TRIP POINT PER RDAR://6792329 BY 07/17/2009: AGILE EVT OK2FAB RELEASE 15.0.0 (FAB)-
CHANGING R7604 FROM 8.87KN) TO 6.04KN)
- PAGE 94: REPLACED J9400 DP CONNECTOR WITH POR PLASTIC CONNECTOR - NO CHANGES SINCE LAST MAJOR 14.7.0. THIS IS FINAL EVT FAB RELEASE
APN 514-0690
- PAGE 75: CHANGED C7565 AND C7568 TO CASE_B4_SM PACKAGE FROM
CASE_B2_SM DUE TO PACKAGING ERROR (SAME APN)
07/21/2009: RELEASE 15.1.0 (MAJOR)-
B 4/24/2009 - RELEASE 12.2.0 (MAJOR): - PAGE 4: DELETED MIKEY_LOAD_DET BOM OPTION FROM THE TABLE UNDER K84_MISC
CATEGORY AS PER CASEY
B
**PAGES SYNCED FROM CASEY’S AUDIO_MLB SINCE LAST RELEASE 12.1.0*** - PAGE 4: UPDATED ALTERNATES FOR MINI DP AND USB CONNECTORS WITH PG2
- REPLACED J6700 WITH APN: 514-0694 PLASTIC CONNECTORS- APN 514-0706 (MDP) & 514-0705 (USB). AND,
- ADDED DZ 6702 AND L6706 UPDATED NOTE BELOW THE ALTERNATES PARTS TABLE ACCORDINGLY
- CONNECTED R6860 TO AUD_IP_PERPH_DET - PAGE 4: ADDED PG2 CONNECTOR APN 514-0704 IN THE MODULE PARTS TABLE FOR
RJ45 J3900 CONNECTOR
- PAGE 4: DELETED 353S2310 PART FROM THE ALTERNATES BOM TABLE AS ALL
4/27/2009 - RELEASE 12.3.0 (MAJOR & WEEKLY ECO): PRODUCTION HAS NOW MOVED TO ITS ALTERNATE PART 353S2718
- PAGE 4: ADDED NEW BOM ENTRY 639-0254 FOR MOLEX DDR3 CONNECTOR CONFIG. ALSO, - PAGE 4: ADDED NEW INTERSIL PART APN 353S2718 IN THE MODULE PARTS TABLE
EDITED 639-0035 BOM NAME TO REFLECT FOXCONN DDR3 CONNECTOR. FOR U7870 TO FIX B4 DONGLE ISSUE
ADDED TWO ENTRIES (J3200 AND J3100) FOR FOXCONN AND TWO FOR MOLEX - PAGE 21: DELETED NOSTUFF BOM ATTRIBUTE FROM R2143 AS MIKEY_LOAD_DET
UNDER MODULE PARTS TABLE . CIRCUIT HAS BEEN REMOVED. SO R2143 NEEDS TO BE STUFFED NOW
- PAGE 74: CHANGED C7432 TO 0.001UF AS PER RDAR://6792327 - PAGE 39: ADDED BOMOPTION ATTRIBUTE OMIT TO J3900 AS NEW PG2 CONNECTOR
- PAGE 74: UNSTUFFED C7434 AS PER RDAR://6792327 PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE
- PAGE 74: CHANGED C7428 TO 0.47UF AS PER RDAR://6792327 - PAGE 78: ADDED BOMOPTION ATTRIBUTE OMIT TO U7870 AS NEW INTERSIL PART
- PAGE 74: CHANGED R7415 TO 10.5K AS PER RDAR://6792327 PART HAS BEEN ADDED ON PAGE 4 MODULE PARTS TABLE
- PAGE 97: CHANGED R9716 FROM 226K TO 243K TO CHANGE THE OVP POINT TO 35.3V
AS PER KIRAN
07/27/2009: RELEASE 15.2.0 (MAJOR)-
- PAGE 4: DELETED LOW NOISE MURRATA CAP ENTRY FROM THE ALTERNATES TABLE
- PAGE 49: CHANGED SMS NOISE FILTERING CAPS C4950-C4952 TO 0.47UF APN
4/28/2009: RELEASE 12.4.0 (MAJOR): 132S0178 TO FIX THE SMART TEST FAILURE
- PAGE 70: DISCONNECTED PM_SLP_S3_L FROM PIN 4 (VREF) AS IT WAS INCORRECTLY
- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER CONNECTED, THEREBY CAUSING HIGHER SLEEP/SHUTDOWN POWER
FOR EMI PURPOSES - L6707 & L6708 - PAGE 97: NOSTUFFED C9716 AND CHANGED C9715 TO APN 138S0661 AS POR IS TO
HAVE SINGLE CAP LOW NOISE MURRATA CAP SOLUTION AS PER ACOUSTICS
ENGINEER
4/28/2009: RELEASE 12.5.0 (MAJOR):
- PAGE 67: MOVED L6707 & L6708 TO J6703 (FULL RANGE SPEAKER CONNECTOR)
BETWEEN CAPS AND CONNECTOR 08/05/2009: RELEASE 15.3.0 (MAJOR)-
- PAGE 4: ADDED APN 138S0606 (TAIYO-YUDEN) AS AN ALTERNATE FOR APN 138S0602
- PAGE 4: ADDED PDNI PLATED AUDIO CONNECTOR W/ CHAMFER APN 514-0718 AS AN
4/29/2009: RELEASE 12.6.0 (MAJOR & WEEKLY ECO): ALTERNATE FOR J6700 APN 514-0694
- PAGE 4: ADDED GOLD PLATED AUDIO CONNECTOR W/O CHAMFER APN 998-2622 AS AN
- PAGE 67: ADDED 0603 FERRITE PLACEHOLDERS APN 155S0367 ON RIGHT PIEZO SPEAKER ALTERNATE FOR J6700 APN 514-0694
J6704 FOR EMI PURPOSES - L6709 & L6710 - PAGE 4: ADDED GOLD PLATED RJ45 CONNECTOR APN 998-2621 AS AN ALTERNATE FOR
- PAGE 97: CHANGED L9710 TO A BIGGER 2525 PACKAGE (LOW DCR) APN 152S0585 FOR J3900 APN 514-0704
BETTER EFFICIENCY - PAGE 4: ADDED GOLD PLATED MINI DP CONNECTOR APN 998-2626 AS AN ALTERNATE
FOR J9400 APN 514-0691
- PAGE 4: ADDED GOLD PLATED USB CONNECTOR APN 998-2624 AS AN ALTERNATE FOR
4/29/2009: RELEASE 12.7.0 (MAJOR & WEEKLY ECO): J4600/J4610 APN 514-0689
- PAGE 97: CHANGED L9710 BACK TO THE ORIGINAL APN 152S0826 AS 2525 PACKAGE CAN’T FIT IN - PAGE 4: ADDED LOW NOISE POGO PINS 870-1885 (MEDIUM), 870-1886 (TALL), AND
870-1887 (THIN) AS ALTERNATES
- PAGE 49: CHANGED C4950, C4951, C4952 TO APN:132S0131 (CAP,0402,0.033UF,
5/01/2009: RELEASE 12.8.0 (MAJOR): 16V,10%) AS THESE WOULD BE USED TO ACHIEVE CUT-OFF FREQUENCY OF
- PAGE 4: ADDED A36 EEE NUMBER FOR NEW BOM CONFIGURATION 639-0254 ~146HZ FOR SMS (AS PER THE VENDOR) AND FILTER THE NOISE TOO AS
- PAGE 60: ADDED 0 OHMS SERIES RESISTORS R6003 AND R6004 ON AVDD AND DVDD SEEN BY SMC CHIP. CAPS ON SMS PAGE WOULD BE UNSTUFFED
SUPPLY RAILS TO ADC CHIP - PAGE 59: ADDED NOSTUFF BOM OPTION ATTRIBUTE TO C5923-C5925 AS STATED
- PAGE 60: CHANGED R6001 & R6002 TO 33 OHMS RESISTORS TO FIX UNDERSHOOT ON ABOVE. ALSO, EDITED THE NOTE ACCORDINGLY
A I2C BUS
05/01/2009: RELEASE 12.9.0 (MAJOR):

- PAGE 70: CHANGED R7031 FROM 10 OHM TO 2.2 OHM, 5%, APN:116S0010 TO FIX
SLOW CHARGING ISSUE, PER DAYU
- PAGE 70: CHANGED R7047 FROM 10 OHM TO 0 OHM, 5%, APN:116S0004 TO FIX SLOW
CHARGING ISSUE, PER DAYU
- PAGE 70: CHANGED C7043 FROM 0.1UF TO 1UF, 10%, APN:138S0640 TO FIX SLOW PAGE TITLE
- PAGE 4: UPDATED PLASTIC PART ALTERNATES FOR USB AND MINI DP CONNECTORS. ALSO
ADDED CORRESPONDING NOTES-
514-0690 PLASTIC ALTERNATE FOR 514-0691 METAL;
CHARGING ISSUE, PER DAYU
Revision History
514-0688 PLASTIC ALTERNATE FOR 514-0689 METAL 08/27/2009: AGILE PDFC OK2FAB RELEASE 16.0.0 (FAB)- DRAWING NUMBER SIZE
- PAGE 46: REPLACED PLASTIC USB CONNECTORS WITH METAL APN 514-0689 PARTS
- PAGE 94: REPLACED PLASTIC MINI DP CONNECTOR WITH METAL APN 514-0691 PART
- FINAL PDFC (PRE DVT) RELEASE!
- PAGE 97: REFRESHED THE SYMBOL OF C9715 4.7UF APN 138S0661 Apple Inc. 051-7982 D
REVISION
05/04/2009: RELEASE 12.10.0 (MAJOR):
- PAGE 4: REMOVED SHORT POGO PIN ALTERNATE
R
C.0.0
- PAGE 4: REVERTING MCP TO EARLIER USE APN 338S0710 NOTICE OF PROPRIETARY PROPERTY: BRANCH
- PAGE 60: CHANGED U6050 INA 211 PART TO 200X GAIN INA 210 APN 353S2073
THE INFORMATION CONTAINED HEREIN IS THE
05/05/2009: RELEASE 12.11.0 (MAJOR & WEEKLY ECO): THE POSESSOR AGREES TO THE FOLLOWING: PAGE
- PAGE 4: ADDED 4 QUANTITIES OF DIMM CONNECTOR SCREWS APN 452-1708
- PAGE 46: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS
THOUGH POR IS PLASTIC USB CONNECTOR PART
6 OF 109
- PAGE 94: ADDED NOTE ABOUT USING METAL PART’S SCHEMATIC AND CAD SYMBOLS III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
THOUGH POR IS PLASTIC MINI DP CONNECTOR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Functional Test Points
POWER NETS FUNC_TEST

FAN CONNECTORS FUNC_TEST X16 WIRELESS CONN FUNC_TEST
TRUE PP5VRT_S0 TRUE PP3V3_S3_BT_F 30

7 8 I303
TRUE PPVCORE_S0_CPU
D
I12
I15 TRUE FAN_RT_PWM 43 I301 TRUE

TRUE
CONN_PCIE_MINI_D2R_P
CONN_PCIE_MINI_D2R_N
30 72
I287
I285 TRUE PPVCORE_S0_MCP

8
8
D
I16 TRUE FAN_RT_TACH 43 I302 30 72
TRUE PP0V75_S0 8
(NEED TO ADD 1 GND TP) TRUE CONN_PCIE_MINI_R2D_P 30 72
I284
I300
TRUE PP1V05_S0 8
TRUE CONN_PCIE_MINI_R2D_N 30 72
I280
I299
TRUE PP1V5_S0 8
MIC FUNC_TEST TRUE PCIE_CLK100M_MINI_CONN_P 30 72
I281
I298
TRUE PP1V8_S0 8
TRUE PCIE_CLK100M_MINI_CONN_N 30 72
I282
TRUE BI_MIC_LO
I293
TRUE PP5VLT_S0 8
I238 53 54
TRUE PP3V3_WLAN 7 30
I376
TRUE BI_MIC_HI
I288 (NEED 2 TP) TRUE PP5VRT_S0 7 8
I237 53 54 TRUE PCIE_WAKE_L 17 30
I396
TRUE BI_MIC_SHIELD
I292
TRUE PP3V3_S0 8
I239 53 54
TRUE CONN_USB2_BT_P 30 73
I283
I295
TRUE PP1V5_S3 8
TRUE CONN_USB2_BT_N 30 73
I279
SPEAKER FUNC_TEST
I290
TRUE PP3V3_S3 7 8
TRUE MINI_CLKREQ_Q_L 30
I278
I271
TRUE PP5V_S3 8
TRUE SPKRAMP_L_N_OUT TRUE MINI_RESET_CONN_L 30
I270
I227 52 53 I289
(NEED TO ADD 2 GND TP) I379 TRUE PP1V1R1V05_S5 8
TRUE SPKRAMP_L_P_OUT 52 53 PP3V3_S5
I226
I273 TRUE 8
I228 TRUE SPKRAMP_R_N_OUT 52 53
TRUE PP3V42_G3H 7 8
I274
TRUE SPKRAMP_R_P_OUT 52 53 PPBUS_G3H
I230
I275 TRUE 8
I229 TRUE SPKRAMP_SUB_N_OUT 52 53
TRUE PP3V3_ENET_PHY 8
I276
I231 TRUE SPKRAMP_SUB_P_OUT 52 53

TRUE PP1V2R1V05_ENET 8
I272
I393
TRUE PP3V3_G3_RTC 21 22 25
IPD_FLEX_CONN FUNC_TEST I392 TRUE PP3V3_WLAN 7 30
TRUE PP5V_SW_ODD 7 34 47
TRUE PP3V3_S3_LDO 7 45
I391
I375
TRUE PP5V_S0_HDD_FLT 7 34
TRUE PP18V5_S3 7 45
I390
I374
TRUE PP3V3_S5_AVREF_SMC 36 37
TRUE Z2_CS_L 44 45
I389
LVDS FUNC_TEST
I372
TRUE PP18V5_S3 7 45
TRUE Z2_DEBUG3 44 45
I388
I370
TRUE PP3V3_S3_LDO 7 45
TRUE PP3V3_LCDVDD_SW_F (NEED 2 TP) TRUE Z2_MOSI 44 45
I387
I259 7 65 I371
TRUE PP3V3_LCDVDD_SW_F 7 65
TRUE PP3V3_S0_LCD_F TRUE Z2_MISO 44 45
I386
I258 65 I369
TRUE PPVOUT_S0_LCDBKLT 7 47 65 68
TRUE PPVOUT_S0_LCDBKLT TRUE Z2_SCLK I385
C I260
I245 TRUE LVDS_IG_DDC_CLK

7 47 65 68
18 65
(NEED 2 TP) I368
I361 TRUE Z2_BOOST_EN

44 45
45
I383 TRUE
TRUE
PP4V5_AUDIO_ANALOG
SMC_PM_G2_EN
49
36 57 63
C
TRUE LVDS_IG_DDC_DATA TRUE Z2_HOST_INTN 44 45
I382
I262 18 65 I366
TRUE PM_SLP_S4_L 21 36 37 63
TRUE LVDS_IG_A_DATA_N<0> TRUE Z2_CLKIN 44 45
I381
I261 18 65 72 I365
TRUE PM_SLP_S3_L 21 32 36 63 67
TRUE LVDS_IG_A_DATA_P<0> 18 65 72 I363 TRUE Z2_KEY_ACT_L 44 45
I380
PP5V_S3_CAMERA_F
I256
Z2_RESET I397 TRUE 7 65
I257 TRUE LVDS_IG_A_DATA_N<1> 18 65 72 I364 TRUE 44 45
TRUE LVDS_IG_A_DATA_P<1> 18 65 72 I362 TRUE PSOC_MISO 44 45

(NEED TO ADD 1 GND TP)
I255
TRUE LVDS_IG_A_DATA_N<2> 18 65 72 I360 TRUE PSOC_MOSI 44 45

I252
TRUE LVDS_IG_A_DATA_P<2> 18 65 72 I359 TRUE PSOC_SCLK 44 45

I253
TRUE LVDS_IG_A_CLK_F_N 65 72 I357 TRUE SMBUS_SMC_A_S3_SDA 39 75

I254
TRUE LVDS_IG_A_CLK_F_P 65 72 I358 TRUE SMBUS_SMC_A_S3_SCL 39 75

I250
TRUE LED_RETURN_1 65 68 I377

TRUE PSOC_F_CS_L 44 45
I251
PICKB_L DC POWER CONN FUNC_TEST
I313 TRUE LED_RETURN_2 65 68 I378 TRUE 44 45
TRUE LED_RETURN_3 65 68
I312 TRUE PP18V5_DCIN_FUSE (NEED 2 TP) 55
I246
TRUE LED_RETURN_4 65 68 I304 TRUE ADAPTER_SENSE 55

I247
I248 TRUE LED_RETURN_5 65 68
KEYBOARD CONN FUNC_TEST
I249 TRUE LED_RETURN_6 65 68
I395 TRUE PP5V_S3_CAMERA_F 7 65

TRUE PP3V3_S3 7 8
I354
I297 TRUE USB_CAMERA_CONN_P 65 73 I355 TRUE PP3V42_G3H 7 8
I294 TRUE USB_CAMERA_CONN_N 65 73 I344 TRUE WS_KBD1 44
(NEED TO ADD 5 GND TP) I345 TRUE WS_KBD2 44
I346 TRUE WS_KBD3 44
SATA ODD CONN FUNC_TEST I349 TRUE WS_KBD5 44
(NEED 2 TP) TRUE WS_KBD6 44

TRUE PP5V_SW_ODD 7 34 47
I348
I264
TRUE WS_KBD7 44
TRUE SMC_ODD_DETECT 34 36
I350
I268
TRUE WS_KBD8
B I269 TRUE
TRUE
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
34 72
34 72
I352
I351 TRUE WS_KBD9

44
44
B
I267
TRUE WS_KBD10 44
TRUE SATA_ODD_R2D_P 34 72
I353
I265
TRUE WS_KBD11 44
TRUE SATA_ODD_R2D_N 34 72
I327
I266
(NEED TO ADD 2 GND TP) I328 TRUE WS_KBD12 44

SATA HDD/SIL FUNC_TEST WS_KBD15_CAP
I342 TRUE 44
(NEED 2 TP) TRUE WS_KBD16_NUM 44
TRUE PP5V_S0_HDD_FLT 7 34
I341
I319
TRUE WS_KBD17 44
TRUE SATA_HDD_R2D_P 34 72
I339
I314
TRUE WS_KBD18 44
TRUE SATA_HDD_R2D_N 34 72
I340
I315
TRUE WS_KBD19 44
TRUE SATA_HDD_D2R_C_P 34 72
I338
I318
TRUE WS_KBD20 44
TRUE SATA_HDD_D2R_C_N 34 72
I336
I317
TRUE WS_KBD21 44
TRUE SYS_LED_ANODE_R 34
I337
I307
(NEED TO ADD 3 GND TP) TRUE WS_KBD23 44
I335
I334 TRUE WS_KBD_ONOFF_L 44
I332 TRUE WS_LEFT_SHIFT_KBD 44
I330 TRUE WS_LEFT_OPTION_KBD 44
I331 TRUE WS_CONTROL_KBD 44

BATT POWER CONN FUNC_TEST

I322 TRUE SMBUS_SMC_BSA_SCL 39 75
I321 TRUE SMBUS_SMC_BSA_SDA 39 75
I320 TRUE SYS_DETECT_L 55
A I305 TRUE BATT_POS_F

55 56
(NEED 2 TP) SYNC_MASTER=K24_MLB SYNC_DATE=02/04/2009 A
PAGE TITLE
FUNC TEST
HALL EFFECT CONNECTOR FUNC_TEST DRAWING NUMBER SIZE

I326 TRUE PP3V42_G3H 7 8
REVISION
I308 TRUE SMC_LID_R 55
R
C.0.0
7 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"S0,S0M" RAILS "S3" RAILS "G3H" RAILS

58 =PP1V5_S3_REG PP1V5_S3 =PP3V42_G3H_REG PP3V42_G3H
7 55 7
64 =PP5VRT_S0_FET PP5VRT_S0 7 MIN_LINE_WIDTH=1.5 mm MIN_LINE_WIDTH=0.6 MM
59 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 7 MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=1.5V VOLTAGE=3.42V
(CPU VCORE PWR) MIN_NECK_WIDTH=0.3 MM VOLTAGE=5V MAKE_BASE=TRUE MAKE_BASE=TRUE
VOLTAGE=1.25V MAKE_BASE=TRUE
MAKE_BASE=TRUE =PP1V5_S3_P1V5S0FET 64 =PPVIN_S5_SMCVREF 37
=PP5V_S0_CPUVTTS0 61
=PPVCORE_S0_CPU 11 12 =PP1V5_S3_MEM_A 27 =PP3V42_G3H_SMBUS_SMC_BSA 39
=PP5V_S0_LPCPLUS 38
=PPVCORE_S0_CPU_VSENSE 40 =PP1V5_S3_MEM_B 28 =PP3V42_G3H_PWRCTL 63
D
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP
43
59
=PP1V5_S3_MEMRESET 29 =PP3V42_G3H_CHGR 56 D
=PP3V42_G3H_SMCUSBMUX 35
64 =PP5VLT_S0_FET PP5VLT_S0 7 64 =PP3V3_S3_FET PP3V3_S3 7 =PP3V42_G3H_TPAD 44

61 =PPCPUVTT_S0_REG PP1V05_S0 7 MIN_LINE_WIDTH=0.30 MM MIN_LINE_WIDTH=0.5 mm
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.25 mm =PP3V3_S5_SMC 36 37
MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V VOLTAGE=3.3V
VOLTAGE=1.05V MAKE_BASE=TRUE MAKE_BASE=TRUE =PP3V3_S5_LPCPLUS 38
MAKE_BASE=TRUE
=PP5V_S0_DP_AUX_MUX 66 =PP3V3_S3_SMBUS_SMC_A_S3 39 =PP3V42_G3H_RTC_D 25
=PP1V05_S0_CPU 10 11 12 13
=PP5V_S0_HDD 34 =PP3V3_S3_PDCISENS 58 =PP3V42_G3H_ONEWIRE 55
=PP1V05_S0_MCP_FSB 14 22 23
=PP5V_S0_MCPREG 60 =PP3V3_S3_SMBUS_SMC_MGMT 39 =PP3V42_G3H_HALL 55
=PP5V_S0_VMON 63 =PP3V3_S3_VREFMRGN 26
=PP1V05_S0_MCP_PEX_DVDD 8 23
=PP3V3_S3_WLAN 30
=PP1V05_S0_MCP_AVDD_UF 23
=PP3V3_S3_MCP_GPIO 21
=PP1V05_S0_MCP_SATA_DVDD 8 23
64 =PP3V3_S0_FET PP3V3_S0 7 =PP3V3_S3_TPAD 44
=PP1V05_S0_MCP_HDMI_VDD 18 24 MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM =PP3V3_S3_SMS 46
=PP1V05_S0_VMON 63 VOLTAGE=3.3V 55 =PP18V5_DCIN_CONN PP18V5_G3H
MAKE_BASE=TRUE =PP3V3_S3_BT 30 MIN_LINE_WIDTH=0.6 MM
=PP1V05_S0_MCP_PLL_UF_R 62 MIN_NECK_WIDTH=0.3 MM
=PP3V3_S0_XDP 13 VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP3V3_S0_MCP 21 22 23
=PP18V5_G3H_CHGR 56
=PP3V3_S0_MCP_DAC_UF 24
57 =PP5V_S3_REG PP5V_S3 7
=PP3V3_S0_MCP_VPLL_UF 24 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
=PP3V3_S0_ODD 34 VOLTAGE=5V
MAKE_BASE=TRUE 56 =PPBUS_G3H PPBUS_G3H 7
=PP3V3_S0_SMBUS_SMC_0_S0 39 MIN_LINE_WIDTH=0.4 mm
=PP5V_S3_EXTUSB 35 MIN_NECK_WIDTH=0.25 mm
=PP3V3_S0_SMBUS_SMC_B_S0 39 VOLTAGE=12.6V
60 =PPMCPCORE_S0_REG PPVCORE_S0_MCP 7 MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM =PP3V3_S0_SMBUS_MCP_0 39
MIN_NECK_WIDTH=0.2 MM =PP5V_S3_CAMERA 65
(MCP VCORE AFTER SENSE RES) VOLTAGE=1.05V =PP3V3_S0_FAN_RT 43
MAKE_BASE=TRUE =PP5V_S3_AUDIO_AMP 52 =PPVIN_S0_MCPCORE 60
=PP3V3_S0_AUDIO 49 53 54
=PPVCORE_S0_MCP 22 23 =PP5V_S3_MCPDDRFET 64 =PPVIN_S5_1V5S30V75S0 58
=PP3V3_S0_IMVP 59
=PP5V_S3_1V5S30V75S0 58 =PPCPUVCORE_VTT_ISNS_R 41
=PPVCORE_S0_MCP_VSENSE 40 =PP3V3_S0_LCD 65 (BEFORE HIGH SIDE SENSING RES.)
=PP5V_S3_AUDIO 49 51 53
C =PP3V3_S0_MCP_GPIO
=PP3V3_S0_MCP_PLL_UF
18 19 21
23
=PP5V_S3_P5VLTS0FET
=PP5V_S3_VTTCLAMP
64
64 =PPBUS_S0_LCDBKLT 69
C
58 =PP0V75_S0_REG PP0V75_S0 7 =PP3V3R1V5_S0_MCP_HDA 21 23
MIN_LINE_WIDTH=0.4 mm =PP5V_S3_DEBUG_ISNS 47 =PPVIN_S5_3V3S5 57
MIN_NECK_WIDTH=0.2 mm =PP3V3_S0_SMC 37
VOLTAGE=0.75V =PP5V_S3_SYSLED 37 =PPVIN_S3_5VS3 57
MAKE_BASE=TRUE =PP3V3_S0_MCPTHMSNS 42
=PP5V_S3_TPAD 45 =PPBUS_G3HRS5 40
=PPVTT_S0_VTTCLAMP 64 =PP3V3_S0_CPUTHMSNS 42
=PP5V_S3_ODD 34
=PP0V75_S0_MEM_VTT_A 27 =PP3V3_S0_DPCONN 67
=PP5V_S3_DEBUG_ADC_AVDD 47
=PP0V75_S0_MEM_VTT_B 28 =PPSPD_S0_MEM_A 27
=PP5V_S3_DEBUG_ADC_DVDD 47
=PPSPD_S0_MEM_B 28
=PP5V_S3_P5VRTS0FET 64
=PP3V3_S0_PWRCTL 63
=PP3V3_S0_VMON 63
=PP3V3_S0_CPUVTTISNS 41
64 =PP1V5_S0_FET PP1V5_S0 7
MIN_LINE_WIDTH=1.5 mm
VOLTAGE=1.5V =PP3V3_S0_SMBUS_MCP_1 39
MAKE_BASE=TRUE
=PP3V3_S0_P1V8S0 62
=PP1V5_S0_CPU 11 12
=PP3V3_S0_MCP_PLL_VLDO 62
=PP1V5_S0_VMON 63
=PP3V3_S0_MCPDDRISNS 41
=PP1V8R1V5_S0_MCP_MEM 16 23
=PP1V5_S0_MEM_MCP 28
58 26 =PPVTT_S3_DDR_BUF PPVTT_S3_DDR_BUF
=PP1V5_S0_MCP_PLL_VLDO 62 MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V 41 =PPCPUVCORE_VTT_ISNS PPBUS_G3H_CPU_ISNS
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 mm
(AFTER HIGH SIDE CPU VCORE VOLTAGE=12.6V
MAKE_BASE=TRUE
62 =PP1V8_S0_REG PP1V8_S0 7 & CPU VTT SENSING RES.)
MIN_LINE_WIDTH=0.10MM =PPVIN_S0_CPUVTTS0 61
MIN_NECK_WIDTH=0.10MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
"S5" RAILS =PPVIN_S5_CPU_IMVP 59
=PP3V3R1V8_S0_MCP_IFP_VDD 18 24
=PP1V8_S0_AUDIO
B
49
"ENET" RAILS 62 =PP1V05_S5_REG PP1V1R1V05_S5 7 B
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.05V
32 =PP3V3_ENET_FET PP3V3_ENET_PHY 7 MAKE_BASE=TRUE
=PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_UF MIN_NECK_WIDTH=0.2 MM =PP1V05_S5_MCP_VDD_AUXC
62 23 VOLTAGE=3.3V 22 23
MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm =PP1V05_ENET_P1V05ENETFET 32
VOLTAGE=1.05V =PP3V3_ENET_MCP_RMGT 18 23
MAKE_BASE=TRUE
=PP3V3_ENET_PHY 31
DIGITAL GROUND
GND
MIN_LINE_WIDTH=0.50MM
32 =PP1V05_ENET_FET PP1V2R1V05_ENET 7 MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.4 MM 57 =PP3V3_S5_REG PP3V3_S5 7 VOLTAGE=0V
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=1.5 mm
VOLTAGE=1.05V MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP1V05_ENET_MCP_PLL_MAC 23
=PP3V3_S5_MCP_GPIO 18 20
=PP1V05_ENET_MCP_RMGT 18 23 =PP3V3_S5_ROM 38 48
=PP3V3_S5_LCD 65
=PP1V05_ENET_PHY 31
=PP3V3_S5_MCP 22 23
=PP3V3_S5_MCPPWRGD 25
PEX & SATA AVDD/DVDD aliases =PP3V3_S5_PWRCTL 63
=PP3V3_S5_P1V05ENETFET 32
=PP3V3_S5_P3V3S3FET 64
=PP1V05_S0_MCP_PEX_AVDD0 17 =PP3V3_S5_P3V3S0FET 64
206 mA (A01)
23 PP1V05_S0_MCP_PEX_AVDD =PP1V05_S0_MCP_PEX_AVDD1 17 =PP3V3_S5_P1V05S5 62
MAKE_BASE=TRUE
=PP3V3_S5_MEMRESET 29
206 mA (A01)
=PP1V05_S0_MCP_PEX_DVDD0 17 =PP3V3_S5_P3V3ENETFET 32
57 mA (A01)
23 8 =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD1 17 =PP3V3_S5_DP_PORT_PWR 67
A 206 mA (A01)
23 PP1V05_S0_MCP_SATA_AVDD =PP1V05_S0_MCP_SATA_AVDD0 20
PAGE TITLE
MAKE_BASE=TRUE
127 mA (A01)
=PP1V05_S0_MCP_SATA_AVDD1 20
127 mA (A01)
Power Aliases
DRAWING NUMBER SIZE
23 8 =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0 20
43 mA (A01) Apple Inc. 051-7982 D
127 mA (A01) =PP1V05_S0_MCP_SATA_DVDD1 20 REVISION
R
C.0.0
8 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-E ALIASES DACS ALIASES SO-DIMM ALIASES
UNUSED GPU LANES
UNUSED CRT & TV-OUT INTERFACE UNUSED ADDRESS PINS
HEATSINK STANDOFFS 17 =PEG_D2R_N<15:0> NC_PEG_D2R_N<15:0>
NO_TEST=TRUE MAKE_BASE=TRUE 18 MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET
NO_TEST=TRUE MAKE_BASE=TRUE 27 MEM_A_A<15> TP_MEM_A_A15
Z0902 Z0901 17 =PEG_D2R_P<15:0> NC_PEG_D2R_P<15:0>
NO_TEST=TRUE 18 MCP_TV_DAC_VREF NC_MCP_TV_DAC_VREF 28 MEM_B_A<15> TP_MEM_B_A15
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH MAKE_BASE=TRUE
NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17 =PEG_R2D_C_N<15:0> NC_PEG_R2D_C_N<15:0>
1 1 NO_TEST=TRUE MAKE_BASE=TRUE 18 MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE MAKE_BASE=TRUE
17 =PEG_R2D_C_P<15:0> NC_PEG_R2D_C_P<15:0>
NO_TEST=TRUE MAKE_BASE=TRUE 18 MCP_CLK27M_XTALOUT NC_MCP_CLK27M_XTALOUT
17 PEG_PRSNT_L TP_PEG_PRSNT_L
LEFT OF CPU ABOVE CPU MAKE_BASE=TRUE 18 CRT_IG_R_C_PR NC_CRT_IG_R_C_PR
ETHERNET ALIASES
17 PEG_CLK100M_P TP_PEG_CLK100M_P
MAKE_BASE=TRUE 18 CRT_IG_G_Y_Y NC_CRT_IG_G_Y_Y
Z0903 Z0904 17 PEG_CLK100M_N TP_PEG_CLK100M_N
D STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
1
MAKE_BASE=TRUE 18 CRT_IG_B_COMP_PB NC_CRT_IG_B_COMP_PB
32
32
=P3V3ENET_EN
=P1V05ENET_EN
PM_SLP_RMGT_L
MAKE_BASE=TRUE
21
D
1 UNUSED EXPRESS CARD LANE 18 CRT_IG_HSYNC NC_CRT_IG_HSYNC
NO_TEST=TRUE MAKE_BASE=TRUE 31 =PP3V3_ENET_PHY_VDDREG RTL8211_VDDREG
MAKE_BASE=TRUE
17 PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_D2R_P 18 CRT_IG_VSYNC NC_CRT_IG_VSYNC 31 =RTL8211_REGOUT NC_RTL8211_REGOUT
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
BELOW MCP BELOW CPU 17 PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2R_N

31 =RTL8211_ENSWREG
MAKE_BASE=TRUE
FAN STANDOFF 17 PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_C_P

LVDS ALIASES
31 TP_RTL8211_CLK125 RTL8211_CLK125
MAKE_BASE=TRUE
MAKE_BASE=TRUE
OMIT 1
Z0905 17 PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_C_N
MAKE_BASE=TRUE
R0931
3P2R2P7 18 LVDS_IG_A_DATA_P<3> NC_LVDS_IG_A_DATA_P3 22
17 PCIE_EXCARD_PRSNT_L TP_PCIE_EXCARD_PRSNT_L NO_TEST=TRUE MAKE_BASE=TRUE 5%
1 MAKE_BASE=TRUE 1/16W
18 LVDS_IG_A_DATA_N<3> NC_LVDS_IG_A_DATA_N3 MF-LF
17 EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L NO_TEST=TRUE MAKE_BASE=TRUE 402
2
MAKE_BASE=TRUE
18 LVDS_IG_B_CLK_P NC_LVDS_IG_B_CLK_P
17 PCIE_CLK100M_EXCARD_P TP_PCIE_CLK100M_EXCARD_P NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
18 LVDS_IG_B_CLK_N NC_LVDS_IG_B_CLK_N
17 PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_EXCARD_N NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
18 LVDS_IG_B_DATA_P<3:0> NC_LVDS_IG_B_DATA_P<3:0>
UNUSED FIREWIRE LANE
18 LVDS_IG_B_DATA_N<3:0> NC_LVDS_IG_B_DATA_N<3:0> CPU FSB FREQUENCY STRAPS
MLB MOUNTING (TO C. BRACKET) SCREW HOLES 72 17 PCIE_FW_D2R_P TP_PCIE_FW_D2R_P
MAKE_BASE=TRUE
BSEL<2..0> FSB MHZ
OMIT 72 17 PCIE_FW_D2R_N TP_PCIE_FW_D2R_N
OMIT Z0907 MAKE_BASE=TRUE 0 0 0 266
Z0906 3P2R2P7 72 17 PCIE_FW_R2D_C_P TP_PCIE_FW_R2D_C_P 70 10 IN CPU_BSEL<0:2> =MCP_BSEL<0:2>
OUT 14
0
0
0
1
1
0
133
200
3P2R2P7 1
MAKE_BASE=TRUE
MISC MCP79 ALIASES MAKE_BASE=TRUE 0
1
1
0
1
0
(166)
333
1 72 17 PCIE_FW_R2D_C_N TP_PCIE_FW_R2D_C_N 1 0 1 100
MAKE_BASE=TRUE 1 1 0 (400)
14 CPU_PECI_MCP TP_CPU_PECI_MCP 1 1 1 (RSVD)
17 PCIE_FW_PRSNT_L TP_PCIE_FW_PRSNT_L MAKE_BASE=TRUE
MAKE_BASE=TRUE 19 FW_PME_L TP_FW_PME_L
MAKE_BASE=TRUE
17 FW_CLKREQ_L TP_FW_CLKREQ_L 17 GMUX_JTAG_TCK_L TP_GMUX_JTAG_TCK_L
MAKE_BASE=TRUE MAKE_BASE=TRUE
17 GMUX_JTAG_TDO TP_GMUX_JTAG_TDO
17 PCIE_CLK100M_FW_P TP_PCIE_CLK100M_FW_P MAKE_BASE=TRUE
MAKE_BASE=TRUE 19 GMUX_JTAG_TDI TP_GMUX_JTAG_TDI
C 17 PCIE_CLK100M_FW_N TP_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE
19 GMUX_JTAG_TMS
MCP_GPIO_4
TP_GMUX_JTAG_TMS
MIKEY_MIC_LOAD_DET
MAKE_BASE=TRUE
MAKE_BASE=TRUE SMC ALIASES C

MLB MOUNTING (TO TOPCASE) SCREW HOLES 21
17 CARDREADER_RESET TP_CARDREADER_RESET
MAKE_BASE=TRUE
54
MAKE_BASE=TRUE 36 SMC_SYS_KBDLED TP_SMC_SYS_KBDLED

OMIT MAKE_BASE=TRUE
OMIT Z0910 USB ALIASES
Z0911 3P2R2P7
3P2R2P7 1 UNUSED USB PORTS LAN ALIASES
1
18 =MCP_MII_RXER MCP_MII_PD
20 USB_EXTD_P TP_USB_EXTD_P MAKE_BASE=TRUE
MAKE_BASE=TRUE 18 =MCP_MII_COL
USB_EXTD_N TP_USB_EXTD_N 1
20
MAKE_BASE=TRUE 18 =MCP_MII_CRS R0930
20 USB_EXCARD_P TP_USB_EXCARD_P 47K CPU VCORE ALIASES
MAKE_BASE=TRUE 5%
USB_EXCARD_N TP_USB_EXCARD_N 1/16W
LVDS CONNECTOR HOLE 20
20 USB_MINI_P TP_USB_MINI_P
MAKE_BASE=TRUE MF-LF
402
2
MAKE_BASE=TRUE
20 USB_MINI_N TP_USB_MINI_N 59 IMVP6_VR_TT TP_IMVP6_VR_TT
OMIT MAKE_BASE=TRUE
DP HOTPLUG PULL-DOWN MAKE_BASE=TRUE
Z0913 20 USB_EXTC_P TP_USB_EXTC_P 59 IMVP6_NTC TP_IMVP6_NTC

3P2R2P7 20 USB_EXTC_N TP_USB_EXTC_N
1 MAKE_BASE=TRUE 18 =DVI_HPD_GMUX_INT HPLUG_DET2

73 20 USB_CARDREADER_P TP_USB_CARDREADER_P MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
73 20 USB_CARDREADER_N TP_USB_CARDREADER_N
MAKE_BASE=TRUE
R0940
73 20 USB_IR_N TP_USB_IR_N 20K
MAKE_BASE=TRUE 5%
73 20 USB_IR_P TP_USB_IR_P 1/16W
MAKE_BASE=TRUE MF-LF
402
EMI IO MEDIUM POGO PINS (870-1794 ) 2
OMIT OMIT OMIT OMIT

ZS0900 ZS0901 ZS0902 ZS0903
2.0DIA-MED-EMI-MLB-K84 2.0DIA-MED-EMI-MLB-K84 2.0DIA-MED-EMI-MLB-K84 2.0DIA-MED-EMI-MLB-K84
SM SM SM SM
1 1 1 1
B B
OMIT OMIT OMIT
ZS0908 ZS0909 ZS0911
2.0DIA-MED-EMI-MLB-K84 2.0DIA-MED-EMI-MLB-K84 2.0DIA-MED-EMI-MLB-K84
SM SM SM
1 1 1
EMI TALL POGO PINS (870-1698 )

OMIT OMIT OMIT OMIT OMIT
ZS0904 ZS0905 ZS0906 ZS0907 ZS0910
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
SM SM SM SM SM
1 1 1 1 1
OMIT
OMIT OMIT OMIT OMIT
ZS0912 ZS0913 ZS0914 ZS0915 ZS0919
2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
SM SM SM SM SM
1 1 1 1 1
A SYNC_MASTER=K24_MLB SYNC_DATE=02/04/2009 A
PAGE TITLE
SIGNAL ALIAS
EMI THINBC POGO PINS (870-1820 ) DRAWING NUMBER SIZE

OMIT REVISION
OMIT OMIT NOSTUFF
ZS0917 ZS0920
R
C.0.0
2.0DIA-MLB-THIN-BC-K84 ZS0918 ZS0916 2.0DIA-MLB-THIN-BC-K84 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SM 2.0DIA-MLB-THIN-BC-K84 2.0DIA-MLB-THIN-BC-K84 SM
SM SM
1 1 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 1
9 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
70 14 BI FSB_A_L<3> J4 A3* U1000 ADS* H1 FSB_ADS_L

BI 14 70
70 14 BI FSB_A_L<4> L5 A4* PENRYN BNR* E2 FSB_BNR_L

BI 14 70
FCBGA
70 14 BI FSB_A_L<5> L4 A5* BPRI* G5 FSB_BPRI_L
BI 14 70
1 OF 4 =PP1V05_S0_CPU 8 11 12 13
70 14 BI FSB_A_L<6> K5 A6*
70 14 BI FSB_A_L<7> M3 A7* DEFER* H5 FSB_DEFER_L BI 14 70
70 14 BI FSB_A_L<8> N2 A8* DRDY* F21 FSB_DRDY_L BI 14 70

1
70 14 FSB_A_L<9> J1 A9* DBSY* E1 FSB_DBSY_L 14 70
R1000
BI BI 54.9
70 14 BI FSB_A_L<10> N3 A10* 1%
ADDR GROUP0
1/16W
70 14 BI FSB_A_L<11> P5 A11* BR0* F1 FSB_BREQ0_L
BI 14 70 MF-LF
402
CONTROL
2
70 14 BI FSB_A_L<12> P2 A12*
D 70 14
70 14
BI
BI
FSB_A_L<13>
FSB_A_L<14>
L2
P4
A13*
A14*
IERR*
INIT*
D20
B3
70 CPU_IERR_L
CPU_INIT_L IN 14 70
D
70 14 BI FSB_A_L<15> P1 A15*
70 14 BI FSB_A_L<16> R1 A16* LOCK* H4 FSB_LOCK_L
BI 14 70
70 14 BI FSB_ADSTB_L<0> M1 ADSTB0*
RESET* C1 FSB_CPURST_L
IN 13 14 70
70 14 BI FSB_REQ_L<0> K3 REQ0* RS0* F3 FSB_RS_L<0>

IN 14 70
70 14 BI FSB_REQ_L<1> H2 REQ1* RS1* F4 FSB_RS_L<1> IN 14 70
70 14 BI FSB_REQ_L<2> K2
REQ2* RS2* G3 FSB_RS_L<2>
IN 14 70
70 14 BI FSB_REQ_L<3> J3 REQ3* TRDY* G2 FSB_TRDY_L IN 14 70
70 14 BI FSB_REQ_L<4> L1 REQ4*
HIT* G6 FSB_HIT_L
BI 14 70
OMIT
70 14 BI FSB_A_L<17> Y2 A17* HITM* E4 FSB_HITM_L BI 14 70
70 14 BI FSB_A_L<18> U5 A18* 70 14 BI FSB_D_L<0> E22 D0* U1000 D32* Y22 FSB_D_L<32> BI 14 70
70 14 BI FSB_A_L<19> R3 A19* BPM0* AD4 XDP_BPM_L<0> BI 13 70

1
70 14 BI FSB_D_L<1> F24 D1* PENRYN D33* AB24 FSB_D_L<33> BI 14 70
70 14 FSB_A_L<20> W6 A20* BPM1* AD3 XDP_BPM_L<1> 13 70

R1001 70 14 FSB_D_L<2> E26 D2* FCBGA D34* V24 FSB_D_L<34> 14 70
BI BI 54.9
BI BI
XDP/ITP SIGNALS
70 14 BI FSB_A_L<21> U4 A21* BPM2* AD1 XDP_BPM_L<2>
BI 13 70 1% 70 14 BI FSB_D_L<3> G22 D3* 2 OF 4 D35* V26 FSB_D_L<35> BI 14 70
ADDR GROUP1
1/16W
70 14 BI FSB_A_L<22> Y5 A22* BPM3* AC4 XDP_BPM_L<3> BI 13 70 MF-LF 70 14 BI FSB_D_L<4> F23 D4* D36* V23 FSB_D_L<36> BI 14 70
402
2
70 14 BI FSB_A_L<23> U1 A23* PRDY* AC2 XDP_BPM_L<4>
BI 13 70 70 14 BI FSB_D_L<5> G25 D5* D37* T22 FSB_D_L<37> BI 14 70
70 14 BI FSB_A_L<24> R4 A24* PREQ* AC1 XDP_BPM_L<5> BI 13 70 70 14 BI FSB_D_L<6> E25 D6* D38* U25 FSB_D_L<38> BI 14 70
70 14 BI FSB_A_L<25> T5 A25* TCK AC5 XDP_TCK

IN 10 13 70 70 14 BI FSB_D_L<7> E23 D7* D39* U23 FSB_D_L<39> BI 14 70
70 14 BI FSB_A_L<26> T3 A26* TDI AA6 XDP_TDI

IN 10 13 70 70 14 BI FSB_D_L<8> K24 D8* D40* Y25 FSB_D_L<40> BI 14 70
70 14 BI FSB_A_L<27> W2 A27* TDO AB3 XDP_TDO OUT 10 13 70 70 14 BI FSB_D_L<9> G24 D9* D41* W22 FSB_D_L<41> BI 14 70
DATA GRP 0
DATA GRP 2
70 14 BI FSB_A_L<28> W5 A28* TMS AB5 XDP_TMS
IN 10 13 70 70 14 BI FSB_D_L<10> J24 D10* D42* Y23 FSB_D_L<42> BI 14 70
70 14 BI FSB_A_L<29> Y4 A29* TRST* AB6 XDP_TRST_L IN 10 13 70 70 14 BI FSB_D_L<11> J23 D11* D43* W24 FSB_D_L<43> BI 14 70
70 14 BI FSB_A_L<30> U2 A30* DBR* C20 XDP_DBRESET_L OUT 13 25 70 14 BI FSB_D_L<12> H22 D12* D44* W25 FSB_D_L<44> BI 14 70
C 70 14 BI FSB_A_L<31> V4 A31* R1002

68
1
70 14 BI FSB_D_L<13> F26 D13* D45* AA23 FSB_D_L<45> BI 14 70 C
70 14 BI FSB_A_L<32> W3 A32* 5% 70 14 BI FSB_D_L<14> K22 D14* D46* AA24 FSB_D_L<46> BI 14 70
1/16W
70 14 FSB_A_L<33> AA4 A33* THERMAL MF-LF 70 14 FSB_D_L<15> H23 D15* D47* AB25 FSB_D_L<47> 14 70
BI BI BI
402
2
70 14 BI FSB_A_L<34> AB2 A34* 70 14 BI FSB_DSTB_L_N<0> J26 DSTBN0* DSTBN2* Y26 FSB_DSTB_L_N<2> BI 14 70
70 14 BI FSB_A_L<35> AA3 A35* PROCHOT* D21 CPU_PROCHOT_L OUT 14 37 70 70 14 BI FSB_DSTB_L_P<0> H26 DSTBP0* DSTBP2* AA26 FSB_DSTB_L_P<2> BI 14 70
70 14 BI FSB_ADSTB_L<1> V1 ADSTB1* THERMDA A24 CPU_THERMD_P

OUT 42 76 70 14 BI FSB_DINV_L<0> H25 DINV0* DINV2* U22 FSB_DINV_L<2>
BI 14 70
THERMDC B25 CPU_THERMD_N

OUT 42 76
70 14 IN CPU_A20M_L A6 A20M*
70 14 OUT CPU_FERR_L A5 FERR* THERMTRIP* C7 PM_THRMTRIP_L
OUT 14 37 70 70 14 BI FSB_D_L<16> N22 D16* D48* AE24 FSB_D_L<48>
BI 14 70
70 14 IN CPU_IGNNE_L C4 IGNNE* 70 14 BI FSB_D_L<17> K25 D17* D49* AD24 FSB_D_L<49>

BI 14 70
ICH
70 14 BI FSB_D_L<18> P26 D18* D50* AA21 FSB_D_L<50>

BI 14 70
H CLK
70 14 IN CPU_STPCLK_L D5 STPCLK* 70 14 BI FSB_D_L<19> R23 D19* D51* AB22 FSB_D_L<51>
BI 14 70
70 14 IN CPU_INTR C6 LINT0 70 14 BI FSB_D_L<20> L23 D20* D52* AB21 FSB_D_L<52>

BI 14 70
70 14 IN CPU_NMI B4 LINT1 BCLK0 A22 FSB_CLK_CPU_P IN 14 70 70 14 BI FSB_D_L<21> M24 D21* D53* AC26 FSB_D_L<53> BI 14 70
70 14 IN CPU_SMI_L A3
SMI* BCLK1 A21 FSB_CLK_CPU_N
IN 14 70 70 14 BI FSB_D_L<22> L22
D22* D54* AD20 FSB_D_L<54>
BI 14 70
70 14 BI FSB_D_L<23> M23 D23* D55* AE22 FSB_D_L<55> BI 14 70
DATA GRP 1
DATA GRP 3
TP_CPU_RSVD_M4 M4 RSVD0 70 14 BI FSB_D_L<24> P25 D24* D56* AF23 FSB_D_L<56> BI 14 70
TP_CPU_RSVD_N5 N5 RSVD1 70 14 BI FSB_D_L<25> P23 D25* D57* AC25 FSB_D_L<57> BI 14 70
TP_CPU_RSVD_T2 T2 RSVD2 70 14 BI FSB_D_L<26> P22

D26* D58* AE21 FSB_D_L<58> BI 14 70
TP_CPU_RSVD_V3 V3 RSVD3 70 14 BI FSB_D_L<27> T24 D27* D59* AD21 FSB_D_L<59>

BI 14 70
RESERVED
TP_CPU_RSVD_B2 B2 RSVD4 70 14 BI FSB_D_L<28> R24 D28* D60* AC22 FSB_D_L<60>

BI 14 70
TP_CPU_RSVD_F6 F6 RSVD5 70 14 BI FSB_D_L<29> L25 D29* D61* AD23 FSB_D_L<61>

BI 14 70
TP_CPU_RSVD_D2 D2 RSVD6 70 14 BI FSB_D_L<30> T25 D30* D62* AF22 FSB_D_L<62>

BI 14 70
TP_CPU_RSVD_D22 D22 RSVD7 1

70 14 BI FSB_D_L<31> N25 D31* D63* AC23 FSB_D_L<63>
BI 14 70
TP_CPU_RSVD_D3 D3 RSVD8 R1005 70 14 FSB_DSTB_L_N<1> L26 DSTBN1* DSTBN3* AE25 FSB_DSTB_L_N<3> 14 70

BI BI
1K
CPU JTAG Support 1% 70 14 BI FSB_DSTB_L_P<1> M26 DSTBP1* DSTBP3* AF24 FSB_DSTB_L_P<3>
BI 14 70
B R1090 2
1/16W
MF-LF
402
70 14 BI FSB_DINV_L<1> N24 DINV1* DINV3* AC20 FSB_DINV_L<3> BI 14 70
B
54.9
70 13 10 XDP_TMS 1 2 70 26 CPU_GTLREF AD26 GTLREF MISC COMP0 R26 70 CPU_COMP<0>
1% CPU_TEST1 C23 TEST1 COMP1 U26 70 CPU_COMP<1>

1/16W
R1091 MF-LF
1 CPU_TEST2 D25 TEST2 COMP2 AA1 70 CPU_COMP<2>
54.9 402
R1006
70 13 10 XDP_TDI 1 2 2.0K TP_CPU_TEST3 C24
TEST3 COMP3 Y1 70 CPU_COMP<3>
1%
1% 1/16W CPU_TEST4 AF26 TEST4
1/16W MF-LF
MF-LF R1092 402 NO STUFF TP_CPU_TEST5 AF1 TEST5 DPRSTP* E5 CPU_DPRSTP_L 14 59 70
1 1
402 54.9 2 IN R1023 R1021
1
70 13 10 XDP_TDO 1 2 C1014 TP_CPU_TEST6 A26 TEST6 DPSLP* B5 CPU_DPSLP_L
IN 14 70 54.9 54.9
1% 1%
PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% NO STUFF 0.1uF TP_CPU_TEST7 C3 TEST7 DPWR* D24 FSB_DPWR_L 14 70 1/16W 1/16W
1/16W 10% IN
MF-LF MF-LF
16V D6
MF-LF
R1010 X5R
2 70 9 OUT CPU_BSEL<0> B22 BSEL0 PWRGOOD CPU_PWRGD IN 13 14 70 402
2
402
2
402
402 D7
1
0
2
70 9 OUT CPU_BSEL<1> B23 BSEL1 SLP* FSB_CPUSLP_L IN 14 70
70 9 OUT CPU_BSEL<2> C21 BSEL2 PSI* AE6 CPU_PSI_L

OUT 59
1 1
NO STUFF 5% NO STUFF R1022 R1020
1/16W
1 1
R1011 MF-LF
R1012 27.4 27.4
R1093 402 1% 1%
54.9 1K 1K PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. 1/16W 1/16W
70 13 10 XDP_TCK 1 2 5% 5% MF-LF MF-LF
1/16W 1/16W PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. 2
402
2
402
1% MF-LF MF-LF
1/16W 402 402 PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
R1094 MF-LF 2 2
649 402
70 13 10 XDP_TRST_L 1 2
PLACEMENT_NOTE (all 4 resistors):
1%
1/16W Place within 12.7mm of CPU
MF-LF
402
PAGE TITLE
CPU FSB
DRAWING NUMBER SIZE
SYNC FROM T18 Apple Inc. 051-7982 D

REVISION
CHANGE CPU FROM SOCKET TO BGA SYMBOL

R
C.0.0
10 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A4 P6
A8 P21
(CPU CORE POWER)
OMIT
A11 P24
=PPVCORE_S0_CPU 8 11 12
A14
U1000 R2
A16
PENRYN
44 A (SV Design Target) R5
FCBGA
41 A (SV HFM) A19 R22
D A7 AB20 30.4 A (SV LFM) A23

4 OF 4
R25 D
A9 OMIT AB7 23 A (LV Design Target) AF2 T1
A10 AC7 B6 T4
U1000
A12 AC9 B8 T23
PENRYN
A13 AC12 B11 T26
FCBGA
A15 AC13 B13 U3

3 OF 4
A17 AC15 B16 U6
A18 AC17 B19 U21
A20 AC18 B21 U24
B7 AD7 B24 V2
B9 AD9 C5 V5
B10 AD10 C8 V22
B12 AD12 C11 V25
B14 AD14 C14 W1
B15 AD15 C16 W4
B17 AD17 C19 W23
B18 AD18 C2 W26
B20 AE9 C22 Y3

VCC
C9 AE10 C25 Y6
C10 AE12 D1 Y21
C12 AE13 D4 Y24
C13 AE15 D8 AA2
C15 AE17 D11 AA5
C17 AE18 D13 AA8
C18 AE20 D16 AA11
D9 AF9 D19 AA14
C D10
D12
AF10
AF12
D23
D26
AA16
AA19
C
D14 AF14 E3 AA22
D15 VCC AF15 E6 AA25
D17 AF17 E8 AB1
D18 AF18 E11 AB4

(CPU IO POWER 1.05V)
E7 AF20 E14 VSS VSS AB8
E9 =PP1V05_S0_CPU 8 10 12 13 E16 AB11
E10 G21 E19 AB13

4500 mA (before VCC stable)
E12 V6 E21 AB16
2500 mA (after VCC stable)
E13 J6 E24 AB19
E15 K6 F5 AB23
E17 M6 F8 AB26
E18 J21 F11 AC3
E20 K21 F13 AC6
F7 M21 F16 AC8

VCCP
F9 N21 F19 AC11
F10 N6 F2 AC14
F12 R21 F22 AC16
F14 R6 F25 AC19
F15 T21 G4 AC21
F17 T6 G1 AC24
F18 V21 G23 AD2

(CPU INTERNAL PLL POWER 1.5V)
F20 W21 G26 AD5
AA7 (BR1#) =PP1V5_S0_CPU 8 12 H3 AD8
AA9 B26 H6 AD11

130 mA
AA10 VCCA C26 H21 AD13
B AA12 H24 AD16 B

AA13 VID0 AD6 CPU_VID<0>
OUT 59 70 J2 AD19
AA15 VID1 AF5 CPU_VID<1>

OUT 59 70 J5 AD22
AA17 VID2 AE5 CPU_VID<2>

OUT 59 70 J22 AD25
=PPVCORE_S0_CPU 8 11 12
AA18 VID3 AF4 CPU_VID<3>
OUT 59 70 J25 AE1
AA20 VID4 AE3 CPU_VID<4>

OUT 59 70
1
K1 AE4
AB9 VID5 AF3 CPU_VID<5> 59 70

R1100 K4 AE8
OUT
100
AC10 VID6 AE2 CPU_VID<6>
OUT 59 70 1% K23 AE11
1/16W
AB10 MF-LF K26 AE14
402
AB12 2 L3 AE16
AB14 VCCSENSE AF7 CPU_VCCSENSE_P OUT 59 70 L6 AE19
AB15 L21 AE23

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
AB17 PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs. L24 AE26
AB18 VSSSENSE AE7 CPU_VCCSENSE_N

OUT 59 70 M2 A2
M5 AF6
1 M22 AF8
R1101
100 M25 AF11
1%
1/16W N1 AF13
MF-LF
402 N4 AF16
2
N23 AF19
N26 AF21
P3 A25
B1 (Socket-P KEY) AF25
PAGE TITLE
CPU Power & Ground

DRAWING NUMBER SIZE
SYNC FROM T18 051-7982 D
Apple Inc. REVISION
CHANGE CPU FROM SOCKET TO BGA SYMBOL R
C.0.0
11 OF 109
Current numbers from Merom for Santa Rosa EMTS, doc #20905. <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805
PLACEMENT_NOTE (C1200-C1219):
11 8 =PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D
1 1 1 1 1 1 1 1 1 1
C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 2 2 2 2 2 2 2 2 2
CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R
805 805 805 805 805 805 805 805 805 805
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 1 1 1 1 1 1 1 1 1
C1210 C1211 C1212 C1213 C1214 C1215 C1216 C1217 C1218 C1219
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 2 2 2 2 2 2 2 2 2
CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R
805 805 805 805 805 805 805 805 805 805
C C
PLACEMENT_NOTE (C1240-C1243):
Place on secondary side. Place on secondary side.
CRITICAL CRITICAL CRITICAL CRITICAL

NOSTUFF 1 1 1 1
C1240 C1241 C1242 C1243
470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM
20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT
D2T-SM D2T-SM D2T-SM D2T-SM
Place on secondary side. Place on secondary side.
VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF
11 8 =PP1V5_S0_CPU
PLACEMENT_NOTE=Place C1281 near CPU pin B26.
1 1
C1250 C1251
10uF 0.01UF
20% 10%
6.3V 16V
X5R 2 2
CERM
603 402
B B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
13 11 10 8 =PP1V05_S0_CPU
1 CRITICAL 1
C1261 1
C1262 1
C1263 1
C1264 1
C1265 1
C1266
C1260
330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20%
20%
10V 10V 10V 10V 10V 10V
2 2.5V 2
CERM
2
CERM
2
CERM
2
CERM
2
CERM
2
CERM
TANT
CASE-B2-SM 402 402 402 402 402 402
PAGE TITLE
CPU Decoupling
DRAWING NUMBER SIZE

REVISION
SYNC FROM T18 R
C.0.0
REMOVE NO STUFF CAPS C1220 TO C1231 NOTICE OF PROPRIETARY PROPERTY: BRANCH
REMOVE C1244 & C1245 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
12 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
D USE WITH 920-0782 ADAPTER FLEX TO SUPPORT CPU, MCP DEBUGGING.

D
MCP79-specific pinout
8 =PP3V3_S0_XDP
12 11 10 8 =PP1V05_S0_CPU
XDP
OMIT
1
R1315 CRITICAL
54.9
1%
J1300
1/16W DF40C-60DS-0.4V
MF-LF F-ST-SM
402
2
1 2
70 10 XDP_BPM_L<5> OBSFN_A0
3 4 OBSFN_C0 JTAG_MCP_TDO 21
BI IN
70 10 XDP_BPM_L<4> OBSFN_A1
5 6 OBSFN_C1 JTAG_MCP_TRST_L 21
BI OUT
7 8
70 10 XDP_BPM_L<3> OBSDATA_A0
9 10 OBSDATA_C0 MCP_DEBUG<0> 19 73
BI BI
70 10 XDP_BPM_L<2> OBSDATA_A1 11 12 OBSDATA_C1 MCP_DEBUG<1> 19 73
IN BI
13 14
70 10 XDP_BPM_L<1> OBSDATA_A2
15 16 OBSDATA_C2 MCP_DEBUG<2> 19 73
IN BI
70 10 XDP_BPM_L<0> OBSDATA_A3 17 18 OBSDATA_C3 MCP_DEBUG<3> 19 73
IN BI
19 20
C TP_XDP_OBSFN_B0 OBSFN_B0
21 22 OBSFN_D0 JTAG_MCP_TDI OUT 21
C
TP_XDP_OBSFN_B1 OBSFN_B1
23 24 OBSFN_D1 JTAG_MCP_TMS 21
OUT
25 26
TP_XDP_OBSDATA_B0 OBSDATA_B0
27 28 OBSDATA_D0 MCP_DEBUG<4> 19 73
BI
TP_XDP_OBSDATA_B1 OBSDATA_B1
29 30 OBSDATA_D1 MCP_DEBUG<5> 19 73
BI
31 32
TP_XDP_OBSDATA_B2 OBSDATA_B2 33 34 OBSDATA_D2 MCP_DEBUG<6> 19 73

BI
XDP 35 36
TP_XDP_OBSDATA_B3 OBSDATA_B3 OBSDATA_D3 MCP_DEBUG<7> 19 73
BI
R1399 37 38
1K
70 14 10 CPU_PWRGD 1 2 XDP_PWRGD PWRGD/HOOK0
39 40 ITPCLK/HOOK4 FSB_CLK_ITP_P 14 70
IN IN
41 42 XDP
5% XDP_OBS20 HOOK1 ITPCLK#/HOOK5 FSB_CLK_ITP_N IN 14 70
1/16W
MF-LF VCC_OBS_AB 43 44 VCC_OBS_CD R1303
402 1K
19 PM_LATRIGGER_L HOOK2 45 46 RESET#/HOOK6 70 XDP_CPURST_L 1 2 FSB_CPURST_L 10 14 70
IN IN
21 JTAG_MCP_TCK HOOK3
47 48 DBR#/HOOK7 XDP_DBRESET_L 10 25 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.
OUT OUT 1/16W
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
402
73 39 21 SMBUS_MCP_0_DATA SDA 51 52 TDO XDP_TDO 10 70
BI IN
73 39 21 SMBUS_MCP_0_CLK SCL 53 54 TRSTn XDP_TRST_L 10 70
BI OUT
TCK1 55 56 TDI XDP_TDI 10 70
NC OUT
70 10 XDP_TCK TCK0 57 58 TMS XDP_TMS 10 70
OUT OUT
59 60 XDP_PRESENT#
XDP XDP
1 1
C1300 C1301
0.1uF 0.1uF
10% 10%
16V 16V
2 2
X5R X5R
402 402
B (998-2515) B
518S0774
Direction of XDP module

Please avoid any obstructions
ON ODD-NUMBERED SIDE OF J1300
PAGE TITLE
eXtended Debug Port(MiniXDP)

DRAWING NUMBER SIZE

REVISION
R
C.0.0
13 OF 109
IV ALL RIGHTS RESERVED <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
70 10 BI FSB_DSTB_L_P<0> T40 CPU_DSTBP0# CPU_D0# Y43 FSB_D_L<0> BI 10 70
70 10 BI FSB_DSTB_L_N<0> U40 CPU_DSTBN0# CPU_D1# W42 FSB_D_L<1> BI 10 70
70 10 BI FSB_DINV_L<0> V41 CPU_DBI0# CPU_D2# Y40 FSB_D_L<2> BI 10 70
CPU_D3# W41 FSB_D_L<3>

BI 10 70
70 10 BI FSB_DSTB_L_P<1> W39 CPU_DSTBP1#
CPU_D4# Y39 FSB_D_L<4> BI 10 70
70 10 BI FSB_DSTB_L_N<1> W37 CPU_DSTBN1#
CPU_D5# V42 FSB_D_L<5>
BI 10 70
70 10 BI FSB_DINV_L<1> V35 CPU_DBI1#
CPU_D6# Y41 FSB_D_L<6>
BI 10 70
D 70 10
70 10
BI
BI
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
N37
L36
CPU_DSTBP2#
CPU_DSTBN2#
CPU_D7#
CPU_D8#
Y42
P42
FSB_D_L<7>
FSB_D_L<8>
BI
BI
10 70
10 70
D
70 10 BI FSB_DINV_L<2> N35 CPU_DBI2# CPU_D9# U41 FSB_D_L<9>
BI 10 70
CPU_D10# R42 FSB_D_L<10> BI 10 70

70 10 BI FSB_DSTB_L_P<3> M39 CPU_DSTBP3#
CPU_D11# T39 FSB_D_L<11> BI 10 70
70 10 BI FSB_DSTB_L_N<3> M41 CPU_DSTBN3#
CPU_D12# T42 FSB_D_L<12> BI 10 70
70 10 BI FSB_DINV_L<3> J41 CPU_DBI3#
CPU_D13# T41 FSB_D_L<13> BI 10 70
CPU_D14# R41 FSB_D_L<14> BI 10 70

70 10 BI FSB_A_L<3> AC34 CPU_A3#
CPU_D15# T43 FSB_D_L<15> BI 10 70
70 10 BI FSB_A_L<4> AE38
CPU_A4#
CPU_D16# W35 FSB_D_L<16> BI 10 70
70 10 BI FSB_A_L<5> AE34 CPU_A5#
CPU_D17# AA37 FSB_D_L<17> BI 10 70
70 10 BI FSB_A_L<6> AC37 CPU_A6#
CPU_D18# W33 FSB_D_L<18> BI 10 70
CPU_D19# W34 FSB_D_L<19> BI 10 70
CPU_D20# AA36 FSB_D_L<20> BI 10 70
70 10 BI FSB_A_L<9> AB35 CPU_A9#
CPU_D21# AA34 FSB_D_L<21> BI 10 70
70 10 BI FSB_A_L<10> AF35 CPU_A10#
CPU_D22# AA38 FSB_D_L<22> BI 10 70
70 10 BI FSB_A_L<11> AG35 CPU_A11#
CPU_D23# AA35 FSB_D_L<23> BI 10 70
70 10 BI FSB_A_L<12> AG39 CPU_A12#
CPU_D24# U38 FSB_D_L<24> BI 10 70
70 10 BI FSB_A_L<13> AE33 CPU_A13#
CPU_D25# U36 FSB_D_L<25> BI 10 70
70 10 BI FSB_A_L<14> AG37 CPU_A14#
CPU_D26# U35 FSB_D_L<26> BI 10 70
70 10 BI FSB_A_L<15> AG38 CPU_A15#
CPU_D27# U33 FSB_D_L<27> BI 10 70
70 10 BI FSB_A_L<16> AG34 CPU_A16#
CPU_D28# U34 FSB_D_L<28> BI 10 70
70 10 BI FSB_A_L<17> AN38
CPU_A17#
CPU_D29# W38 FSB_D_L<29> BI 10 70
70 10 BI FSB_A_L<18> AL39 CPU_A18#
CPU_D30# R33 FSB_D_L<30> BI 10 70
70 10 BI FSB_A_L<19> AG33 CPU_A19#
CPU_D31# U37 FSB_D_L<31> BI 10 70
70 10 BI FSB_A_L<20> AL33 CPU_A20#
CPU_D32# N34 FSB_D_L<32> BI 10 70
70 10 BI FSB_A_L<21> AJ33 CPU_A21#
CPU_D33# N33 FSB_D_L<33> BI 10 70
C 70 10
70 10
BI
BI
FSB_A_L<22>
FSB_A_L<23>
AN36
AJ35
CPU_A22#
CPU_A23#
CPU_D34#
CPU_D35#
R34
R35
FSB_D_L<34>
FSB_D_L<35>
BI 10 70 C
FSB
BI 10 70
70 10 BI FSB_A_L<24> AJ37 CPU_A24#
CPU_D36# P35 FSB_D_L<36>
BI 10 70
70 10 BI FSB_A_L<25> AJ36 CPU_A25#
CPU_D37# R39 FSB_D_L<37> BI 10 70
70 10 BI FSB_A_L<26> AJ38 CPU_A26#
CPU_D38# R37 FSB_D_L<38> BI 10 70
70 10 BI FSB_A_L<27> AL37 CPU_A27#
CPU_D39# R38 FSB_D_L<39> BI 10 70
70 10 BI FSB_A_L<28> AL34 CPU_A28#
CPU_D40# L37 FSB_D_L<40> BI 10 70
70 10 BI FSB_A_L<29> AN37 CPU_A29#
CPU_D41# L39 FSB_D_L<41> BI 10 70
70 10 BI FSB_A_L<30> AJ34
CPU_A30#
CPU_D42# L38 FSB_D_L<42> BI 10 70
70 10 BI FSB_A_L<31> AL38 CPU_A31#
CPU_D43# N36 FSB_D_L<43> BI 10 70
70 10 BI FSB_A_L<32> AL35 CPU_A32#
CPU_D44# N38 FSB_D_L<44> BI 10 70
70 10 BI FSB_A_L<33> AN34 CPU_A33#
CPU_D45# J39 FSB_D_L<45>
BI 10 70
70 10 BI FSB_A_L<34> AR39 CPU_A34#
CPU_D46# J38 FSB_D_L<46> BI 10 70
70 10 BI FSB_A_L<35> AN35 CPU_A35#
CPU_D47# J37 FSB_D_L<47> BI 10 70
70 10 BI FSB_ADSTB_L<0> AE36
CPU_ADSTB0# CPU_D48# L42 FSB_D_L<48> BI 10 70
70 10 BI FSB_ADSTB_L<1> AK35 CPU_ADSTB1# CPU_D49# M42 FSB_D_L<49> BI 10 70
CPU_D50# P41 FSB_D_L<50> BI 10 70
70 10 BI FSB_REQ_L<0> AC38 CPU_REQ0# CPU_D51# N41 FSB_D_L<51> BI 10 70
70 10 BI FSB_REQ_L<1> AA33 CPU_REQ1# CPU_D52# N40 FSB_D_L<52> BI 10 70

23 22 14 8 =PP1V05_S0_MCP_FSB
70 10 BI FSB_REQ_L<2> AC39 CPU_REQ2# CPU_D53# M40 FSB_D_L<53> BI 10 70
70 10 BI FSB_REQ_L<3> AC33 CPU_REQ3# CPU_D54# H40 FSB_D_L<54> BI 10 70
1 1 1
70 10 BI FSB_REQ_L<4> AC35 CPU_REQ4# CPU_D55# K42 FSB_D_L<55> BI 10 70
R1410 R1415 R1416 CPU_D56# H41 FSB_D_L<56> 10 70
BI
54.9 62 62
1% 5% 5% 70 10 BI FSB_ADS_L AD42 CPU_ADS# CPU_D57# L41 FSB_D_L<57> BI 10 70
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 70 10 BI FSB_BNR_L AD43 CPU_BNR# CPU_D58# H43 FSB_D_L<58> BI 10 70
402 402 402
2 2 2
70 10 BI FSB_BREQ0_L AE40 CPU_BR0# CPU_D59# H42 FSB_D_L<59>
BI 10 70
B 70 37 10 IN PM_THRMTRIP_L 70 10 BI
70 FSB_BREQ1_L
FSB_DBSY_L
AL32
AD39
CPU_BR1#
CPU_DBSY#
CPU_D60#
CPU_D61#
K41
J40
FSB_D_L<60>
FSB_D_L<61>
BI
BI
10 70
10 70
B
70 10 IN CPU_FERR_L 70 10 BI FSB_DRDY_L AD41 CPU_DRDY# CPU_D62# H39 FSB_D_L<62>
BI 10 70
70 10 BI FSB_HIT_L AB42 CPU_HIT# CPU_D63# M43 FSB_D_L<63> BI 10 70
70 10 BI FSB_HITM_L AD40 CPU_HITM#

70 10 IN FSB_LOCK_L AC43
CPU_LOCK# CPU_BPRI# AA41 FSB_BPRI_L OUT 10 70
70 10 OUT FSB_TRDY_L AE41 CPU_TRDY# CPU_DEFER# AA40 FSB_DEFER_L OUT 10 70
NO STUFF NO STUFF NO STUFF

9 OUT CPU_PECI_MCP E41 CPU_PECI
R1420
1
R1421
1 1
R1422 BCLK_OUT_CPU_P G42 FSB_CLK_CPU_P
OUT 10 70
70 37 10 OUT CPU_PROCHOT_L AJ41 CPU_PROCHOT#
1K 1K 1K BCLK_OUT_CPU_N G41 FSB_CLK_CPU_N
OUT 10 70
5% 5% 5% AG43 CPU_THERMTRIP#
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF AH40 CPU_FERR# BCLK_OUT_ITP_P AL43 FSB_CLK_ITP_P
OUT 13 70
402 402 402
2 2 2
BCLK_OUT_ITP_N AL42 FSB_CLK_ITP_N
OUT 13 70
9 IN =MCP_BSEL<2> (MCP_BSEL<2>) F42 CPU_BSEL2

BCLK_OUT_NB_P AL41 70 FSB_CLK_MCP_P
9 IN =MCP_BSEL<1> (MCP_BSEL<1>) D42 CPU_BSEL1
BCLK_OUT_NB_N AK42 70 FSB_CLK_MCP_N
9 IN =MCP_BSEL<0> (MCP_BSEL<0>) F41 CPU_BSEL0
Loop-back clock for delay matching.
70 10 OUT FSB_RS_L<0> AC41 CPU_RS0# BCLK_IN_N AK41
70 10 OUT FSB_RS_L<1> AB41 CPU_RS1# BCLK_IN_P AJ40
70 10 OUT FSB_RS_L<2> AC42 CPU_RS2#
R1430
1 1
R1435 23 PP1V05_S0_MCP_PLL_FSB CPU_A20M# AF41 CPU_A20M_L
OUT 10 70 =PP1V05_S0_MCP_FSB 8 14 22 23
49.9 49.9 270 mA (A01) 206 mA AG27 +V_DLL_DLCELL_AVDD CPU_IGNNE# AH39 CPU_IGNNE_L OUT 10 70 NO STUFF
1% 1%
1/16W 1/16W 20 mA AH27 +V_PLL_MCLK CPU_INIT# AH42 CPU_INIT_L OUT 10 70
1
R1440
MF-LF MF-LF
402
2 2
402 29 mA AG28 +V_PLL_FSB CPU_INTR AF42 CPU_INTR OUT 10 70 150
5%
15 mA AH28 +V_PLL_CPU CPU_NMI AG41 CPU_NMI
OUT 10 70 1/16W
MF-LF
CPU_SMI#
A AH41 CPU_SMI_L
70 MCP_BCLK_VML_COMP_VDD AM39 BCLK_VML_COMP_VDD
CPU_PWRGD AH43 CPU_PWRGD
OUT 10 70
2
402
OUT 10 13 70
SYNC_MASTER=K24_MLB
PAGE TITLE
SYNC_DATE=04/06/2009 A
70 MCP_BCLK_VML_COMP_GND AM40 BCLK_VML_COMP_GND
CPU_RESET# H38 FSB_CPURST_L OUT 10 13 70
MCP CPU Interface
70 MCP_CPU_COMP_VCC AM43 CPU_COMP_VCC CPU_SLP# AM33 FSB_CPUSLP_L
OUT 10 70 DRAWING NUMBER SIZE
1 1
70 MCP_CPU_COMP_GND AM42 CPU_COMP_GND CPU_DPSLP# AN33 CPU_DPSLP_L
OUT 10 70
R1431 R1436 CPU_DPWR# AM32 FSB_DPWR_L 10 70 REVISION
49.9 49.9
OUT
1%
1/16W
1%
1/16W
CPU_STPCLK# AG42 CPU_STPCLK_L OUT 10 70
R
C.0.0
MF-LF MF-LF CPU_DPRSTP# AN32 CPU_DPRSTP_L OUT 10 59 70 NOTICE OF PROPRIETARY PROPERTY: BRANCH
402 402
2 2
14 OF 109
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number). <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(2 OF 11) (3 OF 11)
71 27 BI MEM_A_DQ<63> AL8 MDQ0_63 MDQS0_7_P AL10 MEM_A_DQS_P<7>

BI 27 71 71 28 BI MEM_B_DQ<63> AT4 MDQ1_63 MDQS1_7_P AT2 MEM_B_DQS_P<7>
BI 28 71
71 27 BI MEM_A_DQ<62> AL9 MDQ0_62 MDQS0_7_N AL11 MEM_A_DQS_N<7> BI 27 71 71 28 BI MEM_B_DQ<62> AT3 MDQ1_62 MDQS1_7_N AT1 MEM_B_DQS_N<7> BI 28 71
71 27 BI MEM_A_DQ<61> AP9 MDQ0_61 MDQS0_6_P AR8 MEM_A_DQS_P<6>

BI 27 71 71 28 BI MEM_B_DQ<61> AV2 MDQ1_61 MDQS1_6_P AY2 MEM_B_DQS_P<6>
BI 28 71
71 27 BI MEM_A_DQ<60> AN9 MDQ0_60 MDQS0_6_N AR9 MEM_A_DQS_N<6>

BI 27 71 71 28 BI MEM_B_DQ<60> AV3 MDQ1_60 MDQS1_6_N AY1 MEM_B_DQS_N<6>
BI 28 71
D 71 27
71 27
BI
BI
MEM_A_DQ<59>
MEM_A_DQ<58>
AL6
AL7
MDQ0_59
MDQ0_58
MDQS0_5_P
MDQS0_5_N
AW7
AW8
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
BI
BI
27 71
27 71
71 28
71 28
BI
BI
MEM_B_DQ<59>
MEM_B_DQ<58>
AR4
AR3
MDQ1_59
MDQ1_58
MDQS1_5_P
MDQS1_5_N
BB6
BA6
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
BI
BI
28 71
28 71
D
71 27 BI MEM_A_DQ<57> AN6
MDQ0_57 MDQS0_4_P AP13 MEM_A_DQS_P<4>
BI 27 71 71 28 BI MEM_B_DQ<57> AU2
MDQ1_57 MDQS1_4_P BA10 MEM_B_DQS_P<4>
BI 28 71
71 27 BI MEM_A_DQ<56> AN7 MDQ0_56 MDQS0_4_N AR13 MEM_A_DQS_N<4> BI 27 71 71 28 BI MEM_B_DQ<56> AU3 MDQ1_56 MDQS1_4_N AY11 MEM_B_DQS_N<4> BI 28 71
71 27 BI MEM_A_DQ<55> AR6 MDQ0_55 MDQS0_3_P AV25 MEM_A_DQS_P<3> BI 27 71 71 28 BI MEM_B_DQ<55> AY4 MDQ1_55 MDQS1_3_P BB33 MEM_B_DQS_P<3> BI 28 71
71 27 BI MEM_A_DQ<54> AR7 MDQ0_54 MDQS0_3_N AW25 MEM_A_DQS_N<3>

BI 27 71 71 28 BI MEM_B_DQ<54> AY3 MDQ1_54 MDQS1_3_N BA33 MEM_B_DQS_N<3>
BI 28 71
71 27 BI MEM_A_DQ<53> AV6 MDQ0_53 MDQS0_2_P AU30 MEM_A_DQS_P<2> BI 27 71 71 28 BI MEM_B_DQ<53> BB3 MDQ1_53 MDQS1_2_P BB37 MEM_B_DQS_P<2> BI 28 71
71 27 BI MEM_A_DQ<52> AW5 MDQ0_52 MDQS0_2_N AU29 MEM_A_DQS_N<2>

BI 27 71 71 28 BI MEM_B_DQ<52> BC3 MDQ1_52 MDQS1_2_N BA37 MEM_B_DQS_N<2>
BI 28 71
71 27 BI MEM_A_DQ<51> AN10 MDQ0_51 MDQS0_1_P AT35 MEM_A_DQS_P<1>

BI 27 71 71 28 BI MEM_B_DQ<51> AW4 MDQ1_51 MDQS1_1_P BA43 MEM_B_DQS_P<1>
BI 28 71
71 27 BI MEM_A_DQ<50> AR5 MDQ0_50 MDQS0_1_N AU35 MEM_A_DQS_N<1>

BI 27 71 71 28 BI MEM_B_DQ<50> AW3 MDQ1_50 MDQS1_1_N AY42 MEM_B_DQS_N<1>
BI 28 71
71 27 BI MEM_A_DQ<49> AU6 MDQ0_49 MDQS0_0_P AU39 MEM_A_DQS_P<0> BI 27 71 71 28 BI MEM_B_DQ<49> BA3 MDQ1_49 MDQS1_0_P AT42 MEM_B_DQS_P<0> BI 28 71
71 27 BI MEM_A_DQ<48> AV5 MDQ0_48 MDQS0_0_N AT39 MEM_A_DQS_N<0>

BI 27 71 71 28 BI MEM_B_DQ<48> BB2 MDQ1_48 MDQS1_0_N AT43 MEM_B_DQS_N<0>
BI 28 71
71 27 BI MEM_A_DQ<47> AU7 MDQ0_47 71 28 BI MEM_B_DQ<47> BB5 MDQ1_47

71 27 BI MEM_A_DQ<46> AU8 MDQ0_46 71 28 BI MEM_B_DQ<46> BA5 MDQ1_46
MEMORY PARTITION 0
MEMORY PARTITION 1
71 27 BI MEM_A_DQ<45> AW9 MDQ0_45 71 28 BI MEM_B_DQ<45> BA8 MDQ1_45
71 27 BI MEM_A_DQ<44> AP11
MDQ0_44 71 28 BI MEM_B_DQ<44> BC8
MDQ1_44
71 27 BI MEM_A_DQ<43> AW6 MDQ0_43 71 28 BI MEM_B_DQ<43> BB4 MDQ1_43
71 27 BI MEM_A_DQ<42> AY5 MDQ0_42 MRAS0# AV17 MEM_A_RAS_L
OUT 27 71 71 28 BI MEM_B_DQ<42> BC4 MDQ1_42 MRAS1# AW16 MEM_B_RAS_L
OUT 28 71
71 27 BI MEM_A_DQ<41> AU9 MDQ0_41 MCAS0# AP17 MEM_A_CAS_L OUT 27 71 71 28 BI MEM_B_DQ<41> BA7 MDQ1_41 MCAS1# BA15 MEM_B_CAS_L OUT 28 71
71 27 BI MEM_A_DQ<40> AV9 MDQ0_40 MWE0# AR17 MEM_A_WE_L OUT 27 71 71 28 BI MEM_B_DQ<40> AY8 MDQ1_40 MWE1# BA16 MEM_B_WE_L OUT 28 71
71 27 BI MEM_A_DQ<39> AU11 MDQ0_39 71 28 BI MEM_B_DQ<39> BA9 MDQ1_39

71 27 BI MEM_A_DQ<38> AV11 MDQ0_38 71 28 BI MEM_B_DQ<38> BB10 MDQ1_38
71 27 BI MEM_A_DQ<37> AV13 MDQ0_37 71 28 BI MEM_B_DQ<37> BB12 MDQ1_37
71 27 BI MEM_A_DQ<36> AW13 MDQ0_36 71 28 BI MEM_B_DQ<36> AW12 MDQ1_36
71 27 BI MEM_A_DQ<35> AR11 MDQ0_35 71 28 BI MEM_B_DQ<35> BB8 MDQ1_35
71 27 BI MEM_A_DQ<34> AT11 MDQ0_34 MBA0_2 AP23 MEM_A_BA<2>
OUT 27 71 71 28 BI MEM_B_DQ<34> BB9 MDQ1_34 MBA1_2 BB29 MEM_B_BA<2>
OUT 28 71
71 27 BI MEM_A_DQ<33> AR14 MDQ0_33 MBA0_1 AP19 MEM_A_BA<1>

OUT 27 71 71 28 BI MEM_B_DQ<33> AY12 MDQ1_33 MBA1_1 BB18 MEM_B_BA<1>
OUT 28 71
C 71 27 BI MEM_A_DQ<32> AU13 MDQ0_32 MBA0_0 AW17 MEM_A_BA<0> OUT 27 71 71 28 BI MEM_B_DQ<32> BA12 MDQ1_32 MBA1_0 BB17 MEM_B_BA<0> OUT 28 71 C
71 27 BI MEM_A_DQ<31> AR26
MDQ0_31 71 28 BI MEM_B_DQ<31> BC32
MDQ1_31
71 27 BI MEM_A_DQ<30> AU25 MDQ0_30 71 28 BI MEM_B_DQ<30> AW32 MDQ1_30
71 27 BI MEM_A_DQ<29> AT27 MDQ0_29 71 28 BI MEM_B_DQ<29> BA35 MDQ1_29
71 27 BI MEM_A_DQ<28> AU27 MDQ0_28 71 28 BI MEM_B_DQ<28> AY36 MDQ1_28
71 27 BI MEM_A_DQ<27> AP25 MDQ0_27 71 28 BI MEM_B_DQ<27> BA32 MDQ1_27
MA0_14 AR23 MEM_A_A<14>
OUT 27 71 MA1_14 BA29 MEM_B_A<14>
OUT 28 71
71 27 BI MEM_A_DQ<26> AR25 MDQ0_26 71 28 BI MEM_B_DQ<26> BB32 MDQ1_26
MA0_13 AU15 MEM_A_A<13> OUT 27 71 MA1_13 BA14 MEM_B_A<13> OUT 28 71
MA0_12 AN23 MEM_A_A<12>
OUT 27 71 MA1_12 AW28 MEM_B_A<12>
OUT 28 71
71 27 BI MEM_A_DQ<24> AR27 MDQ0_24 71 28 BI MEM_B_DQ<24> AY35 MDQ1_24
MA0_11 AW21 MEM_A_A<11>
OUT 27 71 MA1_11 BC28 MEM_B_A<11>
OUT 28 71
71 27 BI MEM_A_DQ<23> AP29 MDQ0_23 71 28 BI MEM_B_DQ<23> BC36 MDQ1_23
MA0_10 AN19 MEM_A_A<10>
OUT 27 71 MA1_10 BA17 MEM_B_A<10>
OUT 28 71
71 27 BI MEM_A_DQ<22> AR29 MDQ0_22 71 28 BI MEM_B_DQ<22> AW36 MDQ1_22
MA0_9 AV21 MEM_A_A<9> OUT 27 71 MA1_9 BB28 MEM_B_A<9> OUT 28 71
MA0_8 AR22 MEM_A_A<8> OUT 27 71 MA1_8 AY28 MEM_B_A<8> OUT 28 71
71 27 BI MEM_A_DQ<20> AR31 MDQ0_20 71 28 BI MEM_B_DQ<20> AY40 MDQ1_20
MA0_7 AU21 MEM_A_A<7> OUT 27 71 MA1_7 BA28 MEM_B_A<7> OUT 28 71
71 27 BI MEM_A_DQ<19> AV27 MDQ0_19 71 28 BI MEM_B_DQ<19> BA36 MDQ1_19
MA0_6 AP21 MEM_A_A<6>
OUT 27 71 MA1_6 AY27 MEM_B_A<6>
OUT 28 71
71 27 BI MEM_A_DQ<18> AN29
MDQ0_18 71 28 BI MEM_B_DQ<18> BB36
MDQ1_18
MA0_5 AR21 MEM_A_A<5>
OUT 27 71 MA1_5 BA27 MEM_B_A<5>
OUT 28 71
71 27 BI MEM_A_DQ<17> AV29 MDQ0_17 71 28 BI MEM_B_DQ<17> BA38 MDQ1_17
MA0_4 AN21 MEM_A_A<4>
OUT 27 71 MA1_4 BA26 MEM_B_A<4>
OUT 28 71
71 27 BI MEM_A_DQ<16> AN31 MDQ0_16 71 28 BI MEM_B_DQ<16> AY39 MDQ1_16
MA0_3 AV19 MEM_A_A<3>
OUT 27 71 MA1_3 BB26 MEM_B_A<3>
OUT 28 71
71 27 BI MEM_A_DQ<15> AU31 MDQ0_15 71 28 BI MEM_B_DQ<15> BB40 MDQ1_15
MA0_2 AU19 MEM_A_A<2>
OUT 27 71 MA1_2 BA25 MEM_B_A<2>
OUT 28 71
71 27 BI MEM_A_DQ<14> AR33
MDQ0_14 71 28 BI MEM_B_DQ<14> AW40
MDQ1_14
MA0_1 AT19 MEM_A_A<1> OUT 27 71 MA1_1 BB25 MEM_B_A<1> OUT 28 71
71 27 BI MEM_A_DQ<13> AV37 MDQ0_13 71 28 BI MEM_B_DQ<13> AV42 MDQ1_13
MA0_0 AR19 MEM_A_A<0> OUT 27 71 MA1_0 BA18 MEM_B_A<0> OUT 28 71
71 27 BI MEM_A_DQ<12> AW37 MDQ0_12 71 28 BI MEM_B_DQ<12> AV41 MDQ1_12
71 27 BI MEM_A_DQ<11> AT31 MDQ0_11 71 28 BI MEM_B_DQ<11> BA40 MDQ1_11
71 27 BI MEM_A_DQ<10> AV31 MDQ0_10 71 28 BI MEM_B_DQ<10> BC40 MDQ1_10
MEMORY MEMORY
71 27 BI MEM_A_DQ<9> AT37 MDQ0_9 71 28 BI MEM_B_DQ<9> AW42 MDQ1_9
CONTROL CONTROL
71 27 BI MEM_A_DQ<8> AU37 MDQ0_8 71 28 BI MEM_B_DQ<8> AW41 MDQ1_8
0A 1A
71 27 BI MEM_A_DQ<7> AW39 MDQ0_7 71 28 BI MEM_B_DQ<7> AT40 MDQ1_7
MCLK0A_2_P AW33 TP_MEM_A_CLK2P MCLK1A_2_P BA42 TP_MEM_B_CLK2P
B 71 27
71 27
BI
BI
MEM_A_DQ<6>
MEM_A_DQ<5>
AV39
AR37
MDQ0_6
MDQ0_5
MCLK0A_2_N AV33 TP_MEM_A_CLK2N
71 28
71 28
BI
BI
MEM_B_DQ<6>
MEM_B_DQ<5>
AT41
AP41
MDQ1_6
MDQ1_5
MCLK1A_2_N BB42 TP_MEM_B_CLK2N B
71 27 BI MEM_A_DQ<4> AR38 MDQ0_4 MCLK0A_1_P BA24 MEM_A_CLK_P<1> OUT 27 71 71 28 BI MEM_B_DQ<4> AN40 MDQ1_4 MCLK1A_1_P BB22 MEM_B_CLK_P<1> OUT 28 71
71 27 BI MEM_A_DQ<3> AV38 MDQ0_3 MCLK0A_1_N AY24 MEM_A_CLK_N<1> OUT 27 71 71 28 BI MEM_B_DQ<3> AU40 MDQ1_3 MCLK1A_1_N BA22 MEM_B_CLK_N<1> OUT 28 71
71 27 BI MEM_A_DQ<2> AW38 MDQ0_2 71 28 BI MEM_B_DQ<2> AU41 MDQ1_2

MCLK0A_0_P BB20 MEM_A_CLK_P<0> OUT 27 71 MCLK1A_0_P BA19 MEM_B_CLK_P<0> OUT 28 71
71 27 BI MEM_A_DQ<1> AR35
MDQ0_1 71 28 BI MEM_B_DQ<1> AR41
MDQ1_1
MCLK0A_0_N BC20 MEM_A_CLK_N<0> OUT 27 71 MCLK1A_0_N AY19 MEM_B_CLK_N<0> OUT 28 71
71 27 BI MEM_A_DQ<0> AP35 MDQ0_0 71 28 BI MEM_B_DQ<0> AP42 MDQ1_0
71 27 OUT MEM_A_DM<7> AN5 MDQM0_7 MCS0A_1# AT15 MEM_A_CS_L<1> OUT 27 71 71 28 OUT MEM_B_DM<7> AT5 MDQM1_7 MCS1A_1# BB14 MEM_B_CS_L<1> OUT 28 71
71 27 OUT MEM_A_DM<6> AU5 MDQM0_6 MCS0A_0# AR18 MEM_A_CS_L<0>

OUT 27 71 71 28 OUT MEM_B_DM<6> BA2 MDQM1_6 MCS1A_0# BB16 MEM_B_CS_L<0>
OUT 28 71
71 27 OUT MEM_A_DM<5> AR10 MDQM0_5 71 28 OUT MEM_B_DM<5> AY7 MDQM1_5

71 27 OUT MEM_A_DM<4> AN13 MDQM0_4 MODT0A_1 AP15 MEM_A_ODT<1> OUT 27 71 71 28 OUT MEM_B_DM<4> BA11 MDQM1_4 MODT1A_1 BB13 MEM_B_ODT<1> OUT 28 71
71 27 OUT MEM_A_DM<3> AN27

MDQM0_3 MODT0A_0 AV15 MEM_A_ODT<0> OUT 27 71 71 28 OUT MEM_B_DM<3> BB34
MDQM1_3 MODT1A_0 AY15 MEM_B_ODT<0> OUT 28 71
71 27 OUT MEM_A_DM<2> AW29 MDQM0_2 71 28 OUT MEM_B_DM<2> BB38 MDQM1_2

71 27 OUT MEM_A_DM<1> AV35 MDQM0_1 MCKE0A_1 AU23 MEM_A_CKE<1> OUT 27 71 71 28 OUT MEM_B_DM<1> AY43 MDQM1_1 MCKE1A_1 AY31 MEM_B_CKE<1> OUT 28 71
71 27 OUT MEM_A_DM<0> AR34 MDQM0_0 MCKE0A_0 AT23 MEM_A_CKE<0> OUT 27 71 71 28 OUT MEM_B_DM<0> AR42 MDQM1_0 MCKE1A_0 BB30 MEM_B_CKE<0> OUT 28 71
PAGE TITLE
MCP Memory Interface

DRAWING NUMBER SIZE

REVISION
R
C.0.0
15 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(4 OF 11)
TP_MEM_A_CLK5P AU33 MCLK0B_2_P MCLK1B_2_P BA41 TP_MEM_B_CLK5P
MEMORY CONTROL 0B
MEMORY CONTROL 1B
TP_MEM_A_CLK5N AU34 MCLK0B_2_N MCLK1B_2_N BB41 TP_MEM_B_CLK5N
D TP_MEM_A_CLK4P BB24 MCLK0B_1_P MCLK1B_1_P AY23 TP_MEM_B_CLK4P
TP_MEM_A_CLK4N BC24 MCLK0B_1_N MCLK1B_1_N BA23 TP_MEM_B_CLK4N
TP_MEM_A_CLK3P BA21 MCLK0B_0_P MCLK1B_0_P BA20 TP_MEM_B_CLK3P

TP_MEM_A_CLK3N BB21 MCLK0B_0_N MCLK1B_0_N AY20 TP_MEM_B_CLK3N
TP_MEM_A_CS_L<2> AU17 MCS0B_0# MCS1B_0# BC16 TP_MEM_B_CS_L<2>

TP_MEM_A_CS_L<3> AR15 MCS0B_1# MCS1B_1# BA13 TP_MEM_B_CS_L<3>
TP_MEM_A_ODT<2> AN17 MODT0B_0 MODT1B_0 AY16 TP_MEM_B_ODT<2>

TP_MEM_A_ODT<3> AN15 MODT0B_1 MODT1B_1 BC13 TP_MEM_B_ODT<3>
TP_MEM_A_CKE<2> AV23 MCKE0B_0 MCKE1B_0 BA30 TP_MEM_B_CKE<2>

TP_MEM_A_CKE<3> AN25 MCKE0B_1 MCKE1B_1 BA31 TP_MEM_B_CKE<3>
23 PP1V05_S0_MCP_PLL_CORE
23 16 8 =PP1V8R1V5_S0_MCP_MEM
87 mA (A01) 17 mA T27 +V_PLL_XREF_XS
1
12 mA U28 +V_PLL_DP
R1610 19 mA U27 +V_PLL_CORE
40.2 MRESET0# AY32 MCP_MEM_RESET_L
OUT 29
1% 39 mA T28 +V_VPLL
1/16W TP or NC for DDR2.
MF-LF
402
2
71 MCP_MEM_COMP_VDD AN41 MEM_COMP_VDD

71 MCP_MEM_COMP_GND AM41 MEM_COMP_GND =PP1V8R1V5_S0_MCP_MEM 8 16 23
1
+VDD_MEM1 AM17 4771 mA (A01, DDR3)
R1611 +VDD_MEM2 AM19
C 40.2
1%
1/16W
AA22
AP12
GND1
GND2
+VDD_MEM3
+VDD_MEM4
AM21
AM23
C
MF-LF
402
2 G30 GND3 +VDD_MEM5 AM25
P10 GND4 +VDD_MEM6 AM27
T10 GND5 +VDD_MEM7 AM29
T6 GND6 +VDD_MEM8 AN16
V10 GND7 +VDD_MEM9 BC29
V34 GND8 +VDD_MEM10 AN20
W5 GND9 +VDD_MEM11 AN24
AA39 GND10 +VDD_MEM12 AT17
AB22 GND11 +VDD_MEM13 AP16
AB7 GND12 +VDD_MEM14 AN22
AD22 GND13 +VDD_MEM15 AP20
AE20 GND14 +VDD_MEM16 AP24
AF24 GND15 +VDD_MEM17 AV16
AG24 GND16 +VDD_MEM18 AR16
AH35 GND17 +VDD_MEM19 AR20
AK7 GND18 +VDD_MEM20 AR24
AM28 GND19 +VDD_MEM21 AW15
AT25 GND20 +VDD_MEM22 AP22
AP30 GND21 +VDD_MEM23 AP18
AR36 GND22 +VDD_MEM24 AU16
AU10 GND23 +VDD_MEM25 AN18
F28 GND24 +VDD_MEM26 AU24
BC21 GND25 +VDD_MEM27 AT21
AY9 GND26 +VDD_MEM28 AY29
B BC9
D34
GND27
GND28
+VDD_MEM29
+VDD_MEM30
AV24
AU20
B
F24 GND29 +VDD_MEM31 AU22
G32 GND30 +VDD_MEM32 AW27
H31 GND31 +VDD_MEM33 BC17
K7 GND32 +VDD_MEM34 AV20
M38 GND33 +VDD_MEM35 AY17
M6 GND35 +VDD_MEM37 AM15
M7 GND36 +VDD_MEM38 AU18
N39 GND38 +VDD_MEM40 AY26
N8 GND39 +VDD_MEM41 AW19
P33 GND40 +VDD_MEM42 AW24
P34 GND41 +VDD_MEM43 BC25
P37 GND42 +VDD_MEM44 AL30
P4 GND43 +VDD_MEM45 AM31
P40 GND44
P7 GND45 GND55 T33
R36 GND46 GND56 T34
R40 GND47 GND57 T35
R43 GND48 GND58 T37
R5 GND49 GND59 T38
T18 GND50 GND60 T7
T20 GND51 GND61 T9
AK11 GND52 GND62 U18
A T24
T26
GND53
GND54
GND63
GND64
U20
U22
PAGE TITLE
MCP Memory Misc

DRAWING NUMBER SIZE

REVISION
R
C.0.0
16 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
9 IN =PEG_D2R_P<0> F7 PE0_RX0_P PE0_TX0_P C5 =PEG_R2D_C_P<0>

OUT 9
9 IN =PEG_D2R_N<0> E7 PE0_RX0_N PE0_TX0_N D4 =PEG_R2D_C_N<0> OUT 9
9 IN =PEG_D2R_P<1> D7
PE0_RX1_P PE0_TX1_P C4 =PEG_R2D_C_P<1>
OUT 9
9 IN =PEG_D2R_N<1> C7 PE0_RX1_N PE0_TX1_N B4 =PEG_R2D_C_N<1> OUT 9
9 IN =PEG_D2R_P<2> E6 PE0_RX2_P PE0_TX2_P A4 =PEG_R2D_C_P<2> OUT 9
9 IN =PEG_D2R_N<2> F6 PE0_RX2_N PE0_TX2_N A3 =PEG_R2D_C_N<2> OUT 9
9 =PEG_D2R_P<3> E5 PE0_RX3_P PE0_TX3_P B3 =PEG_R2D_C_P<3> 9
D 9
IN
IN =PEG_D2R_N<3> F5 PE0_RX3_N PE0_TX3_N B2 =PEG_R2D_C_N<3>
OUT
OUT 9 D
9 IN =PEG_D2R_P<4> E4 PE0_RX4_P PE0_TX4_P C1 =PEG_R2D_C_P<4> OUT 9
9 IN =PEG_D2R_N<4> E3 PE0_RX4_N PE0_TX4_N D1 =PEG_R2D_C_N<4>

OUT 9
9 IN =PEG_D2R_P<5> C3 PE0_RX5_P PE0_TX5_P D2 =PEG_R2D_C_P<5> OUT 9
9 IN =PEG_D2R_N<5> D3 PE0_RX5_N PE0_TX5_N E1 =PEG_R2D_C_N<5>

OUT 9
9 IN =PEG_D2R_P<6> G5 PE0_RX6_P PE0_TX6_P E2 =PEG_R2D_C_P<6>

OUT 9
9 IN =PEG_D2R_N<6> H5 PE0_RX6_N PE0_TX6_N F2 =PEG_R2D_C_N<6> OUT 9
9 IN =PEG_D2R_P<7> J7 PE0_RX7_P PE0_TX7_P F3 =PEG_R2D_C_P<7> OUT 9
PCI EXPRESS
9 IN =PEG_D2R_N<7> J6 PE0_RX7_N PE0_TX7_N F4 =PEG_R2D_C_N<7> OUT 9
9 IN =PEG_D2R_P<8> J5 PE0_RX8_P PE0_TX8_P G3 =PEG_R2D_C_P<8> OUT 9
9 IN =PEG_D2R_N<8> J4 PE0_RX8_N PE0_TX8_N H4 =PEG_R2D_C_N<8> OUT 9
9 IN =PEG_D2R_P<9> L11 PE0_RX9_P PE0_TX9_P H3 =PEG_R2D_C_P<9> OUT 9
9 IN =PEG_D2R_N<9> L10 PE0_RX9_N PE0_TX9_N H2 =PEG_R2D_C_N<9> OUT 9
9 IN =PEG_D2R_P<10> L9 PE0_RX10_P PE0_TX10_P H1 =PEG_R2D_C_P<10> OUT 9
9 IN =PEG_D2R_N<10> L8 PE0_RX10_N PE0_TX10_N J1 =PEG_R2D_C_N<10> OUT 9
9 IN =PEG_D2R_P<11> L7 PE0_RX11_P PE0_TX11_P J2 =PEG_R2D_C_P<11>

OUT 9
9 IN =PEG_D2R_N<11> L6 PE0_RX11_N PE0_TX11_N J3 =PEG_R2D_C_N<11> OUT 9
9 IN =PEG_D2R_P<12> N11 PE0_RX12_P PE0_TX12_P K2 =PEG_R2D_C_P<12> OUT 9
9 IN =PEG_D2R_N<12> N10 PE0_RX12_N PE0_TX12_N K3 =PEG_R2D_C_N<12> OUT 9
9 IN =PEG_D2R_P<13> N9 PE0_RX13_P PE0_TX13_P L4 =PEG_R2D_C_P<13>

OUT 9
9 IN =PEG_D2R_N<13> P9 PE0_RX13_N PE0_TX13_N L3 =PEG_R2D_C_N<13> OUT 9
9 IN =PEG_D2R_P<14> N7 PE0_RX14_P PE0_TX14_P M4 =PEG_R2D_C_P<14> OUT 9
9 IN =PEG_D2R_N<14> N6 PE0_RX14_N PE0_TX14_N M3 =PEG_R2D_C_N<14> OUT 9
9 IN =PEG_D2R_P<15> N5 PE0_RX15_P PE0_TX15_P M2 =PEG_R2D_C_P<15>

OUT 9
9 IN =PEG_D2R_N<15> N4 PE0_RX15_N PE0_TX15_N M1 =PEG_R2D_C_N<15> OUT 9
C 9 IN PEG_PRSNT_L C9
Int PU
PE0_PRSNT_16#
PE0_REFCLK_P
PE0_REFCLK_N
E11
D11
PEG_CLK100M_P
PEG_CLK100M_N
OUT
OUT
9
9
C
Int PU
30 IN MINI_CLKREQ_L D5 PEB_CLKREQ#/GPIO_49 PE1_REFCLK_P G11 PCIE_CLK100M_MINI_P OUT 30 72
30 IN PCIE_MINI_PRSNT_L D9 PEB_PRSNT# Int PU PE1_REFCLK_N F11 PCIE_CLK100M_MINI_N OUT 30 72
Int PU
9 IN FW_CLKREQ_L E8 PEC_CLKREQ#/GPIO_50 PE2_REFCLK_P J11 PCIE_CLK100M_FW_P OUT 9
9 IN PCIE_FW_PRSNT_L C10 PEC_PRSNT# Int PU PE2_REFCLK_N J10 PCIE_CLK100M_FW_N OUT 9
Int PU
9 IN EXCARD_CLKREQ_L M15 PED_CLKREQ#/GPIO_51 PE3_REFCLK_P G13 PCIE_CLK100M_EXCARD_P
OUT 9
9 IN PCIE_EXCARD_PRSNT_L B10 PED_PRSNT# Int PU PE3_REFCLK_N F13 PCIE_CLK100M_EXCARD_N

OUT 9
Int PU
TP_PE4_CLKREQ_L L16 PEE_CLKREQ#/GPIO_16 PE4_REFCLK_P J13 TP_PCIE_CLK100M_PE4P
TP_PE4_PRSNT_L L18 PEE_PRSNT#/GPIO_46 PE4_REFCLK_N H13 TP_PCIE_CLK100M_PE4N
Int PU
Int PU
54 AUD_IP_PERIPHERAL_DET M16 PEF_CLKREQ#/GPIO_17 PE5_REFCLK_P L14 TP_PCIE_CLK100M_PE5P
9 OUT GMUX_JTAG_TCK_L M18 PEF_PRSNT#/GPIO_47 PE5_REFCLK_N K14 TP_PCIE_CLK100M_PE5N
Int PU
Int PU
9 OUT CARDREADER_RESET M17 PEG_CLKREQ#/GPIO_18 PE6_REFCLK_P N14 TP_PCIE_CLK100M_PE6P
9 IN GMUX_JTAG_TDO M19 PEG_PRSNT#/GPIO_48 PE6_REFCLK_N M14 TP_PCIE_CLK100M_PE6N
Int PU
30 7 IN PCIE_WAKE_L F17 PE_WAKE# Int PU (S5) PEX_RST0# K11 PCIE_RESET_L

OUT 25
72 30 IN PCIE_MINI_D2R_P K9 PE1_RX0_P PE1_TX0_P D8 PCIE_MINI_R2D_C_P

OUT 30 72
72 30 IN PCIE_MINI_D2R_N J9 PE1_RX0_N PE1_TX0_N C8 PCIE_MINI_R2D_C_N OUT 30 72
72 9 IN PCIE_FW_D2R_P H9 PE1_RX1_P PE1_TX1_P B8 PCIE_FW_R2D_C_P

OUT 9 72
B 72 9 IN PCIE_FW_D2R_N G9 PE1_RX1_N PE1_TX1_N A8 PCIE_FW_R2D_C_N OUT 9 72

B
9 IN PCIE_EXCARD_D2R_P F9 PE1_RX2_P PE1_TX2_P A7 PCIE_EXCARD_R2D_C_P
OUT 9
9 IN PCIE_EXCARD_D2R_N E9 PE1_RX2_N PE1_TX2_N B7 PCIE_EXCARD_R2D_C_N

OUT 9
TP_PCIE_PE4_D2RP H7 PE1_RX3_P PE1_TX3_P B6 TP_PCIE_PE4_R2D_CP

TP_PCIE_PE4_D2RN G7
PE1_RX3_N PE1_TX3_N C6 TP_PCIE_PE4_R2D_CN
8 =PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_AVDD0 8
57 mA (A01, DVDD0 & 1) T17 +DVDD0_PEX1 +AVDD0_PEX1 Y12 206 mA (A01, AVDD0 & 1)
W19 +DVDD0_PEX2 +AVDD0_PEX2 AA12
U17 +DVDD0_PEX3 +AVDD0_PEX3 AB12
V19 +DVDD0_PEX4 +AVDD0_PEX4 M12
W16 +DVDD0_PEX5 +AVDD0_PEX5 P12
W17 +DVDD0_PEX6 +AVDD0_PEX6 R12
W18 +DVDD0_PEX7 +AVDD0_PEX7 N12
U16 +DVDD0_PEX8 +AVDD0_PEX8 T12
8 =PP1V05_S0_MCP_PEX_DVDD1 +AVDD0_PEX9 U12
T19 +DVDD1_PEX1 +AVDD0_PEX10 AC12
U19 +DVDD1_PEX2 +AVDD0_PEX11 AD12
+AVDD0_PEX12 V12
+AVDD0_PEX13 W12
23 PP1V05_S0_MCP_PLL_PEX T16 +V_PLL_PEX =PP1V05_S0_MCP_PEX_AVDD1 8
84 mA (A01) +AVDD1_PEX1 M13
+AVDD1_PEX2 N13
72 MCP_PEX_CLK_COMP A11 PEX_CLK_COMP +AVDD1_PEX3 P13
NO STUFF
A 1
R1710
2.37K
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. SYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009 A
1% If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
PAGE TITLE
2
1/16W
MF-LF
402
MCP PCIe Interfaces
DRAWING NUMBER SIZE
PLACEMENT_NOTE=Place within 12.7mm of U1400

REVISION
R
C.0.0
17 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11) =PP3V3_ENET_MCP_RMGT 8 18 23
+3.3V_DUAL_RMGT1 J24 83 mA (A01)

+3.3V_DUAL_RMGT2 K24
LAN
D +V_DUAL_RMGT1 U23
=PP1V05_ENET_MCP_RMGT 8 23
131 mA (A01)
+V_DUAL_RMGT2 V23
74 31 IN ENET_RXD<0> C23 RGMII_RXD0 Network Interface Select

74 31 IN ENET_RXD<1> B23 RGMII_RXD1 MII_VREF E28 MCP_MII_VREF IN 23
74 31 IN ENET_RXD<2> E24 RGMII_RXD2 Interface ENET_TXD<0>

RGMII_TXD0 B24 ENET_TXD<0> OUT 31 74
74 31 IN ENET_RXD<3> A24 RGMII_RXD3
RGMII_TXD1 C24 ENET_TXD<1>
OUT 31 74
RGMII 1
74 31 IN ENET_CLK125M_RXCLK A23 RGMII_RXC/MII_RXCLK RGMII_TXD2 C25 ENET_TXD<2>
OUT 31 74
74 31 IN ENET_RX_CTRL C22 RGMII_RXCTL/MII_RXDV RGMII_TXD3 D25 ENET_TXD<3>

OUT 31 74
MII 0
9 IN =MCP_MII_RXER F23 MII_RXER/GPIO_36 RGMII_TXC/MII_TXCLK D24 ENET_CLK125M_TXCLK
OUT 31 74
9 IN =MCP_MII_COL B26 MII_COL/GPIO_20/MSMB_DATA RGMII_TXCTL/MII_TXEN C26 ENET_TX_CTRL OUT 31 74 NOTE: All Apple products set strap to
23 18 8 =PP3V3_ENET_MCP_RMGT
9 IN =MCP_MII_CRS B22 MII_CRS/GPIO_21/MSMB_CLK MII, RGMII products will enable
RGMII_MDC D21 ENET_MDC OUT 31 74
1
feature via software. This
R1810 TP_ENET_INTR_L J22 RGMII_INTR/GPIO_35 RGMII_MDIO C21 ENET_MDIO BI 31 74
avoids a leakage issue since
49.9
1% 23 PP1V05_ENET_MCP_PLL_MAC RGMII_PWRDWN/GPIO_37 G23 TP_ENET_PWRDWN_L MCP79 requires a S5 pull-up.
1/16W
MF-LF 5 mA (A01) T23 +V_DUAL_MACPLL
402
2
BUF_25MHZ E23 MCP_CLK25M_BUF0_R
OUT 32 74 =PP3V3_S0_MCP_GPIO 8 19 21
74 MCP_MII_COMP_VDD C27 MII_COMP_VDD
74 MCP_MII_COMP_GND B27 MII_COMP_GND MII_RESET# J23 ENET_RESET_L
OUT 31 74
1 1
PP3V3_S0_MCP_DAC 24
R1860 R1861
1
100K 100K
R1811 +V_RGB_DAC J32 103 mA 206 mA (A01) 5% 5%
49.9 1/16W 1/16W
1% +V_TV_DAC K32 103 mA MF-LF MF-LF
1/16W TP_MCP_RGB_DAC_RSET C39 RGB_DAC_RSET 402
2 2
402
MF-LF
402
2
TP_MCP_RGB_DAC_VREF B38 RGB_DAC_VREF
DDC_CLK0 B31 MCP_DDC_CLK0
DDC_DATA0 A31 MCP_DDC_DATA0
DACS
C RGB DAC Disable:
C
RGB_DAC_RED B39 TP_MCP_RGB_RED
RGB_DAC_GREEN A39 TP_MCP_RGB_GREEN Okay to float all RGB_DAC signals.

9 OUT MCP_TV_DAC_RSET E36 TV_DAC_RSET
RGB_DAC_BLUE B40 TP_MCP_RGB_BLUE DDC_CLK0/DDC_DATA0 pull-ups still required.
RGB ONLY
9 OUT MCP_TV_DAC_VREF A35 TV_DAC_VREF
RGB_DAC_HSYNC A40 TP_MCP_RGB_HSYNC
RGB_DAC_VSYNC A41 TP_MCP_RGB_VSYNC
TV / Component
TV DAC Disable:
20 8 =PP3V3_S5_MCP_GPIO C / Pr TV_DAC_RED A36 CRT_IG_R_C_PR
OUT 9
Y / Y TV_DAC_GREEN B36 CRT_IG_G_Y_Y

OUT 9 Okay to float all TV_DAC signals.
1
9 IN MCP_CLK27M_XTALIN C38 XTALIN_TV
R1820 Comp / Pb TV_DAC_BLUE C36 CRT_IG_B_COMP_PB
OUT 9 Okay to float XTALIN_TV and XTALOUT_TV.
9 OUT MCP_CLK27M_XTALOUT D38 XTALOUT_TV
47K DDC_CLK0/DDC_DATA0 pull-ups still required.
5% TV_DAC_HSYNC/GPIO_44 D36 CRT_IG_HSYNC OUT 9
1/16W
MF-LF TV_DAC_VSYNC/GPIO_45 C37 CRT_IG_VSYNC OUT 9
402
2
38 BI LPCPLUS_GPIO E16
GPIO_6/FERR*/IGPU_GPIO_6 IFPA_TXC_P B35 LVDS_IG_A_CLK_P
OUT 65 72
66 IN DP_IG_CA_DET B15 GPIO_7/NFERR*/IGPU_GPIO_7 IFPA_TXC_N C35 LVDS_IG_A_CLK_N

OUT 65 72
(See below) IFPA_TXD0_P B32 LVDS_IG_A_DATA_P<0> OUT 7 65 72

69 68 OUT LVDS_IG_BKL_PWM G39 LCD_BKL_CTL/GPIO_57
IFPA_TXD0_N A32 LVDS_IG_A_DATA_N<0> OUT 7 65 72
Interface Mode 69 OUT LVDS_IG_BKL_ON E37 LCD_BKL_ON/GPIO_59
IFPA_TXD1_P D32 LVDS_IG_A_DATA_P<1> OUT 7 65 72
FLAT PANEL
65 OUT LVDS_IG_PANEL_PWR F40 LCD_PANEL_PWR/GPIO_58
MCP Signal TMDS/HDMI DisplayPort IFPA_TXD1_N C32 LVDS_IG_A_DATA_N<1> OUT 7 65 72
IFPA_TXD2_P D33 LVDS_IG_A_DATA_P<2> OUT 7 65 72

=MCP_HDMI_TXC_P/N TMDS_IG_TXC_P/N DP_IG_ML_P/N<3> 66 OUT =MCP_HDMI_TXC_P D35 HDMI_TXC_P/ML0_LANE3_P
IFPA_TXD2_N C33 LVDS_IG_A_DATA_N<2>
OUT 7 65 72
=MCP_HDMI_TXD_P/N<0> TMDS_IG_TXD_P/N<0> DP_IG_ML_P/N<2> 66 OUT =MCP_HDMI_TXC_N E35 HDMI_TXC_N/ML0_LANE3_N
IFPA_TXD3_P B34 LVDS_IG_A_DATA_P<3>
OUT 9
=MCP_HDMI_TXD_P/N<1> TMDS_IG_TXD_P/N<1> DP_IG_ML_P/N<1>
66 OUT =MCP_HDMI_TXD_P<0> G35 HDMI_TXD0_P/ML0_LANE2_P IFPA_TXD3_N C34 LVDS_IG_A_DATA_N<3> OUT 9
=MCP_HDMI_TXD_P/N<2> TMDS_IG_TXD_P/N<2> DP_IG_ML_P/N<0>
66 OUT =MCP_HDMI_TXD_N<0> F35
HDMI_TXD0_N/ML0_LANE2_N WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
=MCP_HDMI_DDC_CLK TMDS_IG_DDC_CLK DP_IG_DDC_CLK
66 =MCP_HDMI_TXD_P<1> F33 HDMI_TXD1_P/ML0_LANE1_P
B =MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_DDC_DATA
TMDS_IG_HPD
DP_IG_DDC_DATA
DP_IG_HPD
66
OUT
OUT =MCP_HDMI_TXD_N<1> G33 HDMI_TXD1_N/ML0_LANE1_N
IFPB_TXC_P
IFPB_TXC_N
L31
K31
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
OUT
OUT
9
9
B
66 OUT =MCP_HDMI_TXD_P<2> J33 HDMI_TXD2_P/ML0_LANE0_P
DP_IG_AUX_CH_P/N TP_DP_IG_AUX_CHP/N DP_IG_AUX_CH_P/N
66 OUT =MCP_HDMI_TXD_N<2> H33 HDMI_TXD2_N/ML0_LANE0_N IFPB_TXD4_P J29 LVDS_IG_B_DATA_P<0> OUT 9
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. IFPB_TXD4_N H29 LVDS_IG_B_DATA_N<0> OUT 9
NOTE: 20K pull-down required on DP_HPD_DET. 72 66 OUT DP_IG_AUX_CH_P D43 DP_AUX_CH0_P IFPB_TXD5_P L29 LVDS_IG_B_DATA_P<1> OUT 9
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. 72 66 OUT DP_IG_AUX_CH_N C43 DP_AUX_CH0_N IFPB_TXD5_N K29 LVDS_IG_B_DATA_N<1> OUT 9
IFPB_TXD6_P L30 LVDS_IG_B_DATA_P<2> OUT 9

NOTE: HDMI port requires level-shifting. IFP interface can (See below)
9 IN =DVI_HPD_GMUX_INT C31 HPLUG_DET2/GPIO_22 IFPB_TXD6_N K30 LVDS_IG_B_DATA_N<2> OUT 9
be used to provide HDMI or dual-channel TMDS without
66 IN =MCP_HDMI_HPD F31 HPLUG_DET3 IFPB_TXD7_P N30 LVDS_IG_B_DATA_P<3>
OUT 9
level-shifters.
IFPB_TXD7_N M30 LVDS_IG_B_DATA_N<3>
OUT 9
LVDS: Power +VDD_IFPx at 1.8V 24 8 =PP3V3R1V8_S0_MCP_IFP_VDD
Dual-channel TMDS: Power +VDD_IFPx at 3.3V 190 mA (A01, 1.8V) M27 +VDD_IFPA
M26 +VDD_IFPB DDC_CLK2/GPIO_23 C30 LVDS_IG_DDC_CLK OUT 7 65
24 PP3V3_S0_MCP_VPLL
DDC_DATA2/GPIO_24 B30 LVDS_IG_DDC_DATA BI 7 65
16 mA (A01) 8 mA M28 +V_PLL_IFPAB
8 mA M29 +V_PLL_HDMI
DDC_CLK3 D31 =MCP_HDMI_DDC_CLK
OUT 66
24 8 =PP1V05_S0_MCP_HDMI_VDD T25 +VDD_HDMI DDC_DATA3 E31 =MCP_HDMI_DDC_DATA BI 66
95 mA (A01)
72 24 OUT MCP_HDMI_RSET J31

HDMI_RSET IFPAB_RSET E32 MCP_IFPAB_RSET OUT 24 72
72 24 OUT MCP_HDMI_VPROBE J30 HDMI_VPROBE IFPAB_VPROBE G31 MCP_IFPAB_VPROBE

OUT 24 72
1
R1850
10K
GPIOs 57-59 (if LCD panel is used): 5%
1/16W
MF-LF
In MCP79 these pins have undocumented internal 402
2
pull-ups (~10K to 3.3V S0). To ensure pins are low
A by default, pull-downs (1K or stronger) must be used.

PAGE TITLE
=DVI_HPD_GMUX_INT:
MCP Ethernet & Graphics
DRAWING NUMBER SIZE
Alias to DVI_HPD for systems using IFP for DVI.
Alias to GMUX_INT for systems with GMUX. REVISION
Alias to HPLUG_DET2 for other systems.
R
C.0.0
Pull-down (20k) required in all cases. NOTICE OF PROPRIETARY PROPERTY: BRANCH
18 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400 21 18 8 =PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
19 MCP_RS232_SOUT_L R1989 8.2K 1 2
(7 OF 11)
5% 1/16W MF-LF 402
73 19 PCI_REQ0_L T2 PCI_REQ0# PCI_GNT0# R3 TP_PCI_GNT0_L

R1990 8.2K
73 19 PCI_REQ0_L 1 2
73 19 PCI_REQ1_L V9 PCI_REQ1#/FANRPM2 PCI_GNT1#/FANCTL2 U10 TP_PCI_GNT1_L 5% 1/16W MF-LF 402
73 19 PCI_REQ1_L R1991 8.2K 1 2
19 OUT FW_PWR_EN T3 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_GNT2#/GPIO_41/RS232_DTR# R4 GMUX_JTAG_TMS OUT 9 5% 1/16W MF-LF 402
19 FW_PWR_EN R1992 8.2K 1 2
54 OUT AUD_IPHS_SWITCH_EN U9 PCI_REQ3#/GPIO_38/RS232_CTS# PCI_GNT3#/GPIO_39/RS232_RTS# U11 GMUX_JTAG_TDI
OUT 9
R1994 8.2K
5% 1/16W MF-LF 402
19 MCP_RS232_SIN_L 1 2
19 IN MCP_RS232_SIN_L T4 PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT4#/GPIO_53/RS232_SOUT# P3 MCP_RS232_SOUT_L
OUT 19 5% 1/16W MF-LF 402
D 73 13 BI MCP_DEBUG<0> AC3 PCI_AD0 PCI_CBE0# AA3 TP_PCI_C_BE_L<0>

D
73 13 BI MCP_DEBUG<1> AE10
PCI_AD1 PCI_CBE1# AA6 TP_PCI_C_BE_L<1>
73 13 BI MCP_DEBUG<2> AC4 PCI_AD2 PCI_CBE2# AA11 TP_PCI_C_BE_L<2>
73 13 BI MCP_DEBUG<3> AE11 PCI_AD3 PCI_CBE3# W10 TP_PCI_C_BE_L<3>
73 13 BI MCP_DEBUG<4> AB3 PCI_AD4

73 13 BI MCP_DEBUG<5> AC6 PCI_AD5 PCI_DEVSEL# AA9 TP_PCI_DEVSEL_L
73 13 BI MCP_DEBUG<6> AB2 PCI_AD6 PCI_FRAME# Y4 TP_PCI_FRAME_L
73 13 BI MCP_DEBUG<7> AC7 PCI_AD7 PCI_IRDY# AA10 TP_PCI_IRDY_L

TP_PCI_AD<8> AC8 PCI_AD8 PCI_PAR Y1 TP_PCI_PAR
TP_PCI_AD<9> AA2 PCI_AD9 PCI_PERR#/GPIO_43/RS232_DCD# AB9 TP_PCI_PERR_L

TP_PCI_AD<10> AC9 PCI_AD10 PCI_SERR# AA7 TP_PCI_SERR_L
TP_PCI_AD<11> AC10 PCI_AD11 PCI_STOP# Y2 TP_PCI_STOP_L
PCI
TP_PCI_AD<12> AC11 PCI_AD12
PCI_PME#/GPIO_30 T1 PM_LATRIGGER_L OUT 13
TP_PCI_AD<13> AA1 PCI_AD13
Int PU (S5)
TP_PCI_AD<14> AA5
PCI_AD14
TP_PCI_AD<15> Y5 PCI_AD15
TP_PCI_AD<16> W3 PCI_AD16 PCI_RESET0# R10 MEM_VTT_EN_R
OUT 25
TP_PCI_AD<17> W6 PCI_AD17 PCI_RESET1# R11 TP_PCI_RESET1_L

TP_PCI_AD<18> W4 PCI_AD18
TP_PCI_AD<20> V3 PCI_AD20
PCI_CLK0 R6 TP_PCI_CLK0
PCI_CLK1 R7 TP_PCI_CLK1
TP_PCI_AD<22> V2 PCI_AD22
PCI_CLK2 R8 73 PCI_CLK33M_MCP_R
TP_PCI_AD<24> U3 PCI_AD24 1
TP_PCI_AD<25> W11 PCI_AD25 R1910
C TP_PCI_AD<26> U2 PCI_AD26
22
5%
1/16W
C
TP_PCI_AD<27> U5
PCI_AD27 MF-LF
402
2
TP_PCI_AD<28> U1 PCI_AD28
PLACEMENT_NOTE=Place close to pin R8
TP_PCI_AD<29> U6 PCI_AD29 PCI_CLKIN R9 73 PCI_CLK33M_MCP
TP_PCI_AD<30> T5 PCI_AD30
TP_PCI_AD<31> U7 PCI_AD31
TP_PCI_INTW_L P2 PCI_INTW#
TP_PCI_INTX_L N3 PCI_INTX#
LPC_FRAME# AD4 LPC_FRAME_R_L R1960 22 1 2 LPC_FRAME_L
OUT 36 38 73
TP_PCI_INTY_L N2 PCI_INTY# 5% 1/16W MF-LF 402
LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12 LPC_PWRDWN_L
OUT 36 38
TP_PCI_INTZ_L N1 PCI_INTZ#
LPC_RESET0# AE5 LPC_RESET_L OUT 25 73
LPC
TP_PCI_TRDY_L Y3 PCI_TRDY#
LPC_AD0 AD3 LPC_AD_R<0> R1950 22 1 2 LPC_AD<0> BI 36 38 73
5% 1/16W MF-LF 402
38 36 PM_CLKRUN_L AD11
PCI_CLKRUN#/GPIO_42 LPC_AD1 AD2 LPC_AD_R<1> R1951 22 1 2 LPC_AD<1> 36 38 73
IN BI
5% 1/16W MF-LF 402
LPC_AD2 AD1 LPC_AD_R<2> R1952 22 1 2 LPC_AD<2>
BI 36 38 73
5% 1/16W MF-LF 402
9 IN FW_PME_L AE2 LPC_DRQ1#/GPIO_19 Int PU LPC_AD3 AD5 LPC_AD_R<3> R1953 22 1 2 LPC_AD<3>
BI 36 38 73
5% 1/16W MF-LF 402
TP_LPC_DRQ0_L AE1 LPC_DRQ0# Int PU
38 36 BI LPC_SERIRQ AE6 LPC_SERIRQ Int PU LPC_CLK0 AE9 LPC_CLK33M_SMC_R OUT 25 73
1
R1961
U24 GND65 GND98 Y26
10K
U26 GND66 GND99 Y27 5%
1/16W
U39 GND67 GND100 AB18 MF-LF
402
2
U4 GND68 GND101 H34
U8 GND69 GND102 AB20 Strap for Boot ROM Selection (See HDA_SDOUT)
V16 GND70 GND103 AB21
B V17 GND71 GND104 AB23 B


GND
V4 GND81 GND114 AC22
W20 GND84 GND117 AB33
W22 GND85 GND118 AC5
W24 GND86 GND119 AD16
Y16 GND90 GND123 AD20
Y22
GND95 GND128 AD28
A Y24
Y25
GND96
GND97
GND129
GND130
AD33
AD34 SYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009 A

PAGE TITLE
MCP PCI & LPC

DRAWING NUMBER SIZE

REVISION
R
C.0.0
19 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11)
External A
72 34 OUT SATA_HDD_R2D_C_P AJ7 SATA_A0_TX_P USB0_P C29 USB_EXTA_P BI 35 73
72 34 OUT SATA_HDD_R2D_C_N AJ6

SATA_A0_TX_N USB0_N D29 USB_EXTA_N
BI 35 73
AirPort (PCIe Mini-Card)

72 34 IN SATA_HDD_D2R_N AJ5 SATA_A0_RX_N USB1_P C28 USB_MINI_P BI 9
72 34 IN SATA_HDD_D2R_P AJ4 SATA_A0_RX_P USB1_N D28 USB_MINI_N BI 9
External D
D USB2_P A28 USB_EXTD_P BI 9 D

USB2_N B28 USB_EXTD_N BI 9
72 34 OUT SATA_ODD_R2D_C_P AJ11 SATA_A1_TX_P Camera

72 34 OUT SATA_ODD_R2D_C_N AJ10 SATA_A1_TX_N USB3_P F29 USB_CAMERA_P BI 65 73
USB3_N G29 USB_CAMERA_N

BI 65 73
72 34 IN SATA_ODD_D2R_N AJ9 SATA_A1_RX_N IR

72 34 IN SATA_ODD_D2R_P AK9 SATA_A1_RX_P USB4_P K27 USB_IR_P BI 9 73
USB4_N L27 USB_IR_N BI 9 73
Geyser Trackpad/Keyboard
USB5_P J26 USB_TPAD_P BI 44 73
TP_SATA_C_R2D_CP AK2 SATA_B0_TX_P USB5_N J27 USB_TPAD_N

BI 44 73
TP_SATA_C_R2D_CN AJ3 SATA_B0_TX_N Bluetooth

USB6_P F27 USB_BT_P BI 30 73
TP_SATA_C_D2RN AJ2 SATA_B0_RX_N USB6_N G27 USB_BT_N BI 30 73
TP_SATA_C_D2RP AJ1 SATA_B0_RX_P External B
SATA
USB7_P D27 USB_EXTB_P
USB
BI 35 73
USB7_N E27 USB_EXTB_N BI 35 73
ExpressCard
TP_SATA_D_R2D_CP AM4 SATA_B1_TX_P USB8_P K25 USB_EXCARD_P BI 9 =PP3V3_S5_MCP_GPIO 8 18
TP_SATA_D_R2D_CN AL3 SATA_B1_TX_N USB8_N L25 USB_EXCARD_N

BI 9
External C
1 1
TP_SATA_D_D2RN AL4 SATA_B1_RX_N USB9_P H25 USB_EXTC_P
BI 9 R2051 R2053
TP_SATA_D_D2RP AK3 SATA_B1_RX_P USB9_N J25 USB_EXTC_N
BI 9 8.2K 8.2K
5% 5%
1/16W 1/16W
MF-LF MF-LF
USB10_P F25 TP_USB_10P
2
402
2
402
USB10_N G25 TP_USB_10N
C TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
AN1
AM1
SATA_C0_TX_P
SATA_C0_TX_N USB11_P K23 USB_CARDREADER_P
BI 9 73
R2050
8.2K
1
R2052
8.2K
1
C
USB11_N L23 USB_CARDREADER_N
BI 9 73 5% 5%
1/16W 1/16W
TP_SATA_E_D2RN AM2 SATA_C0_RX_N MF-LF MF-LF
402 402
2 2
TP_SATA_E_D2RP AM3 SATA_C0_RX_P
USB_OC0#/GPIO_25 L21 USB_EXTA_OC_L IN 35
USB_OC1#/GPIO_26 K21 USB_EXTB_OC_L IN 35
USB_OC2#/GPIO_27/MGPIO J21 USB_EXTC_OC_L IN

TP_SATA_F_R2D_CP AP3
SATA_C1_TX_P USB_OC3#/GPIO_28/MGPIO H21 EXCARD_OC_L
IN 37
TP_SATA_F_R2D_CN AP2 SATA_C1_TX_N
+V_PLL_USB L28 PP3V3_S0_MCP_PLL_USB 23

TP_SATA_F_D2RN AN3 SATA_C1_RX_N
19 mA (A01)
TP_SATA_F_D2RP AN2 SATA_C1_RX_P
USB_RBIAS_GND A27 73 MCP_USB_RBIAS_GND
1
R2060
TP_MCP_SATALED_L E12 SATA_LED# GND131 AD35 806
1%
GND132 AD37 1/16W
MF-LF
GND133 AD38 402
2
23 PP1V05_S0_MCP_PLL_SATA AE16
+V_PLL_SATA
GND134 AE22
84 mA (A01)
GND135 AE24
8 =PP1V05_S0_MCP_SATA_DVDD0
GND136 AE39
43 mA (A01, DVDD0 & 1) AF19 +DVDD0_SATA1
GND137 AE4
AG16 +DVDD0_SATA2
GND138 AD6
AG17 +DVDD0_SATA3
GND139 AF16
AG19 +DVDD0_SATA4
GND140 AF17
8 =PP1V05_S0_MCP_SATA_DVDD1
GND141 AF18
B AH17
AH19
+DVDD1_SATA1
+DVDD1_SATA2
GND142 AF20 B
GND143 AF22
8 =PP1V05_S0_MCP_SATA_AVDD0 GND144 AF26
127 mA (A01, AVDD0 & 1) AJ12 +AVDD0_SATA1 GND145 AF27
AN11 +AVDD0_SATA2 GND146 AF28
AK12 +AVDD0_SATA3 GND147 AF33
AK13 +AVDD0_SATA4 GND148 AF34
AL12 +AVDD0_SATA5 GND149 AF37
AM11 +AVDD0_SATA6 GND150 AF40
AM12 +AVDD0_SATA7 GND151 AG18
AN12 +AVDD0_SATA8 GND152 AG20
AL13
+AVDD0_SATA9 GND153 AG22
8 =PP1V05_S0_MCP_SATA_AVDD1 GND154 AG26
AN14 +AVDD1_SATA1 GND155 AG36
AL14 +AVDD1_SATA2 GND156 AG40
AM13 +AVDD1_SATA3 GND157 AH18
AM14 +AVDD1_SATA4 GND158 AH20
GND159 AH22
72 MCP_SATA_TERMP AE3 SATA_TERMP GND160 AH24
1
R2010
2.49K
1% If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
1/16W
MF-LF If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
402
2
PAGE TITLE
MCP SATA & USB

DRAWING NUMBER SIZE

REVISION
R
C.0.0
20 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
=PP3V3R1V5_S0_MCP_HDA 8 21 23
MCP79-TOPO-B
BGA 7 mA (A01)
(9 OF 11)
1
+V_DUAL_HDA1 J16
R2160
+V_DUAL_HDA2 K16 8.2K
5%
D
1/16W
HDA
D 2
MF-LF
402
R2170
22
73 49 IN HDA_SDIN0 G15
HDA_SDATA_IN0 HDA_SDATA_OUT F15 73 21 HDA_SDOUT_R 1 2 HDA_SDOUT
OUT 49 73
Int PD 5%
1/16W
MF-LF
BIOS Boot Select
R2171 402
22
TP_MLB_RAM_SIZE J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK HDA_BITCLK E15 73 21 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK
OUT 49 73 I/F HDA_SDOUT LPC_FRAME#
Int PD 5%
1/16W
MF-LF
R2172 LPC 0 0
402
22
TP_MLB_RAM_VENDOR J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA HDA_RESET* K15 73 21 HDA_RST_R_L 1 2 HDA_RST_L OUT 49 73
23 21 8 =PP3V3R1V5_S0_MCP_HDA PCI 0 1
(MXM_OK for MXM systems) Int PD 5%
1/16W
MF-LF
1 R2173 402 SPI0 1 0
R2110 22
49.9 HDA_SYNC L15 73 21 HDA_SYNC_R 1 2 HDA_SYNC OUT 49 73
1%
1/16W 5% SPI1 1 1
MF-LF 1/16W
402 MF-LF
2 402
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
73 MCP_HDA_PULLDN_COMP A15 HDA_PULLDN_COMP HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK K17 MCP_GPIO_4 9 21
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA L17 AUD_I2C_INT_L

IN 21 54 R1961 and R2160 selects SPI0 ROM by
23 PP1V05_S0_MCP_PLL_NV default, LPC+ debug card pulls
37 mA (A01) 20 mA AE18 +V_PLL_NV_H SLP_S3* G17 PM_SLP_S3_L OUT 7 32 36 63 67 LPC_FRAME# high for SPI1 ROM override.
17 mA AE17 +V_PLL_SP_SPREF SLP_RMGT* J17 PM_SLP_RMGT_L
OUT 9
NOTE: MCP79 does not support FWH, only
SLP_S5* H17 PM_SLP_S4_L OUT 7 36 37 63
LPC ROMs. So Apple designs will
25 22 7 PP3V3_G3_RTC not use LPC for BootROM override.
38 OUT =SPI_CS1_R_L_USE_MLB L24 GPIO_1/PWRDN_OK/SPI_CS1
THERM_DIODE_P B11 MCP_THMDIODE_P
OUT 42 76
37 36 32 SMC_ADAPTER_EN L26 GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L NOTE: MCP79 rev A01 does not support
IN
THERM_DIODE_N C11 MCP_THMDIODE_N OUT 42 76
=PP3V3_S0_MCP 8 22 23 SPI1 option. Rev B01 will.
1 1
R2120 R2121 TP_SB_A20GATE K13 A20GATE Int PU BOOT_MODE_SAFE
C 49.9K
1/16W
1%
49.9K
1%
1/16W
TP_MCP_KBDRSTIN_L L13 KBRDRSTIN* Int PU MCP_VID0/GPIO_13 L20 MCP_VID<0> OUT 21 60 1
R2180 C
MF-LF MF-LF 36 IN SMC_WAKE_SCI_L C19
SIO_PME* Int PU (S5) MCP_VID1/GPIO_14 M20 MCP_VID<1>
OUT 21 60 10K BUF_SIO_CLK Frequency
402 402 5%
2 2
36 IN SMC_RUNTIME_SCI_L C18 EXT_SMI/GPIO_32* Int PU (S5) MCP_VID2/GPIO_15 M21 MCP_VID<2>
OUT 21 60 1/16W
MF-LF Frequency
2
402 HDA_SYNC
SM_INTRUDER_L B20 INTRUDER*
SPKR C13 MCP_SPKR
OUT 37
24 MHz 1
BOOT_MODE_USER
TP_MCP_LID_L M25 LID* Int PU (S5)
1
36 PM_BATLOW_L M24 LLB* Int PU (S5) SMB_CLK0 L19 SMBUS_MCP_0_CLK 13 39 73

R2181 14.31818 MHz 0
IN OUT
10K
SMB_DATA0 K19 SMBUS_MCP_0_DATA
BI 13 39 73 5% USER mode: Normal
MISC
1/16W
70 59 IN PM_DPRSLPVR M22 CPU_DPRSLPVR SMB_CLK1/MSMB_CLK G21 SMBUS_MCP_1_CLK OUT 39 73 MF-LF SAFE mode: For ROMSIP
402
2
SMB_DATA1/MSMB_DATA F21 SMBUS_MCP_1_DATA
BI 39 73 recovery
36 IN PM_PWRBTN_L C16 PWRBTN* Int PU (S5) SMB_ALERT*/GPIO_64 M23 AP_PWR_EN OUT 21 30 32 SPI Frequency Select
Connects to SMC for
25 IN PM_SYSRST_DEBOUNCE_L D16 RSTBTN* Int PU
automatic recovery.
Frequency SPI_DO SPI_CLK
(MGPIO2) FANRPM0/GPIO_60 B12 MEM_EVENT_L
IN 21 27 28 36
RTC_RST_L C20
RTC_RST*
FANCTL0/GPIO_61 A12 ODD_PWR_EN_L OUT 34
31 MHz 0 0
(MGPIO3) FANRPM1/GPIO_63 D12 SMC_IG_THROTTLE_L
IN 21 37
36 IN PM_RSMRST_L D20 PWRGD_SB
FANCTL1/GPIO_62 C12 ARB_DETECT 21
25 IN MCP_PS_PWRGD E20 PS_PWRGD 42 MHz 0 1
25 IN MCP_CPU_VLD C17 CPU_VLD CPUVDD_EN D17 MCP_CPUVDD_EN

OUT 25 25 MHz 1 0
13 IN JTAG_MCP_TDI E19 JTAG_TDI Int PU 1 MHz 1 1

SPI_CS0/GPIO_10 C14 SPI_CS0_R_L
OUT 38 73
13 OUT JTAG_MCP_TDO F19 JTAG_TDO
SPI_CLK/GPIO_11 D13 SPI_CLK_R
OUT 38 48 73
13 IN JTAG_MCP_TMS J19 JTAG_TMS Int PU NOTE: Straps not provided on this page.
SPI_DI/GPIO_8 C15 SPI_MISO IN 38 48 73
13 IN JTAG_MCP_TRST_L J18 JTAG_TRST*
SPI_DO/GPIO_9 B14 SPI_MOSI_R
OUT 38 48 73
13 IN JTAG_MCP_TCK G19 JTAG_TCK
B 25 IN MCP_CLK25M_XTALIN A16 XTALIN SUS_CLK/GPIO_34 B18 PM_CLK32K_SUSCLK_R

OUT 25 73
B
25 OUT MCP_CLK25M_XTALOUT B16 XTALOUT BUF_SIO_CLK AE7 TP_MCP_BUF_SIO_CLK
25 IN RTC_CLK32K_XTALIN A19 XTALIN_RTC TEST_MODE_EN K22 MCP_TEST_MODE_EN
25 OUT RTC_CLK32K_XTALOUT B19

XTALOUT_RTC PKG_TEST L22
1 1
R2163 R2190
1 1
R2150 R2151 10K 1K
5% 1%
10K 100K 1/16W 1/16W
5% 5% MF-LF MF-LF
1/16W 1/16W 402 402
2 2
MF-LF MF-LF
402 402
2 2
=PP3V3_S0_MCP_GPIO 8 18 19
=PP3V3_S3_MCP_GPIO 8
HDA Output Caps

1 1 1 1 1
For EMI Reduction on HDA interface

R2140 R2141 R2142 R2143 R2154
10K 10K 10K 10K 100K
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
HDA_SDOUT_R 21 73 402 402 402 402 402
2 2 2 2 2
HDA_BIT_CLK_R 21 73
MCP_GPIO_4 9 21 AP_PWR_EN 21 30 32
HDA_RST_R_L 21 73 AUD_I2C_INT_L 21 54
HDA_SYNC_R 21 73 MEM_EVENT_L 21 27 28 36
SMC_IG_THROTTLE_L 21 37 MCP_VID<0> 21 60
A C2170
10PF
1
C2172
10PF
1
ARB_DETECT 21
MCP_VID<1>
MCP_VID<2>
21 60
21 60
5% 5% PAGE TITLE
50V
CERM
402
2
50V
CERM
402
2
1
R2147
1
R2155
1
R2156
1
R2157
MCP HDA & MISC
DRAWING NUMBER SIZE
100K 22K 22K 22K
1
C2171 1
C2173
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W Apple Inc. 051-7982 D
10PF 10PF
MF-LF MF-LF MF-LF MF-LF REVISION
2
5%
50V
2
5%
50V
2
402
2
402
2
402
2
402 R
C.0.0
CERM
402
CERM
402
21 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(11 OF 11) =PPVCORE_S0_MCP (10 OF 11) =PP1V05_S0_MCP_FSB
23 8 8 14 23
AH26 GND161 GND253 AV40 23065 mA (A01, 1.2V) AA25 +VDD_CORE1 +VTT_CPU1 R32 1139 mA 1182 mA (A01)
AH33 GND162 GND254 BA1 16996 mA (A01, 1.0V) AC23 +VDD_CORE2 +VTT_CPU2 AC32
AH34 GND163 GND255 BA4 U25 +VDD_CORE3 +VTT_CPU3 E40
AH37 GND164 GND256 AW31 AH12 +VDD_CORE4 +VTT_CPU4 J36
AH38 GND165 GND257 AY6 AG10 +VDD_CORE5 +VTT_CPU5 N32
AJ39 GND166 GND258 L35 AG5 +VDD_CORE6 +VTT_CPU6 T32
D AJ8 GND167 GND259 BC33 Y21 +VDD_CORE7 +VTT_CPU7 U32 D

AK10 GND168 GND260 BC37 Y23 +VDD_CORE8 +VTT_CPU8 V32
AK33 GND169 GND261 BC41 AA16 +VDD_CORE9 +VTT_CPU9 W32
AK34 GND170 GND262 AY14 AA26 +VDD_CORE10 +VTT_CPU10 P31
AK37 GND171 GND263 BC5 AA27 +VDD_CORE11 +VTT_CPU11 AF32
AK4 GND172 GND264 C2 AA28 +VDD_CORE12 +VTT_CPU12 AE32
AK40 GND173 GND265 D10 AC16 +VDD_CORE13 +VTT_CPU13 AH32
AL36 GND174 GND266 D14 AC17 +VDD_CORE14 +VTT_CPU14 AJ32
AL40
GND175 GND267 D15 AC18
+VDD_CORE15 +VTT_CPU15 AK31
AL5 GND176 GND268 D18 AC19 +VDD_CORE16 +VTT_CPU16 AK32
AM10 GND177 GND269 D19 AC20 +VDD_CORE17 +VTT_CPU17 AD32
AM16 GND178 GND270 D22 AC21 +VDD_CORE18 +VTT_CPU18 AL31
AM18 GND179 GND271 D23 AA17 +VDD_CORE19 +VTT_CPU19 AB32
AM20 GND180 GND272 D26 AC24 +VDD_CORE20 +VTT_CPU20 B41
AM22 GND181 GND273 D30 AC25 +VDD_CORE21 +VTT_CPU21 B42
AM24 GND182 GND274 D37 AC26 +VDD_CORE22 +VTT_CPU22 C40
AM26 GND183 GND275 D6 AC27 +VDD_CORE23 +VTT_CPU23 C41
AM30 GND184 GND276 E13 AC28 +VDD_CORE24 +VTT_CPU24 C42
AM34 GND185 GND277 E17 AD21 +VDD_CORE25 +VTT_CPU25 D39
AM35 GND186 GND278 E21 AD23 +VDD_CORE26 +VTT_CPU26 D40
AM37 GND187 GND279 E25 W27 +VDD_CORE27 +VTT_CPU27 D41
AM38
GND188 GND280 E29 V25
+VDD_CORE28 +VTT_CPU28 E38
POWER
AM5 GND189 GND281 E33 AA18 +VDD_CORE29 +VTT_CPU29 E39
AM6 GND190 GND282 F12 AE19 +VDD_CORE30 +VTT_CPU30 F37
C AP26
AN28
GND193
GND194
GND285
GND286
F8
G10
AE25
AE26
+VDD_CORE33
+VDD_CORE34
+VTT_CPU33
+VTT_CPU34
G36
G37
C
AN30 GND195 GND287 G12 AE27 +VDD_CORE35 +VTT_CPU35 G38
AN39 GND196 GND288 G14 AE28 +VDD_CORE36 +VTT_CPU36 H35
AN4 GND197 GND289 G16 AF10 +VDD_CORE37 +VTT_CPU37 H37
Y7 GND198 GND290 BC12 AF11 +VDD_CORE38 +VTT_CPU38 J34
AP10 GND199 GND291 G22 AA19 +VDD_CORE39 +VTT_CPU39 J35
AU26 GND200 GND292 G24 AF2 +VDD_CORE40 +VTT_CPU40 K33
AP14
GND201 GND293 AW20 AF21
+VDD_CORE41 +VTT_CPU41 K34
AU14 GND202 GND294 G34 AF23 +VDD_CORE42 +VTT_CPU42 K35
AP28 GND203 GND295 G4 AF25 +VDD_CORE43 +VTT_CPU43 L32

GND
AP36 GND206 GND298 G8 AF7 +VDD_CORE46 +VTT_CPU46 M31
AP37 GND207 GND299 H11 AH23 +VDD_CORE47 +VTT_CPU47 M32
AP4 GND208 GND300 H15 AF9 +VDD_CORE48 +VTT_CPU48 M33
AP40 GND209 GND301 AW35 AA20 +VDD_CORE49 +VTT_CPU49 N31
AP7 GND210 GND302 H23 AG11 +VDD_CORE50 +VTT_CPU50 P32
AW23 GND211 GND303 AN8 AG12 +VDD_CORE51 +VTT_CPU51 Y32
AR28 GND212 GND304 G40 AG21 +VDD_CORE52 +VTT_CPU52 AA32
AR32 GND213 GND305 J12 AG23 +VDD_CORE53

AR40 GND214 GND306 J8 AG25 +VDD_CORE54 +VTT_CPUCLK AG32 43 mA
AT10 GND215 GND307 K10 AG3 +VDD_CORE55
AR12 GND216 GND308 K12 AG4 +VDD_CORE56
AT13 GND217 GND309 K18 AA21 +VDD_CORE57
=PP3V3_S0_MCP 8 21 23
+3.3V_1 AD10 450 mA (A01)
B AT6 GND220 GND312 K4 AG8 +VDD_CORE60
+3.3V_2
+3.3V_3
AE8
AB10
B
+3.3V_4 AD9
AT9 GND222 GND314 K8 AH1 +VDD_CORE62
+3.3V_5 Y10
AY21 GND223 GND315 AU1 AH10 +VDD_CORE63
+3.3V_6 AB11
AY22 GND224 GND316 L40 AH11 +VDD_CORE64
+3.3V_7 AA8
L12 GND225 GND317 L43 W26 +VDD_CORE65
+3.3V_8 Y9
AU12 GND226 GND318 L5 AH2 +VDD_CORE66
AU28 GND227 GND319 M10 AA23 +VDD_CORE67
AP33 GND228 GND320 M34 W28 +VDD_CORE68
AU32 GND229 GND321 M35 AH25 +VDD_CORE69 =PP3V3_S5_MCP 8 23
AR30 GND230 GND322 M37 AH21 +VDD_CORE70 +3.3V_DUAL1 G18 16 mA 266 mA (A01)
AU36
GND231 GND323 Y28 AH3
+VDD_CORE71 +3.3V_DUAL2 H19
AU38 GND232 GND324 Y33 AH4 +VDD_CORE72 +3.3V_DUAL3 J20
AU4 GND233 GND325 Y34 AH5 +VDD_CORE73 +3.3V_DUAL4 K20
G28 GND234 GND326 Y35 AH6 +VDD_CORE74

F20 GND235 GND327 Y37 AH7 +VDD_CORE75 +3.3V_DUAL_USB1 G26 250 mA
AV28 GND236 GND328 Y38 AH9 +VDD_CORE76 +3.3V_DUAL_USB2 H27
AV32 GND237 GND329 AB17 AA24 +VDD_CORE77 +3.3V_DUAL_USB3 J28
AV36 GND238 GND330 AB16 W21 +VDD_CORE78 +3.3V_DUAL_USB4 K28
AV4 GND239 GND331 AN26 W23 +VDD_CORE79

AV7 GND240 GND332 AD7 W25 +VDD_CORE80
AW11 GND241 GND333 M11 AF12 +VDD_CORE81
=PP1V05_S5_MCP_VDD_AUXC 8 23
G20 GND242 GND334 AA4
+VDD_AUXC1 T21 105 mA (A01)
AR43 GND243 GND335 AB19 25 21 7 PP3V3_G3_RTC
+VDD_AUXC2 U21
AW43 GND244 GND336 AY13 10 uA (G3)
A20 +VBAT +VDD_AUXC3 V21
A AY10
AV12
GND245
GND246
GND337
GND338
P11
Y6
80 uA (S0)
AY30 GND247 GND339 T11 PAGE TITLE
AY33 GND248 GND340 V11 MCP Power & Ground
AY34 GND249 GND341 Y11 DRAWING NUMBER SIZE
AY37 GND250 GND342 AH16
AY38 GND251 GND343 T22 REVISION
AY41 GND252
R
C.0.0
22 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP Core Power NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
22 8 =PPVCORE_S0_MCP
23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C2500 C2501 C2502 C2503 C2504 C2505 C2506 C2507 C2508 C2509 C2510 C2511 C2512 C2513
(No IG vs. EG data)
4.7UF 4.7UF 4.7UF 4.7UF 1UF 1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 10% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 2 2 2 2 2 2 2 2 2 2 2 2 2
X5R-1 X5R-1 X5R-1 X5R-1 X5R X5R X5R X5R CERM CERM CERM CERM CERM CERM
402 402 402 402 402-1 402-1 402-1 402-1 402 402 402 402 402 402
D MCP PCIE (DVDD) Power MCP SATA (DVDD) Power

L2570
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) D
30-OHM-5A Apple: 5x 2.2uF 0402 (11 uF)
8 =PP1V05_S0_MCP_PEX_DVDD 8 =PP1V05_S0_MCP_SATA_DVDD 8 =PP1V05_S0_MCP_AVDD_UF PP1V05_S0_MCP_PEX_AVDD 8
1 2
57 mA (A01) 43 mA (A01) 333 mA (A01) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=1.05V
0603
1 1 1 1 1 1 1 1 1 1 1 1
C2515 C2516 C2517 C2518 C2519 C2520 C2521 C2570 C2571 C2572 C2573 C2574
4.7UF 1UF 1UF 0.1uF 0.1uF 4.7UF 0.1uF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 10V 10V 10V 10V 4V 10V 6.3V 6.3V 6.3V 6.3V 6.3V
2 2 2 2 2 2 2 2 2 2 2 2
X5R-1 X5R X5R CERM CERM X5R-1 CERM CERM CERM CERM CERM CERM
402 402-1 402-1 402 402 402 402 402-LF 402-LF 402-LF 402-LF 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

MCP 1.05V AUX Power MCP 1.05V RMGT Power
L2575 Apple: 2x 2.2uF 0402 (4.4 uF)
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_MCP_RMGT 30-OHM-5A PP1V05_S0_MCP_SATA_AVDD
22 8 18 8 8
1 2
105 mA (A01) 131 mA (A01) MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
VOLTAGE=1.05V
0603
1 1 1 1 1 1
C2525 C2526 C2528 C2529 C2575 C2576
0.1uF 0.1uF 4.7UF 0.1uF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
10V 10V 4V 10V 6.3V 6.3V
2 2 2 2 2 2
CERM CERM X5R-1 CERM CERM CERM
402 402 402 402 402-LF 402-LF
MCP FSB (VTT) Power NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
L2580
Apple: 7x 2.2uF 0402 (15.4 uF) 30-OHM-1.7A
22 14 8 =PP1V05_S0_MCP_FSB 62 8 =PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_FSB 14
1 2
1182 mA (A01) 562 mA (A01) MIN_NECK_WIDTH=0.2 MM 270 mA (A01)
VOLTAGE=1.05V
0402
C 1
C2530
2.2UF
1
C2531
2.2UF
1
C2532
2.2UF
1
C2533
2.2UF
1
C2534
2.2UF
1
C2535
2.2UF
1
C2536
2.2UF
C2592
10UF
1
C2580
4.7UF
1 1
C2581
0.1UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 10V
2 2 2 2 2 2 2 2 2 2
CERM CERM CERM CERM CERM CERM CERM X5R X5R-1 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 603 402 402
MCP Memory Power

L2582
=PP1V8R1V5_S0_MCP_MEM 30-OHM-1.7A PP1V05_S0_MCP_PLL_PEX
16 8 17
1 2
4771 mA (A01, DDR3) MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
VOLTAGE=1.05V
0402
1 1 1 1 1 1 1 1 1 1 1 1
C2540 C2541 C2542 C2543 C2544 C2545 C2546 C2547 C2548 C2549 C2582 C2583
4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 10V 10V 10V 10V 10V 10V 10V 10V 10V 4V 10V
2 2 2 2 2 2 2 2 2 2 2 2
X5R-1 CERM CERM CERM CERM CERM CERM CERM CERM CERM X5R-1 CERM
402 402 402 402 402 402 402 402 402 402 402 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) L2584
L2555 Apple: 1x 2.2uF 0402 (2.2 uF) 30-OHM-1.7A
Apple: 4x 2.2uF 0402 (8.8 uF) PP1V05_S0_MCP_PLL_SATA 20
30-OHM-1.7A
22 21 8 =PP3V3_S0_MCP 8 =PP3V3_S0_MCP_PLL_UF PP3V3_S0_MCP_PLL_USB 20 MIN_LINE_WIDTH=0.4 MM
1 2
1 2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
450 mA (A01) 19 mA (A01) MIN_NECK_WIDTH=0.2 MM 19 mA (A01) VOLTAGE=1.05V
0402
VOLTAGE=3.3V
0402
1 1
1 1 1 1 1
C2584 C2585
C2550 C2551 C2552 C2553 C2555 4.7UF 0.1UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 20% 20%
20% 20% 20% 20% 20% 4V 10V
6.3V 6.3V 6.3V 6.3V 6.3V X5R-1 2 2 CERM
2 2 2 2 2
CERM CERM CERM CERM CERM 402 402
402-LF 402-LF 402-LF 402-LF 402-LF
B B
L2586
MCP 3.3V AUX/USB Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Ethernet Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) 30-OHM-1.7A
PP1V05_S0_MCP_PLL_CORE 16
Apple: 1x 2.2uF 0402 (2.2 uF) Apple: 1x 2.2uF 0402 (2.2 uF) MIN_LINE_WIDTH=0.4 MM
=PP3V3_S5_MCP =PP3V3_ENET_MCP_RMGT 1 2
22 8 23 18 8 MIN_NECK_WIDTH=0.2 MM 87 mA (A01)
VOLTAGE=1.05V
0402
266 mA (A01) 83 mA (A01)
1 1 1 1
C2560 C2564 C2586 C2587
2.2UF 2.2UF 4.7UF 0.1UF
20% 20% 20% 20%
6.3V 6.3V 4V 10V
2 2 2 2
CERM CERM X5R-1 CERM
402-LF 402-LF 402 402
L2588
MCP 3.3V/1.5V HDA Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) 30-OHM-1.7A
PP1V05_S0_MCP_PLL_NV 21
Apple: 1x 2.2uF 0402 (2.2 uF) 1 2
21 8 =PP3V3R1V5_S0_MCP_HDA MIN_NECK_WIDTH=0.2 MM 37 mA (A01)
VOLTAGE=1.05V
0402
7 mA (A01)
1 1 1 1
C2562 C2588 C2589 C2590
2.2UF 4.7UF 0.1UF 0.1UF
20%
6.3V
MCP79 Ethernet VRef 20%
4V
20%
10V
20%
10V
2 CERM X5R-1 2 2 CERM 2 CERM
402-LF 402 402 402
23 18 8 =PP3V3_ENET_MCP_RMGT
1
R2591
1.47K
1%
A L2595
1/16W
MF-LF
402
2
PAGE TITLE
30-OHM-1.7A
8 =PP1V05_ENET_MCP_PLL_MAC
5 mA (A01) 1 2
PP1V05_ENET_MCP_PLL_MAC
18
5 mA (A01)
MCP_MII_VREF OUT 18
MCP Standard Decoupling
VOLTAGE=1.05V
1
DRAWING NUMBER SIZE
0402
C2595 1 1
C2596
R2590
1.47K
1
C2591
0.1UF
4.7UF 0.1UF 1%
20%
REVISION
20%
4V
2 2
20%
10V
1/16W
MF-LF
402
2
10V
CERM
R
C.0.0
X5R-1 CERM
402 402
2 402
25 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NO STUFF NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
L2650 Apple: 2x 2.2uF 0402 (4.4 uF)
30-OHM-1.7A
18 8 =PP3V3R1V8_S0_MCP_IFP_VDD 8 =PP3V3_S0_MCP_DAC_UF PP3V3_S0_MCP_DAC 18
1 2
190 mA (A01, 1.8V) 206 mA (A01) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=3.3V
1
C2610 0402
NO STUFF
1
2.2UF 1 R2651
20%
C2650
0
2
6.3V 2.2UF 5%
CERM 20%
D
402-LF
2
6.3V
CERM
402-LF 2
1/16W
MF-LF
402 D
18 8 =PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
1 1
C2615 C2616
4.7UF 0.1UF
20% 20%
4V 10V
X5R-1 2 2
CERM
402 402
72 18 MCP_HDMI_RSET 72 18 MCP_IFPAB_RSET
72 18 MCP_HDMI_VPROBE 72 18 MCP_IFPAB_VPROBE NO STUFF
C NO STUFF
C2620 1
1
R2620
1K
NO STUFF
C2630 1
1
R2630
1K
C
1% 1%
0.1UF 0.1UF
1/16W 1/16W
20% 20%
MF-LF MF-LF
10V 10V
2 402 2 402
CERM 2 CERM 2
402 402
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2640 Apple: ???
30-OHM-1.7A
8 =PP3V3_S0_MCP_VPLL_UF PP3V3_S0_MCP_VPLL 18
1 2
16 mA (A01) MIN_NECK_WIDTH=0.2 MM 16 mA (A01)
VOLTAGE=3.3V
0402
1 1
C2640 C2641
4.7UF 0.1uF
20% 20%
6.3V 10V
CERM 2 2 CERM
603 402
B B
PAGE TITLE
SYNC FROM T18 MCP Graphics Support

DRAWING NUMBER SIZE
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT Apple Inc. 051-7982 D
REVISION
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 R
C.0.0
NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650) NOTICE OF PROPRIETARY PROPERTY: BRANCH
CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
REMOVE HDCP ROMS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
26 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections
LPC Reset (Unbuffered)

R2820
0
8 =PP3V42_G3H_RTC_D 1 2 PP3V3_G3_RTC 7 21 22
R2881
MIN_LINE_WIDTH=0.3 mm PLACEMENT_NOTE=Place close to U1400 33
5% MIN_NECK_WIDTH=0.2 mm 73 19 LPC_RESET_L 1 2 DEBUG_RESET_L 38
1/16W
IN OUT
D
VOLTAGE=3.3V
MF-LF 5%
D 402 C2819
10% 1
1/16W
MF-LF
402
R2883
33
1 2 SMC_LRESET_L 36
1UF OUT
6.3V 5%
PLACEMENT_NOTE=Place close to U1400
CERM 2 1/16W
MF-LF
402 402
PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

PLACE C2819 CLOSE TO MCP79
PCIE Reset (Unbuffered)
R2892
0
17 IN PCIE_RESET_L 1 2 BKLT_PLT_RST_L OUT 69
5%
1/16W
MF-LF
R2891 402
0
1 2 MINI_RESET_L 30
OUT
5%
1/16W
RTC Crystal C2810

MF-LF
402 R2871
0
12pF 1 2 PCA9557D_RESET_L OUT 26
RTC_CLK32K_XTALOUT 1 2 5%
21 IN 1/16W
MF-LF
1 5%
R2810 50V
402
CERM
0 402
5%
1/16W
MF-LF
C 402
2
RTC_CLK32K_XTALOUT_R
C
NO STUFF
1
R2811 CRITICAL
4
10M
5% Y2810
1/16W
MF-LF 32.768K C2811
402
2
1
7X1.5X1.4-SM 12pF
RTC_CLK32K_XTALIN 1 2
21 OUT
5%
50V
CERM
402
MCP 25MHz Crystal

C2815
12pF R2870
33
MCP_CLK25M_XTALOUT 1 2 MEM_VTT_EN_R 1 2 MEM_VTT_EN =DDRVTT_EN
21 IN 19 IN OUT 58 64
MAKE_BASE=TRUE
5%
1 5%
R2815 50V
1/16W
MF-LF
0 CERM
402
402
5%
NO STUFF 1/16W
MF-LF
1
R2816 402
2 R2825
1M MCP_CLK25M_XTALOUT_R PLACEMENT_NOTE=Place close to U1400 33
5% 73 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC
OUT 36 73
1/16W
MF-LF 5%
402 CRITICAL 1/16W
R2826
3
2 MF-LF
4
402 33
Y2815 NC 1 2 LPC_CLK33M_LPCPLUS
OUT 38 73
2
25.0000M
SM-3.2X2.5MM
NC C2816 PLACEMENT_NOTE=Place close to U1400 5%
1
12pF 1/16W
MF-LF
MCP_CLK25M_XTALIN 1 2 402
21 OUT
5%
B 50V
CERM
402 PM_CLK32K_SUSCLK_R
R2829
22
PM_CLK32K_SUSCLK
B
MCP S0 PWRGD & CPU_VLD 73 21 IN
1
5%
2
OUT 36 73
8 =PP3V3_S5_MCPPWRGD 1/16W
MF-LF
402
MCPSEQ_SMC
1
C2850
0.1UF
20%
10V
2
CERM
402
Reset Button
36 PM_SYSRST_L
IN
MCPSEQ_SMC XDP
5 TC7SZ08AFEAPE
2 R2853 R2898 R2899 10K pull-up to 3.3V S0 inside MCP
63 36 ALL_SYS_PWRGD SOT665
IN A
0 0 33
4 S0_AND_IMVP_PGOOD 1 2 MCP_PS_PWRGD XDP_DBRESET_L 1 2 1 2 PM_SYSRST_DEBOUNCE_L
OUT 21 13 10 IN OUT 21
U2850 Y
VR_PWRGOOD_DELAY 1 5% 5%
59 IN B 1
NO STUFF 5% NO STUFF
1/16W 1/16W 1/16W
MF-LF MF-LF
R2890 MF-LF 1
C2899
3 402 402 0 402
1UF
5%
10%
MCPSEQ_MIX 1/16W 10V
MF-LF SILK_PART=SYS RST 2
X5R
402
R2852 2 402
0
1 2
MCPSEQ_MIX 5%
1/16W
MF-LF
R2851 402
0
1 2 MCP_CPU_VLD OUT 21
5% MCPSEQ_SMC
1/16W
MF-LF
402 R2850
A 21 IN MCP_CPUVDD_EN 1
0
5%
2
1/16W SYNC FROM T18 PAGE TITLE
MF-LF
402
CHANGE RESET BUTTOM TO RESET PADS SB Misc
DRAWING NUMBER SIZE
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.
REMOVE UNUSED PCIE RESET SIGNALS Apple Inc. 051-7982 D
REVISION
MCPSEQ_MIX is cross between MLB and internal power sequencing, which
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A R
C.0.0
results in earlier ROMSIP and MCP FSB I/O interface initialization. CHANGE RTC COIN CELL TO LDO & SUPERCAP NOTICE OF PROPRIETARY PROPERTY: BRANCH
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for ALIAS MEM_VTT_EN TO =DDRVTT_EN PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
CHANGE Y2810 AND U2850 TO SMALLER PARTS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
28 OF 109
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately. IV ALL RIGHTS RESERVED <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: MEM A VREF DQ MEM A VREF CA MEM B VREF DQ MEM B VREF CA CPU FSB VREF
- =PP3V3_S3_VREFMRGN
DAC channel A B A B C
- =PP3V3_S5_VREFMRGN
Min DAC code 0x00 0x00 0x00 0x00 0x00
- =PPVTT_S3_DDR_BUF
Max DAC code 0x87 0x87 0x87 0x87 0x55
Signal aliases required by this page: Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
- =I2C_VREFDACS_SCL Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA
- =I2C_VREFDACS_SDA Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V (i.e. not simultaneously) due to current limitation of TPS51116 regulator.
- =I2C_PCA9557D_SCL Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V
- =I2C_PCA9557D_SDA Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V =PPVTT_S3_DDR_BUF
58 8
D BOM options provided by this page:

Vref Stepping
(per DAC LSB)
6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV
10mA max load D
VREFMRGN
NO_VREFMRGN
R2903 VREFMRGN
200
1 2
1%
1/16W
MF-LF PP0V75_S3_MEM_VREFDQ_A
402 27
VREFMRGN A2
B1 U2902 MIN_LINE_WIDTH=0.3 mm
1
C2903 V+
MAX4253
UCSP
R2904 VREFMRGN MIN_NECK_WIDTH=0.2 mm
0.1UF A1
100
VREFMRGN VREFMRGN_DQ_SODIMMA_BUF 1 2
20%
10V 1%
2
=PP3V3_S3_VREFMRGN CERM A3 A4
1/16W Place close to J3100.1
8
402 V- 26 VREFMRGN_DQ_SODIMMA_EN MF-LF
B4 402
VREFMRGN VREFMRGN R2905 VREFMRGN
2
C2900 1
C2901 R2901 200
1 2
2.2UF 0.1UF 100K VREFMRGN
20% 20% 5% 1%
6.3V 10V 1/16W 1/16W
2
CERM CERM MF-LF MF-LF PP0V75_S3_MEM_VREFDQ_B
1
402-LF 402 402 402 28
C2
V+
MAX4253
UCSP
100
VREFMRGN VREFMRGN C1 VREFMRGN_DQ_SODIMMB_BUF 1 2
8 U2900 C3 C4
1%
V- MF-LF
VDD B4
26 VREFMRGN_DQ_SODIMMB_EN
402
39 =I2C_VREFDACS_SCL 6 SCL VOUTA 1 VREFMRGN_DQ_SODIMM
IN MSOP
DAC5574
2
39 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_CA_SODIMM R2902 R2909 VREFMRGN
200
100K VREFMRGN 1 2
9 A0 VOUTC 4 VREFMRGN_CPUFSB 5%
1/16W 1%
MF-LF 1/16W
1
ADDR=0x98(WR)/0x99(RD)
C
10 A1 VOUTD 5
NC
VREFMRGN A2
B1 U2903
402 MF-LF
402
PP0V75_S3_MEM_VREFCA_A
27 C
GND 1
C2904 V+
MAX4253
UCSP
3 100
0.1UF VREFMRGN A1 VREFMRGN_CA_SODIMMA_BUF 1 2
20%
10V
2 1%
CERM A3 A4
402 V- 26 VREFMRGN_CA_SODIMMA_EN MF-LF
B4 402
R2911 VREFMRGN
2
R2907 200
1 2
100K VREFMRGN
5% 1%
1/16W 1/16W
MF-LF MF-LF PP0V75_S3_MEM_VREFCA_B
1
402 402 28
C2
V+
MAX4253
UCSP
C1
100
VREFMRGN VREFMRGN_CA_SODIMMB_BUF 1 2
1%
C3 C4
V- 26 VREFMRGN_CA_SODIMMB_EN MF-LF
B4 402
2
R2908
100K VREFMRGN
5%
1/16W
MF-LF
1
402
VREFMRGN A2
B1 U2904
MAX4253
1
C2905 V+ UCSP
0.1UF VREFMRGN
A1
20% NC
10V
2 A4
CERM A3
402 V-
B4
B B
C2
B1 U2904
VREFMRGN MAX4253 R2914 VREFMRGN
V+ UCSP
1
C2902 VREFMRGN 100
16
VREFMRGN C1 VREFMRGN_CPUFSB_BUF 1 2 CPU_GTLREF 10 70

0.1UF OUT
20% VCC 1%
2
10V C3 C4
1/16W Place close to U1000.AD26
CERM
U2901 V- 26 VREFMRGN_CPUFSB_EN MF-LF
402 B4 402
PCA9557
QFN
6
P0
2
NC VREFMRGN_CPUFSB_EN
R2913
3 P1 7
A0 26
100K
VREFMRGN_CA_SODIMMA_EN VREFMRGN
4 P2 9
ADDR=0x30(WR)/0x31(RD) A1 26 5%
1/16W
VREFMRGN_DQ_SODIMMA_EN
5 P3 10 MF-LF
A2 26
1
VREFMRGN_CA_SODIMMB_EN 402
11
P4 26
VREFMRGN_DQ_SODIMMB_EN
12
P5 26
=I2C_PCA9557D_SCL 1 P6 13
39 IN SCL NC
=I2C_PCA9557D_SDA 2 P7 14
39 BI SDA NC
PCA9557D_RESET_L
THRM RESET* 15
IN 25
PAD GND
17
PAGE TITLE
Required zero ohm resistors when no VREF margining circuit stuffed FSB/DDR3 Vref Margining
DRAWING NUMBER SIZE
REVISION
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2903 CRITICAL NO_VREFMRGN R
C.0.0
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2905 CRITICAL NO_VREFMRGN NOTICE OF PROPRIETARY PROPERTY: BRANCH
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2909 CRITICAL NO_VREFMRGN PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2911 CRITICAL NO_VREFMRGN I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
29 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
8 =PP1V5_S3_MEM_A
Power aliases required by this page:
- =PP1V5_S0_MEM_A
1 1 1 1 1 1 1 1
- =PP1V5_S3_MEM_A
1
C3100 1
C3101 C3110 C3111 C3112 C3113 C3114 C3115 C3116 C3117
- =PP0V75_S0_MEM_VTT_A
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 10V 10V 10V 10V 10V 10V 10V 10V
- =PPSPD_S0_MEM_A (2.5 - 3.3V) 2
X5R
2
X5R
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
603 603 402 402 402 402 402 402 402 402
Signal aliases required by this page:
- =I2C_SODIMMA_SCL
- =I2C_SODIMMA_SDA
(NONE)
26 PP0V75_S3_MEM_VREFDQ_A D
1 1
C3130 C3131
2.2UF 0.1UF
20% 20%
6.3V 10V
2 2
CERM CERM
402-LF 402
1 2
VREFDQ VSS
3 VSS OMIT DQ4 4 MEM_A_DQ<4> 15 71
BI
KEY
73 74 5 6
71 15 IN MEM_A_CKE<0> CKE0 CKE1 MEM_A_CKE<1>
IN 15 71 71 15 BI MEM_A_DQ<0> DQ0 DQ5 MEM_A_DQ<5>
BI 15 71
CRITICAL
75 76 7 8
VDD OMIT VDD 71 15 BI MEM_A_DQ<1> DQ1 VSS
77 78 9 10
NC NC J3100 A15 MEM_A_A<15> IN 9 VSS DQS0* MEM_A_DQS_N<0> BI 15 71
71 15 IN MEM_A_BA<2> 79
BA2 F-RT-THB A14 80 MEM_A_A<14> IN 15 71 71 15 IN MEM_A_DM<0> 11
DM0 J3100 DQS0 12 MEM_A_DQS_P<0> BI 15 71
F-RT-THB
(SYMBOL 2 OF 2)
81 82 13 14
DDR3-SODIMM-DUAL-M97-3
VDD VDD VSS VSS
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 1 OF 2)
83 84 15 16
71 15 IN MEM_A_A<12> A12/BC* A11 MEM_A_A<11>
BI 15 71
85 86 17 18
71 15 IN MEM_A_A<9> A9 A7 MEM_A_A<7>
BI 15 71
87 88 19 20
VDD VDD VSS VSS
71 15 MEM_A_A<8> 89 A8 A6 90 MEM_A_A<6> 15 71 71 15 MEM_A_DQ<14> 21 DQ8 DQ12 22 MEM_A_DQ<9> 15 71
IN IN BI BI
91 92 23 24
71 15 IN MEM_A_A<5> A5 A4 MEM_A_A<4> IN 15 71 71 15 BI MEM_A_DQ<11> DQ9 DQ13 MEM_A_DQ<8> BI 15 71
93 94 25 26
VDD VDD VSS VSS
95 96 27 28
71 15 IN MEM_A_A<3> A3 A2 MEM_A_A<2>
IN 15 71 71 15 BI MEM_A_DQS_N<1> DQS1* DM1 MEM_A_DM<1> IN 15 71
71 15 MEM_A_A<1> 97 A1 A0 98 MEM_A_A<0> 15 71 71 15 MEM_A_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L 28 29

IN IN BI IN
99 100 31 32
VDD VDD VSS VSS
101 102 33 34
71 15 IN MEM_A_CLK_P<0> CK0 CK1 MEM_A_CLK_P<1> IN 15 71 71 15 BI MEM_A_DQ<13> DQ10 DQ14 MEM_A_DQ<15> BI 15 71
103 104 35 36
71 15 IN MEM_A_CLK_N<0> CK0* CK1* MEM_A_CLK_N<1>
IN 15 71 71 15 BI MEM_A_DQ<12> DQ11 DQ15 MEM_A_DQ<10> BI 15 71
C 105
107
VDD VDD 106
108
37
39
VSS VSS 38
40
C
71 15 IN MEM_A_A<10> A10/AP BA1 MEM_A_BA<1>
BI 15 71
109 110 41 42
71 15 IN MEM_A_BA<0> BA0 RAS* MEM_A_RAS_L
BI 15 71
111 112 43 44
VDD VDD VSS VSS
113 114 45 46
71 15 IN MEM_A_WE_L WE* S0* MEM_A_CS_L<0> IN 15 71 71 15 BI MEM_A_DQS_N<3> DQS2* DM2 MEM_A_DM<3> IN 15 71
71 15 MEM_A_CAS_L 115 CAS* ODT0 116 MEM_A_ODT<0> 15 71 71 15 MEM_A_DQS_P<3> 47 DQS2 VSS 48

IN IN BI
117 118 49 50
VDD VDD VSS DQ22 MEM_A_DQ<27> BI 15 71
119 120 51 52
71 15 IN MEM_A_A<13> A13 ODT1 MEM_A_ODT<1> IN 15 71 71 15 BI MEM_A_DQ<26> DQ18 DQ23 MEM_A_DQ<31> BI 15 71
121 122 53 54
71 15 IN MEM_A_CS_L<1> S1* NC NC 71 15 BI MEM_A_DQ<30> DQ19 VSS
123 VDD VDD 124 55 VSS DQ28 56 MEM_A_DQ<18> 15 71
BI
125 126 57 58
NC TEST VREFCA 71 15 BI MEM_A_DQ<20> DQ24 DQ29 MEM_A_DQ<17> BI 15 71
127 128 59 60
VSS VSS 71 15 BI MEM_A_DQ<21> DQ25 VSS
129 130 61 62
71 15 BI MEM_A_DQ<34> DQ32 DQ36 MEM_A_DQ<37>
BI 15 71 VSS DQS3* MEM_A_DQS_N<2>
BI 15 71
71 15 MEM_A_DQ<35> 131 DQ33 DQ37 132 MEM_A_DQ<36> 15 71 71 15 MEM_A_DM<2> 63 DM3 DQS3 64 MEM_A_DQS_P<2> 15 71
BI BI IN BI
133 134 65 66
VSS VSS VSS VSS
135 136 67 68
71 15 BI MEM_A_DQS_N<4> DQS4* DM4 MEM_A_DM<4>
BI 15 71
137 138 69 70
71 15 BI MEM_A_DQS_P<4> DQS4 VSS 71 15 BI MEM_A_DQ<16> DQ27 DQ31 MEM_A_DQ<19>
BI 15 71
139 140 71 72
VSS DQ38 MEM_A_DQ<38> BI 15 71 VSS VSS
141 142
71 15 BI MEM_A_DQ<32> DQ34 DQ39 MEM_A_DQ<39> BI 15 71 KEY
143 144
71 15 BI MEM_A_DQ<33> DQ35 VSS
145 146
VSS DQ44 MEM_A_DQ<41>
BI 15 71 516-0201
147 148
BI 15 71
71 15 MEM_A_DQ<45> 149 DQ41 VSS 150

BI
151 152
VSS DQS5* MEM_A_DQS_N<5>
BI 15 71
153 154
71 15 IN MEM_A_DM<5> DM5 DQS5 MEM_A_DQS_P<5>
BI 15 71
155 156
VSS VSS
B 71 15
71 15
BI
BI
MEM_A_DQ<47>
MEM_A_DQ<46>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
MEM_A_DQ<43>
MEM_A_DQ<42>
BI
BI
15 71
15 71
B
161 162
VSS VSS
163 164
BI 15 71
165 166
71 15 BI MEM_A_DQ<52> DQ49 DQ53 MEM_A_DQ<48> BI 15 71
167 168
VSS VSS
169 170
71 15 BI MEM_A_DQS_N<6> DQS6* DM6 MEM_A_DM<6> IN 15 71
171 172
71 15 BI MEM_A_DQS_P<6> DQS6 VSS
173 174
VSS DQ54 MEM_A_DQ<55>
BI 15 71
71 15 MEM_A_DQ<54> 175 DQ50 DQ55 176 MEM_A_DQ<50> 15 71 PP0V75_S3_MEM_VREFCA_A 26

BI BI
177 178
71 15 BI MEM_A_DQ<51> DQ51 VSS
179 180
VSS DQ60 MEM_A_DQ<57> BI 15 71
181 182 1 1
BI 15 71 C3135 C3136
71 15 MEM_A_DQ<60> 183 DQ57 VSS 184 2.2UF 0.1UF
BI 20% 20%
185 186 6.3V 10V
VSS DQS7* MEM_A_DQS_N<7>
BI 15 71 2
CERM
2
CERM
187 188 402-LF 402
71 15 IN MEM_A_DM<7> DM7 DQS7 MEM_A_DQS_P<7>
BI 15 71
189 190
VSS VSS
71 15 MEM_A_DQ<58> 191 DQ58 DQ62 192 MEM_A_DQ<62> 15 71
BI BI
193 194
71 15 BI MEM_A_DQ<59> DQ59 DQ63 MEM_A_DQ<63> BI 15 71
195 196
VSS VSS
197 198
MEM_A_SA<0> SA0 EVENT* MEM_EVENT_L OUT 21 28 36
199 200
8 =PPSPD_S0_MEM_A VDDSPD SDA =I2C_SODIMMA_SDA BI 39 "Factory" (top) slot
MEM_A_SA<1> 201 SA1 SCL 202 =I2C_SODIMMA_SCL 39
IN
203 204
VTT VTT =PP0V75_S0_MEM_VTT_A 8
1 1
1
C3140 R3140 R3141
1 1
A 2
2.2UF
20%
6.3V
10K
5%
1/16W
MF-LF
10K
5%
1/16W
MF-LF
C3150
2.2UF
20%
C3151
2.2UF
20%
CERM
402 402 2
6.3V
2
6.3V PAGE TITLE
402-LF 2 2 CERM
402-LF
CERM
402-LF
DDR3 SO-DIMM Connector A
DRAWING NUMBER SIZE

REVISION
516-0201
R
C.0.0
SPD ADDR=0xA0(WR)/0xA1(RD) NOTICE OF PROPRIETARY PROPERTY: BRANCH
31 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes DDR3 DECOUPLING AND GROUND RETURN CAPS (CONNECTOR SIDE)
8 =PP1V5_S3_MEM_B
Power aliases required by this page:
- =PP1V5_S0_MEM_B
1 1 1 1 1 1 1 1
- =PP1V5_S3_MEM_B
1
C3200 1
C3201 C3210 C3211 C3212 C3213 C3214 C3215 C3216 C3217
- =PP0V75_S0_MEM_VTT_B
10UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 10V 10V 10V 10V 10V 10V 10V 10V
- =PPSPD_S0_MEM_B (2.5 - 3.3V) 2
X5R
2
X5R
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
603 603 402 402 402 402 402 402 402 402
Signal aliases required by this page:
- =I2C_SODIMMB_SCL
- =I2C_SODIMMB_SDA
(NONE)
26 PP0V75_S3_MEM_VREFDQ_B D
1 1
C3230 C3231
2.2UF 0.1UF
20% 20%
6.3V 10V
2 2
CERM CERM
402-LF 402
1 2
VREFDQ VSS
3 VSS OMIT DQ4 4 MEM_B_DQ<4> 15 71
BI
KEY
73 74 5 6
71 15 IN MEM_B_CKE<0> CKE0 CKE1 MEM_B_CKE<1>
IN 15 71 71 15 BI MEM_B_DQ<1> DQ0 DQ5 MEM_B_DQ<5>
BI 15 71
CRITICAL
75 76 7 8
VDD VDD 71 15 BI MEM_B_DQ<0> DQ1 VSS
77
OMIT 78 9 10
NC A15 MEM_B_A<15> IN 9 VSS DQS0* MEM_B_DQS_N<0> BI 15 71
71 15 IN MEM_B_BA<2> 79
BA2 J3200 A14 80 MEM_B_A<14> IN 15 71 71 15 IN MEM_B_DM<0> 11
DM0 J3200 DQS0 12 MEM_B_DQS_P<0> BI 15 71
81 82 13 F-RT-BGA3 14
VDD F-RT-BGA3 VDD VSS VSS
DDR3-SODIMM
(1 OF 2)
(2 OF 2)
DDR3-SODIMM
83 84 15 16
71 15 IN MEM_B_A<12> A12/BC* A11 MEM_B_A<11>
BI 15 71
85 86 17 18
71 15 IN MEM_B_A<9> A9 A7 MEM_B_A<7>
BI 15 71
87 88 19 20
VDD VDD VSS VSS
71 15 MEM_B_A<8> 89 A8 A6 90 MEM_B_A<6> 15 71 71 15 MEM_B_DQ<13> 21 DQ8 DQ12 22 MEM_B_DQ<12> 15 71
IN IN BI BI
91 92 23 24
71 15 IN MEM_B_A<5> A5 A4 MEM_B_A<4> IN 15 71 71 15 BI MEM_B_DQ<14> DQ9 DQ13 MEM_B_DQ<9> BI 15 71
93 94 25 26
VDD VDD VSS VSS
95 96 27 28
71 15 IN MEM_B_A<3> A3 A2 MEM_B_A<2> IN 15 71 71 15 BI MEM_B_DQS_N<1> DQS1* DM1 MEM_B_DM<1>
IN 15 71
71 15 MEM_B_A<1> 97 A1 A0 98 MEM_B_A<0> 15 71 71 15 MEM_B_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L 27 29

IN IN BI IN
99 100 31 32
VDD VDD VSS VSS
101 102 33 34
71 15 IN MEM_B_CLK_P<0> CK0 CK1 MEM_B_CLK_P<1> IN 15 71 71 15 BI MEM_B_DQ<15> DQ10 DQ14 MEM_B_DQ<8>
BI 15 71
103 104 35 36
71 15 IN MEM_B_CLK_N<0> CK0* CK1* MEM_B_CLK_N<1>
BI 15 71
C 105
107
VDD VDD 106
108
37
39
VSS VSS 38
40
C
71 15 IN MEM_B_A<10> A10/AP BA1 MEM_B_BA<1>
BI 15 71
109 110 41 42
71 15 IN MEM_B_BA<0> BA0 RAS* MEM_B_RAS_L
BI 15 71
111 112 43 44
VDD VDD VSS VSS
113 114 45 46
71 15 IN MEM_B_WE_L WE* S0* MEM_B_CS_L<0> IN 15 71 71 15 BI MEM_B_DQS_N<2> DQS2* DM2 MEM_B_DM<2> IN 15 71
71 15 MEM_B_CAS_L 115 CAS* ODT0 116 MEM_B_ODT<0> 15 71 71 15 MEM_B_DQS_P<2> 47 DQS2 VSS 48

IN IN BI
117 118 49 50
VDD VDD VSS DQ22 MEM_B_DQ<21> BI 15 71
119 120 51 52
71 15 IN MEM_B_A<13> A13 ODT1 MEM_B_ODT<1> IN 15 71 71 15 BI MEM_B_DQ<18> DQ18 DQ23 MEM_B_DQ<23>
BI 15 71
121 122 53 54
71 15 IN MEM_B_CS_L<1> S1* NC 71 15 BI MEM_B_DQ<19> DQ19 VSS
123 VDD VDD 124 55 VSS DQ28 56 MEM_B_DQ<29> 15 71
BI
125 126 57 58
TEST VREFCA 71 15 BI MEM_B_DQ<24> DQ24 DQ29 MEM_B_DQ<25>
BI 15 71
127 128 59 60
VSS VSS 71 15 BI MEM_B_DQ<28> DQ25 VSS
129 130 61 62
71 15 BI MEM_B_DQ<33> DQ32 DQ36 MEM_B_DQ<37> BI 15 71 VSS DQS3* MEM_B_DQS_N<3>
BI 15 71
71 15 MEM_B_DQ<36> 131 DQ33 DQ37 132 MEM_B_DQ<32> 15 71 71 15 MEM_B_DM<3> 63 DM3 DQS3 64 MEM_B_DQS_P<3> 15 71
BI BI IN BI
133 134 65 66
VSS VSS VSS VSS
135 136 67 68
71 15 BI MEM_B_DQS_N<4> DQS4* DM4 MEM_B_DM<4>
BI 15 71
137 138 69 70
71 15 BI MEM_B_DQS_P<4> DQS4 VSS 71 15 BI MEM_B_DQ<27> DQ27 DQ31 MEM_B_DQ<31>
BI 15 71
139 140 71 72
VSS DQ38 MEM_B_DQ<39> BI 15 71 VSS VSS
141 142
71 15 BI MEM_B_DQ<35> DQ34 DQ39 MEM_B_DQ<34> BI 15 71 KEY
143 144
71 15 BI MEM_B_DQ<38> DQ35 VSS
145 146
VSS DQ44 MEM_B_DQ<40>
BI 15 71 516S0706
147 148
71 15 BI MEM_B_DQ<45> DQ40 DQ45 MEM_B_DQ<44> BI 15 71
71 15 MEM_B_DQ<41> 149 DQ41 VSS 150

BI
151 152
VSS DQS5* MEM_B_DQS_N<5>
BI 15 71
153 154
71 15 IN MEM_B_DM<5> DM5 DQS5 MEM_B_DQS_P<5>
BI 15 71
155 156
VSS VSS
B 71 15
71 15
BI
BI
MEM_B_DQ<46>
MEM_B_DQ<47>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
MEM_B_DQ<42>
MEM_B_DQ<43>
BI
BI
15 71
15 71
B
161 162
VSS VSS
71 15 MEM_B_DQ<52> 163
DQ48 DQ52 164 MEM_B_DQ<53> 15 71
DDR3 GROUND RETURN CAPS (MCP SIDE)
BI BI
8 =PP1V5_S0_MEM_MCP
165 166
71 15 BI MEM_B_DQ<49> DQ49 DQ53 MEM_B_DQ<48> BI 15 71
167 168
VSS VSS
169 170 1 1 1 1 1 1 1 1
71 15 BI MEM_B_DQS_N<6> DQS6* DM6 MEM_B_DM<6> IN 15 71 C3222 C3223 C3224 C3225 C3226 C3227 C3228 C3229
71 15 MEM_B_DQS_P<6> 171
DQS6 VSS 172 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
BI 20% 20% 20% 20% 20% 20% 20% 20%
173 174 10V 10V 10V 10V 10V 10V 10V 10V
VSS DQ54 MEM_B_DQ<51>
BI 15 71 2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
2 CERM
175 176 402 402 402 402 402 402 402 402
71 15 BI MEM_B_DQ<55> DQ50 DQ55 MEM_B_DQ<50>
BI 15 71 PP0V75_S3_MEM_VREFCA_B 26
177 178
71 15 BI MEM_B_DQ<54> DQ51 VSS
179 180
VSS DQ60 MEM_B_DQ<63> BI 15 71
181 182 1 1
71 15 BI MEM_B_DQ<56> DQ56 DQ61 MEM_B_DQ<59>
BI 15 71 C3235 C3236
71 15 MEM_B_DQ<58> 183 DQ57 VSS 184 2.2UF 0.1UF
BI 20% 20%
185 186 6.3V 10V
VSS DQS7* MEM_B_DQS_N<7>
BI 15 71 2
CERM
2
CERM
1 187 188 402-LF 402
R3240 71 15 IN MEM_B_DM<7> DM7 DQS7 MEM_B_DQS_P<7>
BI 15 71
189 190
10K VSS VSS
5%
71 15 MEM_B_DQ<61> 191 DQ58 DQ62 192 MEM_B_DQ<62> 15 71
1/16W BI BI
MF-LF
193 194
2
402 71 15 BI MEM_B_DQ<60> DQ59 DQ63 MEM_B_DQ<57> BI 15 71
195 196
VSS VSS
197 198
MEM_B_SA<0> SA0 EVENT* MEM_EVENT_L OUT 21 27 36
199 200
8 =PPSPD_S0_MEM_B VDDSPD SDA =I2C_SODIMMB_SDA BI 39
201 202
"Expansion" (bottom) slot
MEM_B_SA<1> SA1 SCL =I2C_SODIMMB_SCL IN 39
203 204
VTT VTT =PP0V75_S0_MEM_VTT_B 8
MTG PINS
1 205 206
1 R3241 MTG PIN MTG PIN
C3240 207 208 1 1
A 2
2.2UF
20%
6.3V
10K
5%
1/16W
MF-LF
209
MTG PIN
MTG PIN
MTG PIN
MTG PIN
210
C3250
2.2UF
20%
C3251
2.2UF
20%
CERM 211 212 6.3V 6.3V PAGE TITLE
402 MTG PIN MTG PIN 2 2
402-LF 2 CERM
402-LF
CERM
402-LF
DDR3 SO-DIMM Connector B
DRAWING NUMBER SIZE

REVISION
R
C.0.0
516S0706 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SPD ADDR=0xA2(WR)/0xA3(RD) THE INFORMATION CONTAINED HEREIN IS THE
32 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.
R3309
0
16 IN MCP_MEM_RESET_L 2 1 MEM_RESET_L OUT 27 28
5%
1/16W
MF-LF
8 =PP1V5_S3_MEMRESET 402
R3310 1 Q3305
1K =PP3V3_S5_MEMRESET 8
5% DMB53D0UDW
1/16W SOT-363
C R3300 1
MF-LF
402
2 R3305 1
3.3V S5 is used because MEM_RESET
C
Q1
10K 100K
S
6
1
5% 5% must be high before 1.5V starts to
1/16W 1/16W
MF-LF MF-LF rise to avoid glitch on MEM_RESET_L.
402 402
2 2
G
5
2
MEM_RESET_RC_L MEM_RESET
R3301 1
Q2
1
C3300
C
4
3
20K 0.1UF
5%
20%
1/16W 10V
MF-LF 2 CERM
402 402
2
B B
PAGE TITLE
DDR3 Support
DRAWING NUMBER SIZE

REVISION
R
C.0.0
33 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
17 OUT PCIE_MINI_PRSNT_L
3 D Q3401
SSM6N15FEAPE
SOT563
4
S G 5
AP_PWR_EN IN 21 32
3V S3 WLAN FET
D D
17 OUT MINI_CLKREQ_L
MOSFET TPCP8102
CHANNEL P-TYPE
6 D Q3401
SSM6N15FEAPE RDS(ON) 20-30 MOHM @2.5V
SOT563
LOADING 0.727 A (EDP)
1
S G 2
CRITICAL
7 MINI_CLKREQ_Q_L CRITICAL
CRITICAL
Q3450
L3405 155S0367 R3452 TPCP8102
90-OHM-100MA 0.002
DLP11S 727 MA PEAK L3404 MIN_LINE_WIDTH=1 mm
1%
1/4W
MIN_LINE_WIDTH=1 mm
23V1K-SM
8
SYM_VER-1
PLACEMENT_NOTE=Place close to J3401. 606 MA NOMINAL MAX FERR-120-OHM-3A MIN_NECK_WIDTH=0.5 mm
MF MIN_NECK_WIDTH=0.5 mm
3
VOLTAGE=3.3V VOLTAGE=3.3V
CONN_PCIE_MINI_R2D_P 4 3 C3431 1206
7
72 7
1 2 1 2 1 2
2
PCIE_MINI_R2D_P PCIE_MINI_R2D_C_P PP3V3_WLAN PP3V3_WLAN_F PP3V3_WLAN_R =PP3V3_S3_WLAN
S
D
72 0.1uF 17 72 7 47 30 8 30
IN
6
MIN_LINE_WIDTH=1 mm MIN_LINE_WIDTH=0.5 mm
1 2 10% 16V X5R 402 0603 3 4
1
72 PCIE_MINI_R2D_N 0.1uF PCIE_MINI_R2D_C_N IN 17 72 MIN_NECK_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
5
VOLTAGE=3.3V VOLTAGE=3.3V
CONN_PCIE_MINI_R2D_N 1 2
4 G
72 7 10% 16V X5R 402 1
PLACEMENT_NOTE=Place close to J3401. CRITICAL C3422 1
C3421 1 1
C3420 C3451 1 R3451
C3430 10K
516S0582 L3402 PLACEMENT_NOTE=Place close to J3401.
0.1uF
20%
0.1uF
20%
10UF
20%
0.033UF
10%
5%
90-OHM-100MA 1/16W
10V 10V 10V 16V
DLP11S 2 2 2 2 MF-LF
SYM_VER-1 CERM CERM X5R C3450 X5R
402
CRITICAL 402 402 805
0.1UF
402 R3450 2
72 7 CONN_PCIE_MINI_D2R_P 4 3 PCIE_MINI_D2R_P OUT 17 72 100K
J3401
500913-0302
CRITICAL AIRPORT 1
10%
2 P3V3WLAN_SS 1
5%
1/16W
2 PM_WLAN_EN_L IN 30
32
F-ST-SM
32
72 7 CONN_PCIE_MINI_D2R_N 1 2 PCIE_MINI_D2R_N OUT 17 72 L3401 16V MF-LF
31 PLACEMENT_NOTE=Place close to J3401. 90-OHM-100MA X5R 402
C 2 1 4
DLP11S
SYM_VER-1
3 PCIE_CLK100M_MINI_P
PLACEMENT_NOTE=Place close to J3401.
PLACEMENT_NOTE=Place close to Q3450.

402
C
IN 17 72
PLACEMENT_NOTE=Place close to Q3450.
4 3 72 7 PCIE_CLK100M_MINI_CONN_P
6 5 72 7 PCIE_CLK100M_MINI_CONN_N ISNS_AIRPORT_P 47 76
1 2 PCIE_CLK100M_MINI_N OUT
8 IN 17 72
7 ISNS_AIRPORT_N 47 76
OUT
PLACEMENT_NOTE=Place close to J3401.
10 9
12 11
NC
14 13
NC
16 15 L3403
18
20
17
19
BLUETOOTH 90-OHM
DLP0NS
SYM_VER-1
CRITICAL
22 21
4 3 USB_BT_P BI 20 73
73 7 CONN_USB2_BT_P
24 23 73 7 CONN_USB2_BT_N
26 25 1 2 USB_BT_N 20 73
BI
28 27 7 PP3V3_S3_BT_F PLACEMENT_NOTE=Place close to J3401.
30 29 1 C3432 L3406
0.01UF
10% 2 1 =PP3V3_S3_BT 8
34 33 2 16V
CERM
402 FERR-120-OHM-1.5A
0402-LF
PLACEMENT_NOTE=PLACE L3406 NEAR J3401.
PLACEMENT_NOTE=PLACE C3432 NEAR J3401
B B
RC VALUE IS CHOSEN TO MEET THE 100 MS DELAY REQUIREMENT BETWEEN

3.3 WLAN POWER GETTING STABLE AND AIRPORT CARD COMING OUT OF RESET
PP3V3_WLAN_F 30 47
=PP3V3_S3_WLAN 8 30
1
PCIE_WAKE_L 7 17
R3453
OUT
110K
5%
1/16W
U3402 5 MF-LF
402
74LVC1G17 2
TC7SZ08AFEAPE 5 SOT353-1
SOT665 2 WLAN_SMIT_BUF 4 2 R3455
A
4
1
7 MINI_RESET_CONN_L WLAN_SMIT_RC 1 2 WLAN_SMIT_DISCHRG
Y U3401 NC
1 5%
B Q3455
3 1 1/16W
MF-LF
3 NC 1 402 3 D SSM3K15FV
C3453 1 R3454 SOD-VESM-HF
62K
MINI_RESET_L 1UF
IN 25
10%
5% NOSTUFF
A 6.3V
CERM
402
2
2
1/16W
MF-LF
402 SYNC_MASTER=K24_MLB SYNC_DATE=01/27/2009 A
PAGE TITLE
S G 1
2
PM_WLAN_EN_L 30 32
X16 WIRELESS CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
C.0.0
34 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_ENET_PHY 8
(221mA typ - 1000base-T)
D 1 1 1
( 7mA typ - Energy Detect) D
C3710 C3711 WF: Marvell numbers, update for Realtek
0.1UF 0.1UF CRITICAL
10% 10%
16V 16V
X5R
2
X5R
2 L3715
8 =PP3V3_ENET_PHY
402 402 FERR-120-OHM-1.5A
(43mA typ - 1000base-T) 0402-LF
(19mA typ - Energy Detect)

1 1 1 1
WF: Marvell numbers, update for Realtek C3700 C3701 C3702 2
CRITICAL 0.1UF 0.1UF 0.1UF

10% 10% 10% PP1V05_ENET_PHYAVDD
16V 16V 16V
L3705 2
X5R
2
X5R
2
X5R
402 402 402 MIN_NECK_WIDTH=0.2 MM
FERR-120-OHM-1.5A VOLTAGE=1.05V
1 1 1
0402-LF C3714 C3715 C3716
2.2UF 2.2UF 0.1UF
10% 10% 10%
6.3V 6.3V 16V
2 2 2 2
X5R X5R X5R
402 402 402
PP3V3_ENET_PHYAVDD
VOLTAGE=3.3V
1 1
C3705 C3706
0.1UF 0.1UF
10% 10% =PP3V3_ENET_PHY_VDDREG
16V 16V 9
2 2
X5R X5R
402 402
If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1 1 1
R3750 R3751 R3752
=RTL8211_REGOUT
41
15
21
37
44
45
28
36
10
40
4.7K 4.7K 4.7K 9
3
NO STUFF 5% 5% 5%
1/16W 1/16W 1/16W If internal switcher is used, must place inductor within 5mm
AVDD33
DVDD33
VDDREG
1 1
FB10
DVDD10
AVDD10
R3720 R3725 MF-LF
402
MF-LF
402
MF-LF
402 of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
2 2 2
10K 4.7K
C Alias to =PP3V3_ENET_PHY for internal switcher.

5%
1/16W
MF-LF
5%
1/16W
MF-LF
If internal switcher is not used, VDDREG and REGOUT can float. C
Alias to GND for external 1.05V supply. 402
2 2
402 CRITICAL
39
U3700 48
9 IN =RTL8211_ENSWREG ENSWREG RTL8251CA-VB-GR REGOUT
TQFP
R3796
0 22 19 R3790 22
74 18 IN ENET_CLK125M_TXCLK 1 2 74 ENET_CLK125M_TXCLK_R TXC RXC 74 ENET_CLK125M_RXCLK_R 1 2 ENET_CLK125M_RXCLK OUT 18 74
5% 1/16W MF-LF 402
5%
1/16W
402
23 14 R3791 22
MF-LF 74 18 IN ENET_TXD<0> TXD[0] RXD[0] 74 ENET_RXD_R<0> 1 2 ENET_RXD<0>
OUT 18 74
5% 1/16W MF-LF 402
24 16 R3792 22
PLACE R3796 CLOSE TO U1400, PIN D24 74 18 IN ENET_TXD<1> TXD[1] RXD[1]/TXDLY 74 ENET_RXD_R<1> 1 2 ENET_RXD<1> OUT 18 74
25 RGMII/MII 17 5% 1/16W MF-LF 402
74 18 IN ENET_TXD<2> TXD[2] RXD[2]/AN0 74 ENET_RXD_R<2> R3793 22 1 2 ENET_RXD<2>
OUT 18 74
5% 1/16W MF-LF 402
26 18 R3794 22
74 18 IN ENET_TXD<3> TXD[3] RXD[3]/AN1 74 ENET_RXD_R<3> 1 2 ENET_RXD<3> OUT 18 74
5% 1/16W MF-LF 402
27 13 R3795 22
74 18 IN ENET_TX_CTRL TXCTL RXCTL 74 ENET_RXCTL_R 1 2 ENET_RX_CTRL
OUT 18 74
5% 1/16W MF-LF 402
30 1
74 18 IN ENET_MDC MDC MDI+[0] ENET_MDI_P<0> BI 33 74
31 MANAGEMENT 2
74 18 BI ENET_MDIO MDIO MDI-[0] ENET_MDI_N<0>
BI 33 74
4
R3724 MDI+[1] ENET_MDI_P<1>
BI 33 74
5
0 29 MDI-[1] ENET_MDI_N<1> BI 33 74
74 18 IN ENET_RESET_L 1 2 RTL8211_PHYRST_L PHYRSTB* RESET MEDIA DEPENDENT
8
5% MDI+[2] ENET_MDI_P<2>
BI 33 74
1/16W
1 9
MF-LF C3725 MDI-[2] ENET_MDI_N<2>
BI 33 74
402
0.1UF 46
20%
RTL8211_RSET RSET REFERENCE 11
ENET_RESET_L IS NOT ASSERTED WHEN WOL IS ACTIVE. 10V MDI+[3] ENET_MDI_P<3> BI 33 74
2
CERM 12
HENCE, RC (C3725 AND R3725) ARE NOT STUFFED. NO STUFF 402
MDI-[3] ENET_MDI_N<3>
BI 33 74
B 1
9 TP_RTL8211_CLK125 32
CLK125 B
R3730 CLOCK LED0/PHYAD0 34 RTL8211_PHYAD0
2.49K
42 35
1% 74 32 IN RTL8211_CLK25M_CKXTAL1 CKXTAL1 LED LED1/PHYAD1 RTL8211_PHYAD1
1/16W
43 38
MF-LF TP_RTL8211_CKXTAL2 CKXTAL2 LED2/RXDLY RTL8211_RXDLY
402
2
GND NO STUFF
1 1 1
C3790 1 R3755 R3756 R3757
20
33
47
4.7K 4.7K 4.7K
10PF
5% 5% 5%
5%
1/16W 1/16W 1/16W
50V
2 MF-LF MF-LF MF-LF
CERM
402 402 402
402 2 2 2
Reserved for EMI

per RealTek request.
PAGE TITLE
Ethernet PHY (RTL8211CL)

DRAWING NUMBER SIZE

REVISION
R
C.0.0
Configuration Settings: NOTICE OF PROPRIETARY PROPERTY: BRANCH
PHYAD = 01 (PHY Address 00001) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
AN[1:0] = 11 (Full auto-negotiation)
RXDLY = 0 (RXCLK transitions with data)
37 OF 109
TXDLY = 0 (No TXCLK Delay)
IV ALL RIGHTS RESERVED<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V ENET FET

@ 2.5V Vgs: CRITICAL
Rds(on) = 90mOhm max Q3810

I(max) = 1.7A (85C) NTR4101P
SOT-23-HF
8 =PP3V3_S5_P3V3ENETFET =PP3V3_ENET_FET 8
2 S D 3
D 1 1
D
R3800 C3811 G
10K 0.033UF
10%
5% 1
16V
1/16W 2
X5R
MF-LF
402
402 C3810
2 R3810 0.01UF
100K
P3V3ENET_EN_L 1 2 P3V3ENET_SS 2 1
5%
10%
1/16W
MF-LF 16V
Q3801
D 3
402 CERM
402
SSM6N15FEAPE
SOT563
5 G S 4
9 IN =P3V3ENET_EN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and

=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L 30
OUT
C Pull-up is with power FET.
1.05V ENET FET C
Q3805 D 6
SSM6N15FEAPE
SOT563 8 =PP1V05_ENET_P1V05ENETFET
1.8V Vgs
2 G S 1 1
C3840
3
AP_PWR_EN AC_OR_S0_L 0.1UF
30 21 IN CRITICAL
20%
10V
2
D
CERM
8 =PP3V3_S5_P1V05ENETFET R3840 402 Q3840

Q3805 D 3 6 D Q3801 100K
1 2 P1V05ENET_SS 1 G SI2312BDS
SSM6N15FEAPE SSM6N15FEAPE SOT23
SOT563 SOT563 5% S
1/16W
MF-LF
1 402 Q3841 D 6 2
R3842 =PP1V05_ENET_FET 8
5 G S S G 2 69.8K SSM6N15FEAPE
4 1 SOT563
1%
1/16W
37 36 21 SMC_ADAPTER_EN
IN MF-LF
402
2
1
R3841 2 G S 1
C3841
10K 0.01UF
P1V05ENET_EN_L 1 2 10%
16V
67 63 36 21 7 PM_SLP_S3_L
IN 1%
2
CERM
402
1/16W
MF-LF
Q3841
D 3
402 P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
5 G S 4
B 9 IN =P1V05ENET_EN
B
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
A Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
PAGE TITLE
R3895
22
Ethernet & AirPort Support
74 18 MCP_CLK25M_BUF0_R 1 2 RTL8211_CLK25M_CKXTAL1 31 74 DRAWING NUMBER SIZE
IN OUT
5%
1/16W Apple Inc. 051-7982 D
MF-LF REVISION
402
R
C.0.0
38 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
- COPY THIS PAGE FROM K36 CSA.39
D D
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1 1 1 1
C3900 C3901 C3902 C3903
0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
16V 16V 16V 16V
2 2 2 2
X5R X5R X5R X5R
402 402 402 402
ETHERNET CONNECTOR
CRITICAL
OMIT
T3901
SM
CRITICAL
1 12
74 31 BI ENET_MDI_P<1> 74 ENET_MDI_TRAN_P<1>
J3900
RJ45-10/100TX-K83
ENET_MDI_N<1> 2 11 74 ENET_MDI_TRAN_N<1> F-R-TH
74 31 BI ENET_MDI
1
3 10
R3903 TRAN_P0
ENET_CENTER_TAP<1> 1 2 75 2
TRAN_N0
TX 1% 1/16W MF-LF 402 3
TRAN_P1
TLA-6T213HF 4
4 9
R3902 TRAN_P2
75
C ENET_CENTER_TAP<3>
1%
1
1/16W
2
MF-LF 402
5
6
TRAN_N2
TRAN_N1
C
74 31 ENET_MDI_P<3> 5 8 74 ENET_MDI_TRAN_P<3> 7
BI TRAN_P3
74 ENET_MDI_TRAN_N<3> 8
TRAN_N3
74 31 ENET_MDI_N<3> 6 7
BI
RX 9
10
CRITICAL SHIELD
11 PINS
T3902 12
1 SM 12 74 ENET_MDI_TRAN_N<2>
74 31 BI ENET_MDI_N<2>
74 31 ENET_MDI_P<2> 2 11 74 ENET_MDI_TRAN_P<2> 514-0692

BI
3 10
R3901
ENET_CENTER_TAP<2> 1 2 75
TX 1% 1/16W MF-LF 402
TLA-6T213HF R3900
4 9 ENET_CENTER_TAP<0> 1 2 75
1% 1/16W MF-LF 402
74 31 ENET_MDI_N<0> 5 8 74 ENET_MDI_TRAN_N<0>
BI
74 31 ENET_MDI_P<0> 6 7 74 ENET_MDI_TRAN_P<0>
BI
RX
ENET_BOB_SMITH_CAP
1
1 1
C3915 1
CRITICAL
C3911 C3913 10PF C3917 1
10PF 10PF 5% 10PF C3910
B 2
5%
50V
CERM
402-1
2
5%
50V
CERM
402-1
2
50V
CERM
402-1 2
5%
50V
CERM
402-1 2
1000PF
10%
2KV
CERM
B
CRITICAL CRITICAL 1206
CRITICAL CRITICAL CRITICAL
CRITICAL CRITICAL
1 1
C3912 C3914 1
CRITICAL
10PF 10PF C3916 1
5% 5% 10PF C3918
2
50V
2
50V 5% 10PF
CERM CERM 50V 5%
2
402-1 402-1 CERM 50V
402-1 2 CERM
402-1
PLACEMENT_NOTE=PLACE C3911-C3918 ON MDI LINES WITHOUT ANY STUBS
PAGE TITLE
ETHERNET CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
C.0.0
39 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q4590
ODD Power Control TPCP8102
23V1K-SM
PP5V_SW_ODD_R
=PP5V_S3_ODD
8
8 MIN_LINE_WIDTH=0.6mm
3
MIN_NECK_WIDTH=0.4mm
7
VOLTAGE=5V
6
1
5
R4596 1 C4595
G
NOTE: 3.3V must be S0 if 5V is S3 or S5 to
100K 0.068UF
4
ensure the drive is unpowered in S3/S5. 5%
10%
1/16W 10V
=PP3V3_S0_ODD
MF-LF
402
2 CERM C4596
34 8
R4595 402
0.01UF
100K
D R4597
ODD_PWR_EN_LS5V_L 1
5%
2 ODD_PWR_SS 1
10%
2
CRITICAL D
100K 1/16W
5%
1/16W Q4596 D 6
MF-LF
402
16V
CERM R4598 1 3 ISNS_ODD_P OUT 47 76
MF-LF
SSM6N15FEAPE
402 0.002
402 1%
SOT563 1/4W
MF ISNS_ODD_N OUT 47 76
ODD_PWR_EN 1206 2 4
2 G S 1
Q4596 D 3
SSM6N15FEAPE
SOT563
5 G S 4
21 IN ODD_PWR_EN_L
47 7 PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
VOLTAGE=5V
CRITICAL
SATA ODD FL4520

90-OHM-100MA
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
DLP11S PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
SYM_VER-1
34 8 =PP3V3_S0_ODD 3 4 72 SATA_ODD_R2D_UF_P 1 2 C4521 SATA_ODD_R2D_C_P IN 20 72
0.01UF 10% 16V CERM 402

CRITICAL
2 1 72 SATA_ODD_R2D_UF_N 1 2 C4520 SATA_ODD_R2D_C_N
1 J4500 IN 20 72
R4590 10% 16V CERM 402
C 33K
5%
54722-0164
1
F-ST-SM
2
PLACEMENT_NOTE=Place FL4520 close to J4500
0.01UF
C
1/16W
MF-LF
402 2
3 4 72 7 SATA_ODD_R2D_P
5 6 72 7 SATA_ODD_R2D_N
7 8
36 7 OUT SMC_ODD_DETECT 9 10 SATA_ODD_D2R_C_N

Indicates disc presence
11 12 SATA_ODD_D2R_C_P PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 FL4525
13 14
90-OHM-100MA
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526 DLP11S
SYM_VER-1
15 16
C4526 1 2 4
CRITICAL
3
72 SATA_ODD_D2R_UF_N SATA_ODD_D2R_N OUT 20 72
10% 16V CERM 402
0.01UF
516S0616 C4525 1 2 1 2
72 SATA_ODD_D2R_UF_P SATA_ODD_D2R_P OUT 20 72
10% 16V CERM 402
0.01UF
PLACEMENT_NOTE=Place FL4525 close to J4500
CRITICAL
J4502
78171-0002
M-RT-SM
3
R4531 PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
4.7 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
B 37 SYS_LED_ANODE 2
402
5%
1
1/16W
7 SYS_LED_ANODE_R 1
2
B
MF-LF
SIL 1
C4501
0.1UF
1
C4502
0.1UF CRITICAL
518S0519 20% 20%
1
C4531
2
10V
CERM
CRITICAL
2
10V
CERM R4599
402 402 0.002
0.001UF
10%
L4500 1%
1/4W
50V FERR-70-OHM-4A MF
2 CERM 1206
402
7 PP5V_S0_HDD_FLT 1 2 PP5V_S0_HDD_R 1 2 =PP5V_S0_HDD 8
MIN_LINE_WIDTH=0.6mm MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2MM 0603 MIN_NECK_WIDTH=0.4mm 3 4
VOLTAGE=5V PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501 VOLTAGE=5V
ISNS_HDD_P OUT 47 76
CRITICAL
FL4502 ISNS_HDD_N OUT 47 76
90-OHM-100MA
DLP11S
SYM_VER-1
72 7 SATA_HDD_D2R_C_N C4515 1 2 72 SATA_HDD_D2R_UF_N 4 3 SATA_HDD_D2R_N OUT 20 72

CRITICAL 10% 16V CERM 402
0.01UF
J4501 C4516
54722-0164 72 7 SATA_HDD_D2R_C_P 1 2 72 SATA_HDD_D2R_UF_P 1 2 SATA_HDD_D2R_P OUT 20 72
F-ST-SM
0.01UF 10% 16V CERM 402
1 2 PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
3 4 PLACEMENT_NOTE=Place C4515 next to C4516
PLACEMENT_NOTE=Place C4516 close to J4501
5 6
7 8
CRITICAL
SATA HDD NC
9
11
10
12
FL4501
90-OHM-100MA
A 13 14
DLP11S
SYM_VER-1
PLACEMENT_NOTE=Place C4511 next to C4510
PLACEMENT_NOTE=Place C4510 close to MCP79
15 16 72 7 SATA_HDD_R2D_N 3 4 72 SATA_HDD_R2D_UF_N C4511 1 2 SATA_HDD_R2D_C_N IN
PAGE TITLE
0.01UF 10% 16V CERM 402 SATA Connectors

516S0616 2 1 C4510 1 2
DRAWING NUMBER SIZE
72 7 SATA_HDD_R2D_P 72 SATA_HDD_R2D_UF_P SATA_HDD_R2D_C_P 20 72
PLACEMENT_NOTE=Place FL4501 close to J4501 0.01UF 10% 16V CERM 402

IN
REVISION
R
C.0.0
45 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
POR IS PLASTIC USB CONNECTOR PARTS BUT METAL PART’S SCHEMATIC AND CAD SYMBOLS
HAVE BEEN USED AS ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch USB PORT A (FRONT PORT)
PLACEMENT_NOTE=NEAR J4600
CRITICAL CRITICAL
L4605
U4690 FERR-220-OHM-2.5A
TPS2064DGN
C 8 =PP5V_S3_EXTUSB 2 IN
MSOP
OUT1 7 PP5V_S3_RTUSB_A_ILIM
1
0603
2 PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm OMIT
C
8
MIN_NECK_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm CRITICAL
20 OUT USB_EXTA_OC_L OC1* VOLTAGE=5V VOLTAGE=5V
1
C4605
3
EN1 OUT2 6 PP5V_S3_RTUSB_B_ILIM
0.01uF
J4600
MIN_LINE_WIDTH=0.5 mm PLACEMENT_NOTE=NEAR J4600 USB-K83
USB_EXTB_OC_L 5 20%
20 OUT OC2* MIN_NECK_WIDTH=0.5 mm 16V CRITICAL F-RT-TH
VOLTAGE=5V 2
4
EN2
CERM
402
L4600 5
90-OHM
6
DLP0NS
GND TPAD SYM_VER-1
1 9 73 USB_EXTA_MUXED_N 4 3 73 CONN_USB_EXTA_N
NOSTUFF CRITICAL CRITICAL
1
1 1
C4690 C4691 1 1 1 1 2
10UF 0.1UF C4695 C4696 C4617 C4616
20% 20% 10UF 100UF 10UF 100UF 73 USB_EXTA_MUXED_P 1 2 73 CONN_USB_EXTA_P 3
6.3V 10V 20% 20%
2 2 20% 20%
X5R CERM 6.3V
6.3V
6.3V
6.3V
4
2 2 2 2
603 402 X5R POLY-TANT X5R POLY-TANT
603 CASE-B2-SM 603 CASE-B2-SM 2 5 3 4
NC
IO
NC
IO
We can remove C4690 later if the output cap of the 5V_S5 regulator is close enough. 7
6 VBUS
8
1 GND
514-0689
63 IN =USB_PWR_EN CAN NOSTUFF C4696 AND C4616 AFTER CHARACTERIZATION
D4600
RCLAMP0502N
SLP1210N6
CRITICAL NOSTUFF
PLACEMENT_NOTE=NEAR J4610
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
Place L4600 and L4605 at connector pin
1 2 PP5V_S3_RTUSB_B_F
0603 MIN_NECK_WIDTH=0.5 mm
B USB/SMC Debug Mux

1
C4615
0.01uF
20%
VOLTAGE=5V
B
16V
2
CERM
402
OMIT
CRITICAL
8 =PP3V42_G3H_SMCUSBMUX
J4610
USB-K83
SMC_DEBUG_YES F-RT-TH
1
1 R4650 PLACEMENT_NOTE=NEAR J4610 5
C4650
10K CRITICAL
0.1UF 6
5%
20%
10V
1/16W L4610
2 MF-LF 90-OHM
CERM
402 DLP0NS
402 2 SYM_VER-1 1
USB_EXTB_N 4 3 73 CONN_USB_EXTB_N 2
9
73 20 BI
73 CONN_USB_EXTB_P 3
VCC
4
5
SMC_DEBUG_YES 1
38 37 36 SMC_RX_L M+ Y+ 73 20 USB_EXTB_P 1 2
IN BI
SMC_TX_L 4 2
38 37 36 OUT M- U4650 Y- 7
PI3USB102ZLE 2 5 3 4 8
USB_EXTA_P 7 TQFN
D+
NC
IO
NC
IO
73 20 BI
73 20 USB_EXTA_N 6 D- 6 VBUS
BI
CRITICAL 514-0689
1 GND
8 OE* SEL 10 USB_DEBUGPRT_EN_L 36
IN
GND SEL=0 Choose SMC
SEL=1 Choose USB
D4610
3
RCLAMP0502N
SLP1210N6
CRITICAL NOSTUFF
SMC_DEBUG_NO
A 1
R4651
0
2
PAGE TITLE
5%
1/16W
MF-LF
SMC_DEBUG_NO
R4652
USB PORT B (BACK PORT) External USB Connectors
402 DRAWING NUMBER SIZE
0
1 2

5% REVISION
1/16W
MF-LF
402
R
C.0.0
46 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
37 7 PP3V3_S5_AVREF_SMC
37 8 =PP3V3_S5_SMC
D D
1 1 1 1 1
C4902 C4903 C4904 C4905 C4906
22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 10V 10V 10V 10V
CERM 2 2 CERM 2 CERM 2 CERM 2 CERM
805 402 402 402 402
U4900 PLACEMENT_NOTE=PLACE C4907 CLOSE TO U4900 PIN E1
37 OUT SMC_EXCARD_PWR_EN B12 P10 H8S2117 P60 L13 SMC_PM_G2_EN
OUT 7 57 63
37 OUT SMC_RSTGATE_L A13 P11 LGA-HF P61 K12

NC SMC_VCL
ALL_SYS_PWRGD A12 P12 (1 OF 3) P62 K11 R4999
63 25 IN NC 4.7
63 IN RSMRST_PWRGD B13 P13 P63 J12
NC 1 2 PP3V3_S5_SMC_AVCC
1
MIN_LINE_WIDTH=0.25 MM C4907
D11 P14 OMIT P64 K13 SMC_ADAPTER_EN 5%
M12
H10
L11
21 32 37
NC OUT MIN_NECK_WIDTH=0.20 MM
0.47UF
B1
M1
E1
1/16W VOLTAGE=3.3V
1 10%
21 OUT PM_RSMRST_L C13 P15 P65 J10
NC MF-LF C4920 6.3V
402 2
59 IMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L 37 0.1UF CERM-X5R
OUT IN 20% 402
10V AVCC VCC VCL AVREF
21 OUT PM_PWRBTN_L D10 P17 P67 H12 SMC_BIL_BUTTON_L IN 37 CERM 2
1 1
402 R4909 R4901
37 OUT ESTARLDO_EN D13 P20 P70 N10 SMC_CPU_ISENSE IN 41
U4900 NC E5
NC 10K 10K
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PIN M12 H8S2117 5% 5%
NC E11 P21 P71 M11 SMC_CPU_VSENSE

IN 40
LGA-HF 1/16W 1/16W
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PIN M12 MF-LF MF-LF
NC D12 P22 P72 L10 SMC_GPU_ISENSE

IN 37 402
2 2
402
(3 OF 3)
NC F11 P23 P73 N11 SMC_GPU_VSENSE IN 37
OMIT MD1 D1 SMC_MD1 IN 38
37 SMC_P24 E13 P24 P74 N12 SMC_DCIN_ISENSE
IN 41
MD2 H1 SMC_KBC_MDE
NC E12 P25 P75 M13 SMC_PBUS_VSENSE IN 40 38 37 IN SMC_RESET_L D3 RES*
37 SMC_P26 F13 P26 P76 N13 SMC_BATT_ISENSE IN 41
37 SMC_XTAL A3 XTAL
NC E10 P27 P77 L12 SMC_NB_MISC_ISENSE
IN 37
37 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI
IN 38
73 38 19 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L

OUT 21
73 38 19 BI LPC_AD<1> D9 P31 P81 B6

NC
73 38 19 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 19 38
ETRST H3 SMC_TRST_L
IN 38
C 73 38 19
73 38 19
BI
IN
LPC_AD<3>
LPC_FRAME_L
B7
A8
P33
P34
P83
P84
D5
A6
LPC_PWRDWN_L
SMC_TX_L
IN
OUT
19 38
35 36 37 38 AVSS L9
1 1 1
NO STUFF C
25 SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L 35 36 37 38 VSS R4902 R4998 R4903
IN IN
10K 10K 0
73 25 IN LPC_CLK33M_SMC D7 P36 P86 C6 (OC) SMB_MGMT_CLK BI 39 5% 5% 5%
D2
L3
F10
B11
C5
1/16W 1/16W 1/16W
38 19 BI LPC_SERIRQ D6 P37 XW4900 MF-LF MF-LF MF-LF
P90 J4 SMC_ONOFF_L IN 37 44 SM
2
402
2
402
2
402
NC D4 P40 P91 G3 SMC_BC_ACOK IN 37 55 2 1
37 SMC_P41 A5 P41 P92 H2 SMC_BS_ALRT_L IN 37
39 BI SMB_MGMT_DATA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 7 21 32 63 67
46 OUT SMS_ONOFF_L A1 P43 P94 H4 PM_SLP_S4_L

IN 7 21 37 63
NC C2 P44 P95 G4 PM_SLP_S5_L IN 37 NOTE: P94 and P95 are shorted, P95 could be spare.
GND_SMC_AVSS 37 40 41
NC B2 P45 P96 F4 PM_CLK32K_SUSCLK
IN 25 73
37 OUT SMC_GFX_THROTTLE_L C1 P46 P97 F1 (OC) SMB_0_S0_DATA BI 39
9 OUT SMC_SYS_KBDLED C3 P47
38 37 36 35 OUT SMC_TX_L G2 P50

38 37 36 35 IN SMC_RX_L F3 P51
39 BI SMB_0_S0_CLK (OC) E4 P52
U4900
(DEBUG_SW_1) 37 SMC_PA0 N3 PA0 H8S2117 PE0 K1 SMC_CASE_OPEN
IN 37
(DEBUG_SW_2) 37 SMC_PA1 N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 37 38
25 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI

IN 37 38
35 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 OMIT PE3 J1 SMC_TDO OUT 37 38
28 27 21 BI MEM_EVENT_L (OC) N2 PA4 PE4 K4 SMC_TMS

IN 37 38
B 55 BI
37 SMC_PA5
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5
NC B
PF1 N5 SMC_SYS_LED
OUT 37
21 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID
IN 37 44 55
NC B8 PB0 PF3 L5
NC
21 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5
NC
34 7 IN SMC_ODD_DETECT B9 PB2 PF5 N4 SMC_MCP_SAFE_MODE OUT 37
37 SMC_PB3 (See below) A10 PB3 PF6 L4

NC
37 IN SMC_EXCARD_CP C10 PB4 PF7 M4
NC
NC B10 PB5
PG0 M8
NC
37 IN SMC_EXCARD_OC_L C11 PB6
PG1 N7 =SMC_SMS_INT
IN 37 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
37 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMB_BSA_DATA BI 39 If SMS interrupt is not used, pull up to SMC rail.
43 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMB_BSA_CLK
BI 39
37 OUT SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMB_A_S3_DATA BI 39
37 OUT SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMB_A_S3_CLK

BI 39
37 OUT SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMB_B_S0_DATA

BI 39
43 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMB_B_S0_CLK BI 39
37 IN SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT
OUT 37
37 IN SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP
OUT 37
37 IN SMC_FAN_3_TACH J13 PC7
PH2 J2 SMC_PH2 37
46 IN SMS_X_AXIS M10 PD0 PH3 A4 ALS_GAIN

OUT 37
46 IN SMS_Y_AXIS N9 PD1 PH4 B3

NC
46 IN SMS_Z_AXIS K10 PD2 PH5 C4
NC
37 IN SMC_ANALOG_ID L8 PD3
37 IN SMC_NB_CORE_ISENSE M9 PD4
A 37
37
IN
IN
SMC_NB_DDR_ISENSE
ALS_LEFT
N8
K9
PD5
PD6 SYNC_MASTER=K24_MLB SYNC_DATE=04/02/2009 A
37 ALS_RIGHT L7 PD7 PAGE TITLE
IN
1 C4950 SMC
0.033UF
DRAWING NUMBER SIZE
2
10%
16V
1 C4951
X5R 0.033UF
402 10%
REVISION
PLACEMENT_NOTE=PLACE C4950 CLOSE TO U4900 PIN M10
PLACEMENT_NOTE=PLACE C4951 CLOSE TO U4900 PIN N9
PLACEMENT_NOTE=PLACE C4952 CLOSE TO U4900 PIN K10
2 16V
X5R
1 C4952 R
C.0.0
402 0.033UF
10%
16V
2 X5R
402
SMC_PB3: THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SMC_IG_THROTTLE_L for MG systems.

49 OF 109
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
SMC FSB to 3.3V Level Shifting
36 SMC_BIL_BUTTON_L NC_SMC_BIL_BUTTON_L 37 8 =PP3V3_S0_SMC

MAKE_BASE=TRUE
36 SMC_FAN_1_CTL NC_SMC_FAN_1_CTL
MAKE_BASE=TRUE
1 1
36 SMC_FAN_2_CTL NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
R5061 R5060
100K 10K
36 SMC_FAN_3_CTL NC_SMC_FAN_3_CTL 5% 5%
MAKE_BASE=TRUE 1/16W 1/16W
SMC Reset "Button" / Brownout Detect MF-LF MF-LF
36 SMC_GFX_THROTTLE_L SMC_IG_THROTTLE_L 21 402 402
2 2
MAKE_BASE=TRUE TO SMC
36 ESTARLDO_EN NC_ESTARLDO_EN SMC_PROCHOT_3_3_L OUT 36

37 36 8 =PP3V3_S5_SMC MAKE_BASE=TRUE
55 37 36 SMC_BC_ACOK =CHGR_ACOK 56 CPU_PROCHOT_BUF

6
D
MAKE_BASE=TRUE
D C5000
1 1
R5000
36 SMC_P24 TP_SMC_P24
MAKE_BASE=TRUE
D Q5060
0.1uF 1K SMC_P26 TP_SMC_P26 DMB53D0UV
CRITICAL 36
20%
5% MAKE_BASE=TRUE
10V U5000 SOT-563
CERM
2
NCP303LSN
1/16W
SMC_P41 TP_SMC_P41 3 2 G
402
SOT23-5-HF
MF-LF
402
36
MAKE_BASE=TRUE
TO CPU
R5062
2
36 SMC_NB_CORE_ISENSE SMC_MCP_CORE_ISENSE 41 CPU_PROCHOT_L 1

3.3K
2 CPU_PROCHOT_L_R 5 Q5060
70 14 10 BI
SMC_MANUAL_RST_L 5 CD OUT 1 SMC_RESET_L
OUT 36 38 MAKE_BASE=TRUE
5%
DMB53D0UV
SOT-563
NOSTUFF NC 4 NC IN 2 36 SMC_NB_DDR_ISENSE SMC_MCP_DDR_ISENSE 41 1/16W
MF-LF S
4
1
R5001
GND MAKE_BASE=TRUE
402
C5001
1
36 ALS_LEFT SMC_CPU_FSB_ISENSE 41 1
0
3
MAKE_BASE=TRUE
6 D Q5059
0.01UF
SILK_PART=SMC_RST 5%
1/10W
10% Q5032 36 SMC_GPU_VSENSE SMC_MCP_VSENSE 40 SSM6N15FEAPE
MF-LF
16V
2 MAKE_BASE=TRUE SOT563
CERM SSM3K15FV D 3
603
402
2
SOD-VESM-HF 36 SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN
MAKE_BASE=TRUE
36 SMC_RSTGATE_L TP_SMC_RSTGATE_L S G 2
MAKE_BASE=TRUE 1
36 SMC_PB3 NC_SMC_PB3 SMC_PROCHOT IN 36
37 36 8 =PP3V3_S5_SMC
1 G S 2
MAKE_BASE=TRUE
36 ALS_GAIN NC_ALS_GAIN
5
U5001 MAKE_BASE=TRUE
SN74LVC1G02 36 SMC_ANALOG_ID NC_SMC_ANALOG_ID

1
44 SMC_TPAD_RST_L SOT553-5 MAKE_BASE=TRUE 70 14 10 OUT PM_THRMTRIP_L
4 SMC_TPAD_RST ALS_RIGHT NC_ALS_RIGHT

36
MAKE_BASE=TRUE
2
44 37 36 SMC_ONOFF_L 02 3 D Q5059
=PP3V3_S5_SMC 8 36 37
3 SSM6N15FEAPE
SOT563
R5095 1
0
R5010
36 SMC_EXCARD_OC_L 1 2 EXCARD_OC_L 20 10K
OUT IN
5%
4
S G 5
5% 1/16W
SMC AVREF Supply 1/16W
MF-LF
MF-LF
402 SMC_THRMTRIP 36
402
2 IN
C CRITICAL
VR5020
36 OUT =SMC_SMS_INT SMS_INT_L
MAKE_BASE=TRUE
IN C
REF3333
8 =PPVIN_S5_SMCVREF PP3V3_S5_AVREF_SMC 7 36 37 36 8 =PP3V3_S5_SMC
SOT23-3
1 IN OUT 2 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
GND 36 SMC_PA0 R5091 100K 1 2

1
C5026 5% 1/16W MF-LF 402
3
36 SMC_PA1 R5092 100K 1 2
0.01UF
5% 1/16W MF-LF 402
10%
2
16V
CERM
MCP_SAFE_MODE SIGNAL TO SUPPORT ROM FAILURE OVERRIDE
402
1 1
C5020 C5025 RADAR 5925345
44 37 36 SMC_ONOFF_L R5070 10K 1 2
0.47UF 10uF
5% 1/16W MF-LF 402
10% 20%
55 44 36 SMC_LID R5071 100K 1 2
6.3V 6.3V
2 2 5% 1/16W MF-LF 402
CERM-X5R X5R 10K
SMC_PH2 R5072
402 603 R5011 36 1 2
5% 1/16W MF-LF 402

0 38 36 35 SMC_TX_L R5073 10K 1 2
21 MCP_SPKR 1 2 SMC_MCP_SAFE_MODE IN 36 5% 1/16W MF-LF 402

GND_SMC_AVSS 36 40 41 38 36 35 SMC_RX_L R5074 100K 1 2
MIN_LINE_WIDTH=0.4 mm 5% 5% 1/16W MF-LF 402
MIN_NECK_WIDTH=0.2 mm 1/16W
VOLTAGE=0V MF-LF
402
TABLE_ALT_HEAD
R5077 10K
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 38 36 SMC_TMS 1 2
PART NUMBER 5% 1/16W MF-LF 402

38 36 SMC_TDO R5078 10K 1 2
TABLE_ALT_ITEM
5% 1/16W MF-LF 402

353S1381 353S1912 ALL ISL60002-33, INTERSIL 38 36 SMC_TDI R5079 10K 1 2
5% 1/16W MF-LF 402

38 36 SMC_TCK R5080 10K 1 2
5% 1/16W MF-LF 402

55 37 36 SMC_BC_ACOK R5087 470K 1 2
5% 1/16W MF-LF 402

36 SMC_GFX_OVERTEMP_L R5050 10K 1 2
5% 1/16W MF-LF 402
B 36 SMC_BS_ALRT_L R5076 100K 1 2

B
5% 1/16W MF-LF 402
36 SMC_FAN_1_TACH R5051 10K 1 2
5% 1/16W MF-LF 402

36 SMC_FAN_2_TACH R5052 10K 1 2
5% 1/16W MF-LF 402

SMC_FAN_3_TACH R5053 10K 1 2
36
System (Sleep) LED Circuit 36 SMC_GPU_ISENSE R5054 10K 1 2
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402

36 SMC_NB_MISC_ISENSE R5055 10K 1 2
5% 1/16W MF-LF 402
8 =PP5V_S3_SYSLED
36 32 21 SMC_ADAPTER_EN R5085 10K 1 2
SMC Crystal Circuit Debug Power "Button" R5086 10K

5% 1/16W MF-LF 402
36 SMC_CASE_OPEN 1 2
5% 1/16W MF-LF 402
1 1
R5031 R5030 36 SMC_EXCARD_CP R5088 10K 1 2
523 80.6 C5010 5% 1/16W MF-LF 402

1% 1% 15pF
1/16W 1/16W
1 2 R5090 100K
MF-LF MF-LF 36 SMC_XTAL SMC_ONOFF_L
OUT 36 37 44 36 PM_SLP_S5_L 1 2
402 402 5% 1/16W MF-LF 402

2 2 PM_SLP_S4_L
NOSTUFF NOSTUFF 63 36 21 7
5%
CRITICAL 50V
SYS_LED_ILIM 1
1 1
CERM R5015 R5016

Y5010 402
PLACE R5015,R5001 ON BOTTOM SIDE
20.00MHZ
0 0 PLACE R5016 ON TOP SIDE
2 SILK_PART=PWR_BTN 5% 5% 37 8 =PP3V3_S0_SMC
5X3.2-SM
1/10W 1/10W
2
C5011 MF-LF MF-LF
SOD
2SA2154MFV-YAE 15pF 603 603
SYS_LED_L_VDIV 2 2
SILK_PART=PWR_BTN
1 SMC_EXTAL 1 2
Q5030 36
R5089 10K
36 SMC_PA5 1 2
5% 1/16W MF-LF 402

1 3 5%
R5032 50V
CERM
1.47K
SYS_LED_ANODE 402
1%
OUT 34
1/16W
MF-LF
402
2
SYS_LED_L
A Q5033
PAGE TITLE
SSM3K15FV D 3
SOD-VESM-HF SMC Support
DRAWING NUMBER SIZE
36 SMC_SYS_LED
IN
REVISION
1 G S 2
R
C.0.0
50 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
D 38 8
8
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
31 32
D
1 2 LPC_CLK33M_LPCPLUS IN 25 73
73 36 19 BI LPC_AD<0> 3 4 LPC_AD<2> BI 19 36 73
73 36 19 BI LPC_AD<1> 5 6 LPC_AD<3> BI 19 36 73
7 8
73 38 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB OUT 38
73 38 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 38 73
73 36 19 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 38
36 19 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 19 36
37 36 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 19 36
25 IN DEBUG_RESET_L 19 20 SMC_TDI OUT 36 37
Alternate SPI ROM Support 36

37
36
OUT
IN
SMC_TDO
SMC_TRST_L
21
23
22
24
SMC_TCK
SMC_RESET_L
OUT
OUT
36 37
36 37
SMC_MD1 25 26 SMC_NMI
36 OUT OUT 36
37 36 35 IN SMC_TX_L 27 28 SMC_RX_L OUT 35 36 37

29 30 LPCPLUS_GPIO OUT 18
33 34
48 38 8 =PP3V3_S5_ROM
R5190 1 516S0573
10K
5%
1/16W
MF-LF
402 2
73 48 38 21 IN SPI_CLK_R
C 73 48 38 21 IN SPI_MOSI_R
C
1
R5191
10K
5%
1/16W
MF-LF LPCPLUS_NOT
402 2
R5146
0
1 2 SPI_MLB_CS_L
5% PLACEMENT_NOTE=PLACE NEXT TO U5110
1/16W =PP3V3_S5_ROM 8 38 48
MF-LF
402
1
38 8 =PP3V3_S5_LPCPLUS LPCPLUS R5144
20K
5%
1 C5124 1/16W
0.1UF MF-LF
1 20% 402 2
R5140 LPCPLUS 10V
2
5
CERM
100K SEL HIGH OUTPUTS TO B1(ON BOARD ROM) 402
5% VCC
1/16W SEL LOW OUTPUTS TO B0 (FRANKCARD ROM)
MF-LF
402
U5110
2 NC7SB3157P6XG
21 BI =SPI_CS1_R_L_USE_MLB 38 SPIROM_USE_MLB 6 S SC70 B1 1 SPI_MLB_CS_L OUT 38 4838 48
MAKE_BASE=TRUE
CRITICAL
73 21 IN SPI_CS0_R_L 4 A B0 3 SPI_ALT_CS_L OUT 38
GND
Pull-up on debug card
2
B B
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO

LPCPLUS
R5156
0
73 38 OUT SPI_ALT_CLK 1 2 SPI_CLK_R IN 21 38 48 73
5%
1/16W LPCPLUS
MF-LF
402 R5157
0
73 38 OUT SPI_ALT_MOSI 1 2 SPI_MOSI_R IN 21 38 48 73
5% PLACEMENT_NOT=PLACENEXT TO WHERE IT BRANCHES INTO TWO

LPCPLUS 1/16W
MF-LF
R5158 402
0
73 38 IN SPI_ALT_MISO 1 2 SPI_MISO OUT 21 48 73
5%
1/16W
A MF-LF
402
PLACEMENT_NOT=PLACE NEXT TO WHERE IT BRANCHES INTO TWO

PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER SIZE

REVISION
R
C.0.0
51 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP79 SMBUS "0" CONNECTIONS SMC "0" SMBus Connections SMC "A" SMBus Connections
D NOTE: SMC RMT bus remains powered and may be active in S3 state
D
8 =PP3V3_S0_SMBUS_MCP_0 8 =PP3V3_S0_SMBUS_SMC_0_S0 8 =PP3V3_S3_SMBUS_SMC_A_S3
1 1 1 1 1 1
MCP79 R5200 R5201 SO-DIMM "A" SMC R5250 R5251 MCP Temp SMC R5270 R5271 TRACKPAD
2.0K 2.0K 4.7K 4.7K 1K 1K
U1400 5% 5% J3100 U4900 5% 5% EMC1403-5: U5535 U4900 5% 5% J5800
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0xA0 Read: 0xA1) (MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99) (MASTER) MF-LF MF-LF (Write: 0x90 Read: 0x91)
402 402 402 402 402 402
2 2 2 2 2 2
73 21 13 SMBUS_MCP_0_CLK =I2C_SODIMMA_SCL 27 36 SMB_0_S0_CLK 75 SMBUS_SMC_0_S0_SCL =I2C_MCPTHMSNS_SCL 42 36 SMB_A_S3_CLK SMBUS_SMC_A_S3_SCL =I2C_TPAD_SCL 45

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
73 21 13 SMBUS_MCP_0_DATA =I2C_SODIMMA_SDA 27 36 SMB_0_S0_DATA 75 SMBUS_SMC_0_S0_SDA =I2C_MCPTHMSNS_SDA 42 36 SMB_A_S3_DATA SMBUS_SMC_A_S3_SDA =I2C_TPAD_SDA 45

MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
SO-DIMM "B" SENSOR ADC

J3200 U6000
(Write: 0xA2 Read: 0xA3) (WRITE: 0X10 READ: 0X11)
1
R5203
0 =I2C_SODIMMB_SCL 28 =I2C_SMC_ADCS_SCL 47
MCPSMC_DIGITEMP_YES 5%
1/16W
MF-LF =I2C_SODIMMB_SDA 28 =I2C_SMC_ADCS_SDA 47
2 402
1MCPSMC_DIGITEMP_YES SENSOR ADC CAN ONLY WORK IN S0 AS IT HAS I2C BUS PULLED UP TO S0 POWER RAIL
R5204
0
5%
1/16W
Mikey
MF-LF U6880
2 402 (WRITE: 0X72 READ: 0X73) SMC "Battery A" SMBus Connections SMC "B" SMBus Connections
C 39 I2C_MIKEY_SCL_R =I2C_MIKEY_SCL 39 54
C
MAKE_BASE=TRUE 8 =PP3V42_G3H_SMBUS_SMC_BSA 8 =PP3V3_S0_SMBUS_SMC_B_S0
39 I2C_MIKEY_SDA_R =I2C_MIKEY_SDA 39 54
MAKE_BASE=TRUE
1 1 1 1
SMC R5280 R5281 BATTERY SMC R5260 R5261 CPU Temp

1K 1K 2.0K 2.0K
U4900 5% 5% J6950 U4900 5% 5% EMC1403-5: U5515
1/16W 1/16W 1/16W 1/16W
(MASTER) MF-LF MF-LF (See Table) (MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99)
MCP79 SMBUS "1" CONNECTIONS 402

2 2
402 402
2 2
402
36 SMB_BSA_CLK SMBUS_SMC_BSA_SCL =SMBUS_BATT_SCL 55 39 36 SMB_B_S0_CLK 75 SMBUS_SMC_B_S0_SCL =I2C_CPUTHMSNS_SCL 42

36 SMB_BSA_DATA SMBUS_SMC_BSA_SDA =SMBUS_BATT_SDA 55 39 36 SMB_B_S0_DATA 75 SMBUS_SMC_B_S0_SDA =I2C_CPUTHMSNS_SDA 42

8 =PP3V3_S0_SMBUS_MCP_1 MAKE_BASE=TRUE MAKE_BASE=TRUE
MCPSMC_DIGITEMP_NO
1
MCPSMC_DIGITEMP_NO
MCP79 R5230
1 R5231
2.0K
Mikey Battery Charger
U1400 2.0K 5% U6880
5% 1/16W ISL6258A - U7000 SMC "B" SMBUS SIGNALS ALSO GET CONNECTED TO MCP SMBUS 1 CONNECTIONS(SEE LEFT SIDE)
(MASTER) 1/16W MF-LF MCPSMC_DIGITEMP_NO (WRITE: 0X72 READ: 0X73)
(SLAVE: WRITE:0XE0 READ:0XE1) MF-LF
2
402
R5232 Battery (Write: 0x12 Read: 0x13)
402
2
1
0 2
73 21 SMBUS_MCP_1_CLK =I2C_MIKEY_SCL 39 54 Battery Manager - (Write: 0x16 Read: 0x17)
=SMBUS_CHGR_SCL 56
5%39 I2C_MIKEY_SCL_R Battery Temp - (Write: 0x90 Read: 0x91)
73 21 SMBUS_MCP_1_DATA 1/16W =I2C_MIKEY_SDA 39 54
MF-LF =SMBUS_CHGR_SDA 56
402
R5233
1
0 2
39 I2C_MIKEY_SDA_R
5%
1/16W
MF-LF
402 MCPSMC_DIGITEMP_NO
B SMC "Management" SMBus Connections B

1MCPSMC_DIGITEMP_YES The bus formerly known as "Battery B"
R5235
0 8 =PP3V3_S3_SMBUS_SMC_MGMT
5%
1/16W
MF-LF
2 402
1 1
SMC R5290 R5291 Vref DACs

1 4.7K 4.7K
R5234 U4900 5% 5% U2900
0 1/16W 1/16W
MCPSMC_DIGITEMP_YES 5% (MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99)
1/16W 402
2 2
402
MF-LF
2 402 36 SMB_MGMT_CLK 75 SMBUS_SMC_MGMT_SCL =I2C_VREFDACS_SCL 26
SMC 36 SMB_MGMT_DATA
MAKE_BASE=TRUE
75 SMBUS_SMC_MGMT_SDA =I2C_VREFDACS_SDA 26
U4900 MAKE_BASE=TRUE
(MASTER)
SMC "B" SMBUS
SMB_B_S0_CLK 36 39
Margin Control
SMB_B_S0_DATA 36 39 U2901
(Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL 26
=I2C_PCA9557D_SDA 26
MCP SMBUS1 ACTS AS SLAVE DEVICE FOR MCPSMC_DIGITEMP_YES STUFFED
PAGE TITLE
K84 SMBUS CONNECTIONS

DRAWING NUMBER SIZE

REVISION
R
C.0.0
52 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Voltage Sense / Filter
XW5309 R5309
8 =PPVCORE_S0_CPU_VSENSE SM
4.53K
1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE OUT 36
PLACEMENT_NOTE=Place near U1000 center 1%

1/16W
1
MF-LF C5309
402
0.22UF
20%
6.3V
2
X5R
402
D GND_SMC_AVSS 36 37 40 41 D
Place RC close to SMC
MCP Voltage Sense / Filter
XW5359 R5359
8 =PPVCORE_S0_MCP_VSENSE SM
4.53K
1 2 MCPVSENSE_IN 1 2 SMC_MCP_VSENSE OUT 37
PLACEMENT_NOTE=Place near U1400 center 1%

1/16W
1
MF-LF C5359
402
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS 36 37 40 41
C C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3169CZ
SOT-963
N-CHANNEL
6 PBUSVSENS_EN_L
D
1
R5316
100K
63 =PBUSVSENS_EN 2 G
IN 1%
S 1/16W
MF-LF
Enables PBUS VSense 402
1 2
divider when high.

3 PPBUS_G3HRS5_VSENSE
D VOLTAGE=18.5V
1
R5385
27.4K
5 G 1%
S 1/16W
8 =PPBUS_G3HRS5 MF-LF
402 RTHEVENIN = 4573 OHMS
4 2
P-CHANNEL SMC_PBUS_VSENSE 36
B R5315
1
1
OUT
B
100K
1%
R5386 1
C5385
1/16W 5.49K
0.22UF
MF-LF 1%
20%
402 1/16W
2 6.3V
MF-LF 2
X5R
402
2 402
PBUSVSENS_EN_L_DIV
PAGE TITLE
VOLTAGE SENSING
DRAWING NUMBER SIZE

REVISION
R
C.0.0
53 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP VCore Current Sense Filter
R5416
4.53K
60 MCPCORES0_IMON 1 2 SMC_MCP_CORE_ISENSE 37
OUT
1%
1/16W
1
MF-LF C5472
402
0.22UF
20%
6.3V
D
2
X5R
D 402
MCP MEM VDD Current Sense
8 =PP3V3_S0_MCPDDRISNS
64 P1V5_S0_KELVIN
IN
MEM_SENSE
P1V5_S0_SENSE
MEM_SENSE
64 IN U5400 1
C5400
1 5 OPA348
0.1uF
1 SC70-5 20%
R5410 MEM_SENSE 4
2
10V
CERM
MEM_SENSE 0 C5434 402
5%
1/16W 0.1UF 3 MCP MEM VDD Current Sense Filter
MF-LF 2
1 2
402
2 MEM_SENSE
Gain: 50x
10%
P1V5_S0_SENSE_E 16V R5417
X5R 4.53K
402 1 2 SMC_MCP_DDR_ISENSE
Q5401 MEM_SENSE
OUT 37
2 2SA2154MFV-YAE R5411 1% MEM_SENSE
SOD 1/16W
MEM_SENSE 0 MF-LF 1
C5435
1 P1V5_S0_SENSE_B 1 2 P1V5_S0_SENSE_AMP 402
0.22UF
C 3
5%
1/16W
MF-LF
402
2
20%
6.3V
X5R
402
C
P1V5_S0_SENSE_C
1
R5412 Place RC close to SMC
118
1% MEM_SENSE
1/16W
MF-LF
402
2
CPU 1.05V AND CPU VCORE HIGH SIDE CURRENT SENSE

8 =PP3V3_S0_CPUVTTISNS
1P05_HIGH_SIDE_SENSE
R5492 1
C5417 CPU VCore Load Side Current Sense / Filter
0.01
1P05_HIGH_SIDE_SENSE 0.1uF 1P05_HIGH_SIDE_SENSE Place RC close to SMC
0.5% 20%
3
1W 10V
2
MF CERM R5471
0612-1 402 V+
6.19K
8 =PPCPUVCORE_VTT_ISNS_R 1 2 =PPCPUVCORE_VTT_ISNS 8 1P05_HIGH_SIDE_SENSE 59 IMVP6_IMON 1 2 SMC_CPU_ISENSE 36
IN OUT IN OUT
3 4
U5402 R5418 1%
INA213 4.53K 1/16W
76 ISNS_CPUVTT_N 5 6 CPUVTT_IOUT SMC_CPU_FSB_ISENSE 1

IN- SC70 OUT 1 2
OUT 37 MF-LF
402
R5480
1
C5470
0.22UF
1% 1P05_HIGH_SIDE_SENSE 17.4K
20%
1/16W 1%
76 ISNS_CPUVTT_P 4 1 1 6.3V
IN+ REF MF-LF C5436 1/16W 2
X5R
402 MF-LF
0.22UF 402
402
20% 2
GND 2
6.3V
X5R
2
402
B Place RC close to SMC

B
DC-IN (BMON) CURRENT SENSE DC-IN (AMON) CURRENT SENSE
R5401 R5481
4.53K 4.53K
56 CHGR_BMON 1 2 SMC_BATT_ISENSE 36 56 CHGR_AMON 1 2 SMC_DCIN_ISENSE 36
IN OUT IN OUT
1% 1%
1/16W 1/16W
1 1
MF-LF C5490 MF-LF C5487
402 402
0.22UF 0.22UF
20% 20%
6.3V 6.3V
2 X5R
2
X5R
402 402
GND_SMC_AVSS 36 37 40 41 GND_SMC_AVSS 36 37 40 41
A PLACE R5401 AND C5490 CLOSE TO SMC

PAGE TITLE
Current Sensing
DRAWING NUMBER SIZE

REVISION
R
C.0.0
54 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
8 =PP3V3_S0_CPUTHMSNS R5515
47
1 2 PP3V3_S0_CPUTHMSNS_R
5%
D
1/16W
D MF-LF
402
VOLTAGE=3.3V
APN 353S2571 1
VDD
1
C5515 R5516
10K
1 1
R5517
10K
0.1uF
1% 5%
76 10 CPU_THERMD_P
U5515 2
20%
10V
1/16W
MF-LF
1/16W
MF-LF
BI EMC1413 CERM
402 402
402 2 2
SIGNAL_MODOL=EMPTY DFN
C5521 1 2 DP1 THERM*/ADDR 7 CPUTHMSNS_THERM_L
DETECT CPU DIE TEMPERATURE
0.0022uF CRITICAL
10% 3 DN1 ALERT* 8 CPUTHMSNS_ALERT_L
50V
CERM
2
402 4 DP2/DN3 SMDATA 9 =I2C_CPUTHMSNS_SDA 39
CPU_THERMD_N
BI
76 10 BI
5 DN2/DP3 SMCLK 10 =I2C_CPUTHMSNS_SCL 39
BI
GND THRM_PAD
6 11
76 CPUTHMSNS_D2_P
3
SIGNAL_MODOL=EMPTY
PLACEMENT NOTE: PLACE U5515 NEAR CPU
1
C5520
Q5501 1
0.0022uF
DETECT FIN-STACK TEMPERATURE
BC846BMXXH 10%
50V
SOT732-3 2
CERM
2 402
76 CPUTHMSNS_D2_N
C C
MCP T-Diode Thermal Sensor

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
MCP_T_DIODE_SENSOR
8 =PP3V3_S0_MCPTHMSNS R5535 MCP_T_DIODE_SENSOR
47
1 2 PP3V3_S0_MCPTHMSNS_R
5% MIN_NECK_WIDTH=0.25 mm MCP_T_DIODE_SENSOR
1/16W VOLTAGE=3.3V MCP_T_DIODE_SENSOR
MF-LF APN 353S2571 1 1 R5536
1 1
R5537
402 C5535
VDD 0.1uF
10K 10K
1% 5%
76 21 BI MCP_THMDIODE_P
U5535 2
20%
10V 1/16W
MF-LF
1/16W
MF-LF
EMC1413 CERM
402 402
2 2
402
SIGNAL_MODOL=EMPTY DFN MCP_T_DIODE_SENSOR
C5522 1 2 DP1 THERM*/ADDR
7 MCPTHMSNS_THERM_L
DETECT MCP DIE TEMPERATURE 0.0022uF

10% 3 DN1 CRITICALALERT* 8 MCPTHMSNS_ALERT_L
50V
2
CERM
B 76 21 BI MCP_THMDIODE_N
402 4 DP2/DN3
5 DN2/DP3
SMDATA 9
10
=I2C_MCPTHMSNS_SDA BI 39
B
MCP_T_DIODE_SENSOR SMCLK =I2C_MCPTHMSNS_SCL
BI 39
GND THRM_PAD
6 11
MCP_T_DIODE_SENSOR
76 MCPTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
3 C5540 1
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
Q5502 1 DETECT HEAT-PIPE TEMPERATURE 10%
50V
2
BC846BMXXH CERM
SOT732-3 402
2 76 MCPTHMSNS_D2_N
MCP_T_DIODE_SENSOR
PLACEMENT_NOTE=PLACE CLOSE TO J4501 IN A CONVENIENT LOCATION
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE

REVISION
R
C.0.0
55 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PP5V_S0_FAN_RT
8 =PP3V3_S0_FAN_RT
CRITICAL
R5660 1 J5601
C 47K
78171-0004
M-RT-SM
5
C
5% NC
1/16W
R5665 MF-LF
402 2
1 5V DC
36 SMC_FAN_0_TACH 1 47K 2 7 FAN_RT_TACH 2 TACH
5% 3
1/16W
MF-LF 4
MOTOR CONTROL
402 GND
NC 6
R5661 1
100K 518S0521
5% Q5660
1
1/16W
MF-LF SSM3K15FV
G
402 2 SOD-VESM-HF
D
7 FAN_RT_PWM
3
2
36 SMC_FAN_0_CTL
B B
PAGE TITLE
Fan
DRAWING NUMBER SIZE

REVISION
R
C.0.0
56 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
KEYBOARD CONNECTOR
IC
PSOC USB CONTROLLER PIN NAME CURRENT R_SNS V_SNS POWER
CRITICAL
TMP102 V+ 10UA 2.55 KOHM 0.0255 V 0.255E-6 W J5713

80UA 0.204 V 16.32E-6 W APN 518S0637
3V3 LDO VDD 60MA MAX 10 OHM 0.6 V 36E-3 W NC 32
USB INTERFACES TO MLB TRACKPAD PICK BUTTONS VOUT 60MA MAX 0.2 OHM 0.012 V 0.72E-3 W
VDD
=PP3V3_S3_TPAD
SPI HOST TO Z2 KEYBOARD SCANNER PSOC 8MA (TYP) 1.5 OHM 0.012 V 96E-6 W IN
D 14MA (MAX) 0.021 V 294E-6 W

30
29
D
44 8
PP3V3_S3_PSOC 44 44 7 WS_KBD1
28
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W
44 7 WS_KBD2
27
44
44
44
44
44
44
44 7 WS_KBD3
26
45 7 PICKB_L
7
44 7 WS_KBD4
25
44 BUTTON_DISABLE
44 7 WS_KBD5
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
24
45 7 Z2_HOST_INTN
44 7 WS_KBD6
23
44 WS_LEFT_SHIFT_KEY
44 7 WS_KBD7
22
44 WS_LEFT_OPTION_KEY
44 7 WS_KBD8
21
44 7 WS_KBD9
20
56
55
54
53
52
51
50
49
48
47
46
45
44
43
44 7 WS_KBD10
19
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
44 7 WS_KBD11
R5714 18
113 44 7 WS_KBD12
44 WS_CONTROL_KEY 1
P2_3 P2_2 42 WS_KBD17 7 44 44 WS_KBD15_C 1 2 17
44 7 WS_KBD13
2 41 16
45 7 Z2_KEY_ACT_L P2_1 P2_0 WS_KBD16N 44
1%
1/16W 44 7 WS_KBD14
CRITICAL 15
NC
3
P4_7 P4_6 40 WS_KBD15_C 44
MF-LF
402 7 WS_KBD15_CAP
14
TP_P4_5 4
P4_5 U5701 P4_4 39 WS_KBD14 7 44
7 WS_KBD16_NUM
5 38 13
45 7 Z2_DEBUG3 P4_3 CY8C24794 P4_2 WS_KBD13 7 44
44 7 WS_KBD17
6 37 12
45 7 Z2_RESET P4_1 MLF P4_0 WS_KBD12 7 44
44 7 WS_KBD18
(SYM-VER2) R5715 11
45 7 PSOC_MISO 7
P3_7 P3_6 36 WS_KBD11 7 44
10K 44 7 WS_KBD19
44 WS_KBD16N
10
45 7 PSOC_F_CS_L 8
P3_5 APN 337S2983 P3_4 35 WS_KBD10 7 44
1 2
44 7 WS_KBD20
9 34 9
45 7 PSOC_MOSI P3_3 OMIT
P3_2 WS_KBD9 7 44
1%
1/16W 44 7 WS_KBD21
10 33 8
45 7 PSOC_SCLK P3_1 P3_0 WS_KBD8 7 44
MF-LF
402 44 7 WS_KBD22
R5710 7
45 7 Z2_MISO 11
P5_7 P5_6 32 WS_KBD7 7 44
44 7 WS_KBD23
6
45 7 Z2_CS_L 12
P5_5 P5_4 31 WS_KBD1 7 44
37 36 SMC_ONOFF_L 1
1K
2 7 WS_KBD_ONOFF_L
OUT 5
45 7 Z2_MOSI 13
P5_3 P5_2 30 WS_KBD2 7 44
5% 44 8 =PP3V42_G3H_TPAD
14 29 4
45 7 Z2_SCLK P5_1 P5_0 WS_KBD3 7 44 1/16W
P7_7
P7_0
P1_0
P1_2
P1_4
P1_6
P1_7
P1_5
P1_3
18 P1_1
C MF-LF 44 7 WS_LEFT_SHIFT_KBD
3
C
19 VSS
22 VDD
402
THRML 1
C5710 44 7 WS_LEFT_OPTION_KBD
20 D+
21 D-
2
PAD 57
0.1UF
44 7 WS_CONTROL_KBD
20% 1
15
16
17
23
24
25
26
27
28
10V
2
CERM
402
PLACEMENT_NOTE=NEAR J5713 NC 31
ISOLATION CIRCUIT F-RT-SM
FF14-30A-R11B-B-3H
TP_PSOC_SCL WS_KBD4 7 44
WS_KBD5 7 44 C5725
WS_KBD6 7 44 0.1UF
=PP3V42_G3H_TPAD 2 1
44 8
TP_PSOC_SDA
TP_ISSP_SDATA_P1_0 20%
SMC_MANUAL_RESET LOGIC
CRITICAL
10V
ISSP SDATA/I2C SDA 5 TC7SZ08AFEAPE
CERM
=PP3V3_S3_TPAD 2 SOT665
44 8 A 402
44 8 =PP3V42_G3H_TPAD
TP_PSOC_P1_3 4 WS_LEFT_SHIFT_KEY
44 1
Z2_CLKIN 7 45 U5725 Y C5758
WS_LEFT_SHIFT_KBD 1 0.1UF
44 7 B
10%
16V
3 2 X7R-CERM
402
TP_P7_7
TP_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL C5726

0.1UF
=PP3V42_G3H_TPAD
44 8 2 1
APN 311S0406
20%
DIFFERENTIAL_PAIR=USB2_TPAD CRITICAL
5 TC7SZ08AFEAPE
10V CRITICAL
R5701 =PP3V3_S3_TPAD 2 SOT665
CERM 5
SN74LVC1G10
44 8 A 402
24 44 7 WS_LEFT_SHIFT_KBD 1
A SC70
73 20 USB_TPAD_P 1 2 73 USB_TPAD_R_P 4 WS_LEFT_OPTION_KEY
Y 44 4
U5726 44 7 WS_LEFT_OPTION_KBD 3 37
5% PP3V3_S3_PSOC WS_LEFT_OPTION_KBD 1 B U5703 Y
44 44 7
1/16W B WS_CONTROL_KBD 6
44 7 C SMC_TPAD_RST_L
MF-LF
402 3
B TO MLB CONNECTOR
2
B
R5702
24
73 20 USB_TPAD_N 1 2 73 USB_TPAD_R_N
C5727 1
5% R5769 1 1
0.1UF R5770
1/16W
=PP3V42_G3H_TPAD R5771
MF-LF 2 1 33K
44 8 33K 33K
402 5%
5% 5%
1/16W
DIFFERENTIAL_PAIR=USB2_TPAD 1/16W 1/16W
20% MF-LF
CRITICAL MF-LF MF-LF
10V 402
5 TC7SZ08AFEAPE 2 402 402
CERM 2 2
=PP3V3_S3_TPAD 2 SOT665
44 8 A 402
4 WS_CONTROL_KEY
Y 44
U5727
44 7 WS_CONTROL_KBD 1
B
U5701 CHIP DECOUPLING

Alternate Parts
PLACE C5701, C5702 & C5703 PLACE C5704, C5705 & C5706 TABLE_ALT_HEAD
CLOSE TO U5701 VDD PIN 22 CLOSE TO U5701 VDD PIN 49 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TPAD BUTTONS DISABLE TABLE_ALT_ITEM
311S0406 311S0447 ALL NXP PART AS ALTERNATE
R5704
1.5 =PP3V3_S3_TPAD BUTTON_DISABLE
44 PLACE THESE COMPONENTS CLOSE TO J5800
44 PP3V3_S3_PSOC MIN_LINE_WIDTH=0.50MM
1 2 8 44
MIN_NECK_WIDTH=0.20MM THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
5%
1/16W
MF-LF
1 1 1 1 1 1
C5701 C5702 C5703 C5704 C5705 C5706 402
4.7UF 100PF 0.1UF 100PF 0.1UF 4.7UF

20% 5% 10% 5% 10% 20% Q5701
6.3V 50V 16V 50V 16V 6.3V
2 2 2 2 2 2
X5R CERM X7R-CERM CERM X7R-CERM X5R SSM3K15FV D 3
603 402 402 402 402 603
SOD-VESM-HF
A PLACEMENT_NOTE=PLACE C5702 CLOSE TO U5701 VDD PIN 22 PLACEMENT_NOTE=PLACE C5704 CLOSE TO U5701 VDD PIN 49
PAGE TITLE
THE TPAD BUTTONS WILL BE DISABLE
SMC_LID
1 G S 2 WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V
WELLSPRING 1
55 37 36 DRAWING NUMBER SIZE
IN
LID CLOSE => SMC_LID_LC < 0.50V
REVISION
R
C.0.0
57 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS
D 45 8
=PP5V_S3_TPAD
APN 152S0504
CRITICAL
- R5812,R5813,C5818 MODIFIED
D
CRITICAL
L5801
D5802
3.3UH-870MA
SOD-323
R5806
0 PP18V5_S3
2
INPUT_SW BOOST_SW PP18V5_S3_SW 1 2
7 45 IPD FLEX CONNECTOR
R5805
1/16W
MF-LF
402
VLF3010AT-SM-HF MIN_LINE_WIDTH=0.50MM
5%
0
0.50MM 5%
0.20MM MIN_NECK_WIDTH=0.20MM 1/16W

B0520WSXG
MF-LF
SWITCH_NODE=TRUE
APN 371S0313
1
402
1
1 R5812 APN 516S0689
C5818
MIN_LINE_WIDTH=0.50MM PP5V_S3_BOOSTER 1M
39PF 1%
5%
1/16W
50V CRITICAL
2 MF-LF
CERM
APN 353S1401 402
402 2 J5800
2
55560-0228
VIN 0.50MM M-ST-SM
1 0.20MM
C5819
U5805 1UF 2 1
1 L FB 4 BOOST_FB
10%
TPS61045 25V 44 7 Z2_CS_L 4 3 Z2_KEY_ACT_L 7 44
1
C5800 QFN
2
X5R
603-1 44 7 Z2_DEBUG3
6 5 Z2_RESET 7 44
0.1UF 3 DO CTRL 5 Z2_BOOST_EN 7 45
20%
8 7 PSOC_F_CS_L
10V 44 7 Z2_MOSI 7 44
2 CERM CRITICAL 1
R5813 44 7 Z2_MISO 10 9 PICKB_L 7 44
402
SW 8
71.5K
PGND
PLACEMENT_NOTE=NEAR J5800 12 11 PSOC_MISO
44 7 Z2_SCLK 7 44
GND
THRML 1%
PAD 1
1/16W
45 7 Z2_BOOST_EN
14 13 PSOC_MOSI 7 44
MF-LF
1 1 R5811
C5816 C5817 402
44 7 Z2_HOST_INTN
16 15 PSOC_SCLK 7 44
6
2
9
100K
0.1UF 2.2UF
1% 18 17 =I2C_TPAD_SDA
10% 10%
1/16W
NC 39
16V 16V
2 X7R-CERM
2 X5R
MF-LF
44 7
Z2_CLKIN 20 19 =I2C_TPAD_SCL 39
402
402 603 2
45 7 PP3V3_S3_LDO 0.50MM
22 21 0.50MM PP18V5_S3 7 45
0.20MM 0.20MM
C C
3V3 LDO FOR IPD
R5873
=PP5V_S3_TPAD 10
45 8 1 2 PP5V_S3_VR
1%
1/16W
MF-LF
402
45 7 PP3V3_S3_LDO
CRITICAL
2
2
APN 353S1364
R5836
0.2
402-HF
1/6W
1%
MF
VDD 1
C5838 1
C5854
1
C5853 VR5802 0.1UF 4.7UF
1
2.2UF MM3243DRRE 10%
16V
20%
10% 6.3V
MLF 2 2
X7R-CERM
16V PP3V3_S3_LDO_R X5R
2 X5R
1
CE VOUT 3
402 603
603 GND
B B
4
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER SIZE

REVISION
R
C.0.0
58 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
R5921 PULLS UP SEL PINS TO ENTER STANDBY MODE WHEN PIN IS NOT BEING DRIVEN BY SMC
Analog SMS
R5922
10
1 2 PP3V3_S3_SMS_FILT
5%
1/16W
8 =PP3V3_S3_SMS MF-LF
1
2
402
1
C5922 1 C5926
VDD 0.1UF 0.01UF
R5921
1
U5920 2
10%
16V
X5R
2
10%
16V
CERM
Desired orientation when
10K
5%
BMA141 11
402 402
placed on board top-side:
1/16W LGA AMUX NC
B
MF-LF
402
2 NC
7 DNC
CRITICAL
AX 10 SMS_X_AXIS OUT 36
B
36 SMS_ONOFF_L SMS_PWRDN 12 SEL0
IN
MAKE_BASE=TRUE +Y
6 SEL1 AY 9 SMS_Y_AXIS OUT 36
Front of system
+X
5 ST AZ 8 SMS_Z_AXIS 36
OUT
+Z (up)
GND
3
4
NOSTUFF
NOSTUFF NOSTUFF 1 C5925
1
C5923 1 C5924
0.033UF
0.033UF 0.033UF 10%
Circle indicates pin 1 location when placed
10% 10% 16V
16V 16V 2 X5R in correct orientation
2 X5R
2 X5R 402
402 402
C4950-C4952 CAP VALUES WILL BE USED TO GET CUT-OFF FREQUENCY OF ~146HZ
A A
PAGE TITLE
SMS
DRAWING NUMBER SIZE

REVISION
R
C.0.0
59 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEBUG_ADC DEBUG_ADC
R6003 R6004
=PP5V_S3_DEBUG_ADC_AVDD 10 PP5V_S3_DEBUG_ADC_AVDD_FILT PP5V_S3_DEBUG_ADC_DVDD_FILT 10 =PP5V_S3_DEBUG_ADC_DVDD
PLACEMENT_NOTE=PLACE NEAR Q3450 PLACEMENT_NOTE=PLACE NEAR Q4590 8 1 2 1 2 8
OMIT OMIT 5% 5%
1/16W 1/16W
XW6010 XW6020 MF-LF
402
DEBUG_ADC DEBUG_ADC DEBUG_ADC DEBUG_ADC MF-LF
402
SM SM
1 2 1 2
1 C6000 1 C6001 1 C6002 1 C6003
30 PP3V3_WLAN_F PP3V3_WLAN_F_XW 34 7 PP5V_SW_ODD PP5V_SW_ODD_XW 0.1UF 10UF 0.1UF 10UF
20% 20% 20% 20%
10V 6.3V 10V 6.3V
DEBUG_ADC DEBUG_ADC 2 CERM 2 X5R 2 CERM 2 X5R
1 1 402 603 402 603
R6010 R6020
634K PLACEMENT_NOTE=PLACE RC NEAR U6000 1M PLACEMENT_NOTE=PLACE RC NEAR U6000
12
13
21
1% 1%
1/16W DEBUG_ADC 1/16W DEBUG_ADC
MF-LF MF-LF AVDD DVDD
2
402
R6012 2 402 R6022 DEBUG_ADC
D PP3V3_WLAN_F_DIV 1
226K
2 ADC_CH0 47 PP5V_SW_ODD_DIV 1
226K
2 ADC_CH1 47
U6000
LTC2309
R6001
33
PLACEMENT_NOTE=PLACE CLOSE TO U4900
D
DEBUG_ADC 1% DEBUG_ADC 1% 47 ADC_CH0 22 CH0 AD0 14 1 2 =I2C_SMC_ADCS_SDA BI 39
QFN
1
1/16W DEBUG_ADC 1
1/16W DEBUG_ADC 23 15
R6011 MF-LF
1 R6021 MF-LF
1 47 ADC_CH1 CH1 AD1 5%
1M
402 C6012 681K
402 C6022 24
DEBUG_ADC 1/16W DEBUG_ADC
2.2UF 2.2UF 47 ADC_CH2 CH2 MF-LF
1% 1% 402
1/16W 10%
6.3V 1/16W 10%
6.3V 47 ADC_CH3 1 CH3 SDA 17 ADC_SDA R6002 PLACEMENT_NOTE=PLACE CLOSE TO U4900
MF-LF 2 MF-LF 2 33
402
X5R
402
X5R
47 ADC_CH4 2 CH4 SCL 16 ADC_SCL 1 2 =I2C_SMC_ADCS_SCL IN 39
2 402 2 402
47 ADC_CH5 3 CH5 5%
1/16W
47 ADC_CH6 4 CH6 VREF 7 ADC_VREF MF-LF
402
47 ADC_CH7 5 CH7
REFCOMP 8 ADC_REFCOMP
6 COM
DIVIDER: ~ 2/5 DEBUG_ADC DEBUG_ADC DEBUG_ADC
DIVIDER: ~ 2/3 THRM 1 1 1
I2C ADDRESS: 0X10 / 0X11 GND PAD
C6004 C6005 C6006
ADC RANGE: 0V TO 4.096V 0.1UF 10UF 2.2UF
20% 20% 20%
9
10
11
18
19
20
25
10V 6.3V 6.3V
LSB: 0.001V 2 CERM 2 X5R 2 CERM
402 603 402-LF
47 8 =PP5V_S3_DEBUG_ISNS
DEBUG_ADC DEBUG_ADC
1 C6030 1 C6040
0.1UF 0.1UF
DEBUG_ADC 20% DEBUG_ADC 20%
10V 10V
2 CERM 2 CERM
R6030 DEBUG_ADC 402 R6050 402
243 U6030 499 DEBUG_ADC
76 30 IN ISNS_AIRPORT_P 1 2 76 ISNS_AIRPORT_R_P PLACEMENT_NOTE=PLACE RC NEAR U6000 76 34 IN ISNS_ODD_P 1 2 76 ISNS_ODD_R_P PLACEMENT_NOTE=PLACE RC NEAR U6000
5 OPA330 U6040
1%
1 SC70-5 DEBUG_ADC 1% DEBUG_ADC
1/16W
+IN V+
1/16W
5 OPA330
C MF-LF
402
3
4
ISNS_AIRPORT_IOUT 1
R6034
226K
2 ADC_CH2
MF-LF
402 1
+IN V+
SC70-5
4 ISNS_ODD_IOUT
R6054
1
226K
2 ADC_CH4
C
DEBUG_ADC -IN V- 47
DEBUG_ADC
47
1% 3 1%
2
1/16W DEBUG_ADC -IN V- 1/16W DEBUG_ADC
R6031 MF-LF R6051 2 MF-LF
1 1
ISNS_AIRPORT_N 1
243
2 76 ISNS_AIRPORT_R_N
GAIN: 1239X 402 C6034 ISNS_ODD_N 1
499
2 76 ISNS_ODD_R_N
GAIN: 561X 402 C6054
76 30 IN 76 34 IN
2.2UF 2.2UF
1% 10% 1% 10%
1/16W 6.3V 1/16W 6.3V
2 X5R 2 X5R
MF-LF MF-LF
402 402 402 402
DEBUG_ADC DEBUG_ADC
DEBUG_ADC DEBUG_ADC
1 DEBUG_ADC DEBUG_ADC
1
C6032 1 R6032 R6033 C6052 1 R6052 R6053
470PF 301K 301K 470PF 280K 280K
1% 1 2 1% 1 2
10% 10%
50V 1/16W 50V 1/16W
CERM 2 MF-LF 1% DEBUG_ADC CERM 2 MF-LF 1% DEBUG_ADC
402 1/16W 402 1/16W
402 2 MF-LF 402 2 MF-LF
402 C6033 402 C6053
470PF 470PF
1 2 1 2
10% 10%
50V 50V
CERM CERM
402 402
47 8 =PP5V_S3_DEBUG_ISNS
DEBUG_ADC DEBUG_ADC
1 C6031 1 C6041
DEBUG_ADC 0.1UF 0.1UF
20% 20%
R6040 10V
2 CERM
10V
2 CERM
3.65K DEBUG_ADC 402 402
76 58 ISNS_1V5_S3_P 1 2 76 ISNS_1V5_S3_R_P PLACEMENT_NOTE=PLACE RC NEAR U6000
B IN
1%
1/16W
5
U6031
OPA330
DEBUG_ADC DEBUG_ADC B
MF-LF
402 1
+IN
SC70-5 R6044 R6060
V+ 4 226K 412 DEBUG_ADC
ISNS_1V5_S3_IOUT 1 2 ADC_CH3 47 76 34 IN ISNS_HDD_P 1 2 76 ISNS_HDD_R_P PLACEMENT_NOTE=PLACE RC NEAR U6000
DEBUG_ADC 3 1% 1% U6041 DEBUG_ADC
-IN V- 1/16W DEBUG_ADC 1/16W OPA330
R6041 MF-LF MF-LF
5
3.65K 2
GAIN: 273X 402 1 C6044 402 1
+IN
SC70-5 R6064
76 58 IN ISNS_1V5_S3_N 1 2 76 ISNS_1V5_S3_R_N
2.2UF
V+ 4
226K
10%
ISNS_HDD_IOUT 1 2 ADC_CH5 47
1%
6.3V DEBUG_ADC 3
1/16W 2 1%
MF-LF X5R -IN V- 1/16W DEBUG_ADC
402 402 R6061 2 MF-LF
DEBUG_ADC
ISNS_HDD_N
412
ISNS_HDD_R_N
GAIN: 845X 402 1 C6064
DEBUG_ADC DEBUG_ADC
1 76 34 IN
1 2 76
2.2UF
C6042 1 R6042 R6043 1% 10%
1M 1M 1/16W 6.3V
2
470PF 1% 1 2 MF-LF
X5R
10% 402 402
50V 1/16W
CERM 2 MF-LF 1% DEBUG_ADC DEBUG_ADC
402 2
402 1/16W DEBUG_ADC DEBUG_ADC
1
MF-LF
402 C6043 C6062 1 R6062 R6063
470PF 470PF 348K 348K
1% 1 2
1 2 10% 1/16W
50V
CERM 2 MF-LF 1% DEBUG_ADC
402 1/16W
10% 402 2 MF-LF
50V PLACEMENT_NOTE=PLACE NEAR D9710 402 C6063
CERM 470PF
402 OMIT 1 2
=PP5V_S3_DEBUG_ISNS
XW6080
47 8 SM 10%
DEBUG_ADC PPVOUT_S0_LCDBKLT 50V
68 65 7 1 2 PPVOUT_S0_LCDBKLT_XW
1 CERM
C6050 402
0.1UF DEBUG_ADC
20%
10V 1
2 CERM R6080
402 1M PLACEMENT_NOTE=PLACE RC NEAR U6000
1%
A 1/16W DEBUG_ADC
A
3
PLACEMENT_NOTE=PLACE RC NEAR U6000 MF-LF

V+ 2 402 R6082 SYNC_MASTER=K19_IMLB SYNC_DATE=02/25/2009
DEBUG_ADC PAGE TITLE
226K
U6050 R6074 PPVOUT_S0_LCDBKLT_DIV 1 2 ADC_CH7
DEBUG SENSORS AND ADC
INA210 226K DEBUG_ADC 1%
76 68 IN ISNS_LCDBKLT_N 5 IN- SC70 OUT 6 ISNS_LCDBKLT_IOUT 1 2 ADC_CH6 47 1/16W DEBUG_ADC DRAWING NUMBER SIZE
1 MF-LF
DEBUG_ADC 1% R6081 402 1 C6082 051-7982 D
76 68 ISNS_LCDBKLT_P 4 IN+ REF 1
1/16W
MF-LF
DEBUG_ADC 47.0K
1%
2.2UF Apple Inc. REVISION
IN 1 10%
GAIN: 200X 402 C6074
2.2UF
1/16W
MF-LF
402
2
6.3V
X5R
R
C.0.0
GND 10% 2 402
6.3V
2
2
X5R
402 THE INFORMATION CONTAINED HEREIN IS THE
60 OF 109
DIVIDER: 1/22 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
38 8 =PP3V3_S5_ROM
NO STUFF
R61901 R6100 1 1
C
C R6101 CRITICAL
8
C6100 1
10K 3.3K 3.3K 0.1UF VCC
5% 5% 5% 20%
1/16W 1/16W 1/16W 10V
MF-LF MF-LF MF-LF CERM 2 U6100
402 2 402 2
2 402 402 32MBIT
R6150 SOP
R6152
0 0
73 38 21 IN SPI_CLK_R 1 2 73 SPI_CLK 6
SCLK SI/SIO0 5 73 SPI_MOSI 1 2 SPI_MOSI_R IN 21 38 73
PLACEMENT_NOTE=PLACE CLOSE TO U6100 5% MX25L3205DM2I-12G 5% PLACEMENT_NOTE=PLACE CLOSE TO U6100

1/16W 1/16W
MF-LF OMIT R6105 MF-LF
38 IN SPI_MLB_CS_L 402 1 CE* 0 402
SO/SIO1 2 73 SPI_MISO_R 1 2 SPI_MISO OUT 21 38 73
SPI_WP_L 3 WP*/ACC
5%
SPI_HOLD_L 7 HOLD* NO STUFF 1/16W PLACEMENT_NOTE=PLACE CLOSE TO U6100
1 MF-LF
R6191 402
GND 10K
4
5%
1/16W
MF-LF
402
2
MCP79 SPI Frequency Select
Frequency SPI_MOSI SPI_CLK

B B
31 MHz 0 0
42 MHz 0 1
25 MHz 1 0
1 MHz 1 1
25MHz is selected with R5190 and R5191

Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
C.0.0
61 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S2355
L6201 U6201 CONSUMES 33MA MAX. FROM 1.8V RAIL
FERR-220-OHM =PP5V_S3_AUDIO 8 49 51 53
=PP1V8_S0_AUDIO 1 2 PP1V8_S0_AUDIO_DIG
8 IN
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.10MM 0402
MIN_NECK_WIDTH=0.10MM =PP3V3_S0_AUDIO 8 49 53 54
C6210 1 1
C6211
D 4.7UF
20%
4V
0.1UF
10%
16V
PP4V5_AUDIO_ANALOG IN 7 49
D
X5R 2 2 X5R
402 402
C6216 1
C6215 1
1 1UF 0.1UF C6214 1 1

C6213
C6219 10% 10% 0.1UF 10UF CRITICAL
10UF 10V 16V
20%
C6218 1 1
C6217 X5R 2 X5R 2
10%
16V
20%
6.3V
2 2
16V 2
0.1UF 10UF 402-1 402 X5R X5R
10% 402 603-1
53 51 49 GND_AUDIO_HP_AMP TANT-POLY
16V
20%
2012-LLP
24
46
25
CRITICAL 2 2 16V
9
PP4V5_AUDIO_ANALOG X5R TANT-POLY GND_AUDIO_HP_AMP
49 7 IN 402 49 51 53
C6221 1 1
C6220 2012-LLP
GND_AUDIO_CODEC
10UF 10UF VD VA_REF VA_HP VA 49 50 53 54
20%
6.3V
20%
6.3V
VBIAS_DAC 29 VBIAS_DAC
1
R6210 X5R 2 2 X5R
HPOUT_L 38 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM AUD_HP_PORT_L OUT 51
603-1 603-1 CS4206_FP
2.67K 44 VHP_FILT+
AUD_HP_PORT_R
U6201 HPOUT_R
1% CRITICAL 40 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM OUT 51
1/16W CS4206_FN 41 VHP_FILT-
MF-LF
402 CS4206ACNZC HPREF 39 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.10MM AUD_HP_PORT_REF 53
2 QFN
IN
GPIO0 = ANALOG SW CONTROL 53 OUT AUD_GPIO_0 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 TP_AUD_LO1_P_L NC

51 OUT AUD_GPIO_1 12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34 TP_AUD_LO1_N_L NC
GPIO1 = HP AMP CONTROL /SPDIF_OUT2
TP_AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_P_R OUT 52
NC AUD_GPIO_3 AUD_LO1_N_R
FR SPKR AMP. SIG. SOURCE
GPIO3 = SPKR AMP SHDN CONTROL 52 OUT 15 GPIO3 LINEOUT_R1- 37 OUT 52
54 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_P_L OUT 52

LFT. SPKR AMP. SIG. SOURCE
CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_N_L OUT 52
CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_P_R OUT 52

45 FLYP RT. SPKR AMP. SIG. SOURCE
LINEOUT_R2- 33 AUD_LO2_N_R OUT 52
C6222 1 1
C6223 43 FLYC
2.2UF 2.2UF 42 FLYN
20% 20%
6.3V 6.3V CRITICAL
CERM 2 2 CERM MICBIAS 16 AUD_CODEC_MICBIAS OUT 54
402-LF 402-LF
3 VL_HD
CS4206_FLYN
C VCOM 28 CS4206_VCOM
C
1 VL_IF
LINEIN_L+ 21 AUD_LI_P_L IN 50
73 21 IN HDA_BIT_CLK 6 BITCLK
LINEIN_C- 22 AUD_LI_REF IN 50
73 21 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 50
R6211 10 SYNC
HDA_SDIN0 1
22 2 AUD_SDI_R AUD_MIC_INP_L
73 21 OUT 8 SDI MICIN_L+ 18 IN 54
EXT MIC CODEC INPUT
5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 54
1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INP_R IN 54
402 11 RESET* BI MIC CODEC INPUT
73 21 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INN_R IN 54
73 21 IN HDA_RST_L
NC TP_AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC NC
AUD_SPDIF_OUT_CHIP 48 SPDIF_OUT
R6212
1
22 2
53 OUT AUD_SPDIF_OUT DMIC_SCL 4 TP_AUD_DMIC_CLK NC
5%
1/16W
MF-LF
402 DGND THRM_PAD AGND
49
26
CRITICAL
1
C6224 1
C6225 NOSTUFF
1UF 10UF 1
20% 20%
16V 2 2 16V
R6213
TANT POLY-TANT 100K
0603-SM CASE-B2-SM 5%
1/16W
MF-LF
402
B 2
B
54 53 50 49 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2456
NOTES ON CODEC I/O
L6200 MIN_LINE_WIDTH=0.15MM MIN_LINE_WIDTH=0.15MM
FERR-220-OHM MIN_NECK_WIDTH=0.10MM
VOLTAGE=5V
U6200 MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V
DIFF FSINPUT= 2.45VRMS
TPS71745 SE FSINPUT= 1.22VRMS
=PP5V_S3_AUDIO 1 2 4V5_REG_IN 6 SON 1 PP4V5_AUDIO_ANALOG
53 51 49 8 IN IN OUT OUT 7 49
DAC1 FSOUTPUT= 1.34VRMS
0402
CRITICAL
R6200 4V5_REG_EN 4 3 4V5_NR
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
EN NR/FB
2.21K DAC2/3 FSOUTPUTSE= 1.34VRMS
54 53 49 8 IN =PP3V3_S0_AUDIO 1 2
NC 5
1% GND
1/16W
2
MF-LF 1
C6200 1
C6201 1
C6203
402
1UF 1UF C6202 1
1UF
10% 10% 0.1UF 10%
10V 10V 10% 10V
2 X5R PLACE NEAR U6200 2 X5R 16V 2 X5R
2
402
XW6200 402 X7R-CERM
402
402
SM
1 2 GND_AUDIO_CODEC 49 50 53 54
NOSTUFF
A R6201
0
SYNC_MASTER=AUDIO SYNC_DATE=06/09/2009 A
1 2 PAGE TITLE
5%
1/16W
AUDIO: CODEC/REGULATOR
MF-LF DRAWING NUMBER SIZE
402
XW6201 Apple Inc. 051-7982 D

SM REVISION
1 2 MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_AUDIO_HP_AMP 49 51 53
R
C.0.0
PLACE NEAR C6220 AND C6221 NOTICE OF PROPRIETARY PROPERTY: BRANCH
62 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS
NET RIN = 10.36K OHMS (INCLUDING PULL-DOWNS AT ANALOG SWITCH COM PINS)
FC_HP = 3.6 HZ
FC_LP = 43KHZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
R6301 C6301
7.87K2 2.2UF
53 IN AUD_LI_L 1 AUD_LI_L_DIV 1 2 AUD_LI_P_L OUT 49
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1/16W 20%
MF-LF 10V
402 X5R-CERM
402
C C
NOSTUFF 1
1 C6303 R6302
820PF 21.5K
10% 1%
50V 1/16W
2 CERM MF-LF
402 2 402 CRITICAL
C6302
2.2UF
1 2
20%
10V
X5R-CERM
402
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM AUD_LI_REF OUT 49
53 IN AUD_LI_GND MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1
R6300
10
1% CRITICAL
1/16W
MF-LF
2 402
C6312
2.2UF
1 2
54 53 49 IN GND_AUDIO_CODEC 20%
10V
NOSTUFF X5R-CERM
1 C6313 402
820PF
10% 1
R6312
B 50V
2 CERM
402
1%
21.5K B
1/16W
MF-LF
2 402
CRITICAL
R6311 C6311
2.2UF
AUD_LI_R 1
7.87K2 AUD_LI_R_DIV 1 2 AUD_LI_P_R
53 IN OUT 49
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1/16W 20%
MF-LF 10V
402 X5R-CERM
402
A A
PAGE TITLE
AUDIO: LINE INPUT FILTER

DRAWING NUMBER SIZE

REVISION
R
C.0.0
63 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
HP/LO AMP
L6520 MIN_NECK_WIDTH=0.2MM APN: 353S1637
FERR-120-OHM-1.5A
=PP5V_S3_AUDIO 1 2
AUD_PP5V_F
53 49 8
0402-LF
1 C6520 1 C6521
0.1UF 10UF
10% 20%
2 16V
X7R-CERM 2 6.3V
X5R
402 603 MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM AUD_LO_AMP_OUTL OUT 51 53
12
VDD
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER 51
AUD_LO_AMP_INL_M
AUD_LO_AMP_INR_M
6 INL
8 INR
CRITICAL
U6500 OUTL 11
AUD_LO_AMP_OUTR OUT 51 53
51 OUTR 10
MAX9724A MAX9724_C1P 1
R6520 TQFN
CRITICAL R6523
0 C1P 1 2.21K
49 IN AUD_GPIO_1 1 2 AUD_GPIO_1_R 5 SHDN*
C1N 3
1 C6524 1%
1/16W
1
R6524
5% 1UF MF-LF 2.21K
51 49 IN AUD_HP_PORT_L 1/16W 10%
2 402 1%
2 10V
13 THRM
7 SGND
2 PGND
9 SVSS
4 PVSS
MF-LF 1/16W
MAX9724_C1N X5R
PAD
402 MF-LF
CRITICAL 402
2 402
C6500 1
1
0.1UF R6522
10%
16V 100K MAX9724_SVSS
X7R-CERM 2 5%
402 1/16W
MF-LF
NC AUD_HP_ZOBEL_L 2 402 CRITICAL
CRITICAL
1 C6523 C
C R65001
39
1 C6522
1UF
1UF
10%
10% 10V
5% 10V 2 X5R
1/16W 2 X5R 402
MF-LF GND_AUDIO_HP_AMP 402
402 53 51 49
2
53 51 49 IN GND_AUDIO_HP_AMP
R65101
39
5%
1/16W
MF-LF
402 2 MAX9724 GAIN/FILTER COMPONENTS
NC AUD_HP_ZOBEL_R AV_PB = -1V/V, FC_LPF = 35.2KHZ
CRITICAL CRITICAL
C6510 1
0.1UF
C6530
10%
330PF
16V
2 1 2
X7R-CERM
402
51 49 IN AUD_HP_PORT_R 5%
50V
COG
402
R6531
1
13.7K2
1%
1/16W
MF-LF
402
B AUD_HP_PORT_L
R6530
13.7K2
AUD_LO_AMP_INL_M
AUD_LO_AMP_OUTL
B
51 49 1 51 51 53
IN OUT
1%
1/16W
MF-LF
402
R6532 AUD_LO_AMP_INR_M
AUD_HP_PORT_R 13.7K2
1
AUD_LO_AMP_OUTR
51 49 IN 51 OUT 51 53
1%
1/16W
MF-LF
402 R6533
1
13.7K2
1%
1/16W
MF-LF
402
CRITICAL
C6531
330PF
1 2
5%
50V
COG
402
A SYNC_MASTER=AUDIO SYNC_DATE=06/09/2009 A
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER SIZE

REVISION
R
C.0.0
65 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DYNAMIC (SUB) AND PIEZO (SATELLITE) SPKR AMPLIFIERS
NO STUFF
C6612
180PF
SATELLITE HPF FC = 775 HZ 1 2
5%
SUB 80 HZ < HPF FC < 132 HZ R6615 50V
CERM
26.1K2 402
1
SUB GAIN 6DB (2V/V) 1% NO STUFF
1/16W
MF-LF C6613
SAT GAIN 5.6DB (1.91V/V) 402 180PF
D
1
5%
2
D
50V
CERM
R6616 402
26.1K2
1
1%
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 1/16W
APN:353S2630 MF-LF
402
52 8 =PP5V_S3_AUDIO_AMP
CRITICAL
1 C6601
D3
A2
C6607 1 10UF OMIT
1UF 10% MIN_LINE_WIDTH=0.30 mm
10% PVDD SVDD 16V
CRITICAL 10V
X5R 2
2 X5R-CERM R6612 MIN_NECK_WIDTH=0.20 MM
L6610 C6610 402 U6610 SPKRAMP_R_P_OUT_R
0805
1
6.8 2 SPKRAMP_R_P_OUT
FERR-1000-OHM 0.015UF R6613 LM48556TL
7 53
LM48311_R_P_C 113.7K2 OMIT 5%

49 AUD_LO2_P_R 1 2 SPKRAMP_INR_P 1 2 BGA 1/8W MIN_LINE_WIDTH=0.30 mm
IN
A3 IN+ OUT+ B2 R6617 MF-LF
0402 1% LM48311_R_P 805 MIN_NECK_WIDTH=0.20 MM
10% 1/16W B3 IN- CRITICAL OUT- A1 6.8
16V
X7R
MF-LF LM48311_R_N SPKRAMP_R_N_OUT_R 1 2 SPKRAMP_R_N_OUT 7 53
CRITICAL 402
L6611 C6611 402
C3 C1P C2 LM48556_C1P_R 5%
FERR-1000-OHM 0.015UF R6614 SD*
C1N D1 CRITICAL
1/8W
MF-LF
LM48311_R_N_C 113.7K2
805
49 IN AUD_LO2_N_R 1 2 SPKRAMP_INR_N 1 2
CPVSS C1
1 C6604
0402 1% 4.7UF
10% 1/16W 10%
16V 1 PGND SVSS 10V
X7R
MF-LF
402 R6611 2 X5R
805
402
R6610 100K LM48556_VSS_R
D2
B1
5% LM48556_C1N_R
0 1/16W
49 IN AUD_GPIO_3 1 2 MF-LF CRITICAL
5% 2 402 1 C6602
1/16W
MF-LF 10UF
402 10%
SPKRAMP_SHDN 16V
52 2 X5R-CERM
C 0805
C
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM
CRITICAL
APN:353S2621 1
C6603
47UF MIN_LINE_WIDTH=0.30 mm
B2 B1
C6608 1
PVDD VDD
20%
2 6.3V
CRITICAL 1UF CRITICAL TANT1 SPKRAMP_SUB_P_OUT 7 53
10% 2012-LLP
L6620 C6620 10V
X5R 2 U6620
FERR-1000-OHM 0.1UF 402 LM48311 MIN_LINE_WIDTH=0.30 mm
BGA
49 IN AUD_LO1_P_R 1 2 SPKRAMP_INSUB_P 1 2 LM48311_SUB_P A1 IN+ OUTA A3 MIN_NECK_WIDTH=0.20 MM
0402 CRITICAL LM48311_SUB_N C1 IN- OUTB C3 SPKRAMP_SUB_N_OUT 7 53
10%
L6621 16V
X5R C6621 A2 SD*
FERR-1000-OHM 402 0.1UF
49 AUD_LO1_N_R 1 2 SPKRAMP_INSUB_N 1 2
IN PGND GND
0402
10% B3 C2
16V
X5R
402
52 SPKRAMP_SHDN
NO STUFF
C6634
180PF
1 2
5%
50V
R6634 CERM
B 1
26.1K2 402
B
1%
1/16W NO STUFF
MF-LF
402 C6635
180PF
1 2
5%
50V
CERM
R6635 402
1
26.1K2
1%
ALIAS OF PP5V_S3_REG, MIN_LINE_WIDTH=0.60MM, MIN_NECK_WIDTH=0.20MM 1/16W
MF-LF
APN:353S2630 402
CRITICAL
1 C6605
D3
A2
10UF MIN_LINE_WIDTH=0.30 mm
10% OMIT
CRITICAL C6609 1 PVDD SVDD 16V
2 X5R-CERM R6630 SPKRAMP_L_P_OUT
L6630 C6630 1UF
10% U6630 SPKRAMP_L_P_OUT_R
0805
1
6.8 2
7 53
FERR-1000-OHM 0.015UF R6631 10V

X5R 2 LM48556TL
1 2 SPKRAMP_INL_P 1 2 LM48311_L_P_C 13.7K2 LM48311_L_P 402 BGA OMIT 5% MIN_LINE_WIDTH=0.30 mm
49 AUD_LO2_P_L 1 1/8W
IN
0402 A3 IN+ OUT+ B2 R6633 MF-LF MIN_NECK_WIDTH=0.20 MM
1% 805
10% 1/16W B3 IN- CRITICAL OUT- A1 6.8 SPKRAMP_L_N_OUT
16V
X7R CRITICAL MF-LF LM48311_L_N SPKRAMP_L_N_OUT_R 1 2 7 53
402
L6631 402
C6631 C3 C1P C2 LM48556_C1P_L 5%
FERR-1000-OHM 0.015UF R6632 SD*
C1N D1 CRITICAL
1/8W
MF-LF
13.7K2 805
49 IN AUD_LO2_N_L 1 2 SPKRAMP_INL_N 1 2 1
CPVSS C1
1 C6633
0402 LM48311_L_N_C 1% 4.7UF
10% 1/16W 10%
A 16V
X7R
402
MF-LF
402
PGND SVSS
LM48556_C1N_L
10V
2 X5R
805 SYNC_MASTER=AUDIO SYNC_DATE=06/09/2009 A
D2
B1
PAGE TITLE
SPKRAMP_SHDN
52 LM48556_VSS_L
AUDI0: SPEAKER AMP
CRITICAL DRAWING NUMBER SIZE
1 C6632 Apple Inc. 051-7982 D
10UF REVISION
10%
16V
2 X5R-CERM
R
C.0.0
0805
66 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO JACK: LI/LO/HP CONNECTOR, SPDIF TX

54 49 8 =PP3V3_S0_AUDIO AUD_SPDIF_OUT IN 49
L6701
FERR-1000-OHM
1 2 HS_MIC_HI OUT 54
0402
AUD_CONNJ1_MIC
L6702
FERR-1000-OHM PLACE NEAR J6700
XW6702
D MIN_LINE_WIDTH=0.4MM
1
0402
2 HS_MIC_LO OUT 54
1
SM
2
AUD_HP_PORT_REF
OUT 49
D
CRITICAL
AUD_CONNJ1_SLEEVE
L6703 MIN_LINE_WIDTH=0.4MM
PLACE NEAR J6700
FERR-120-OHM-1.5A MIN_NECK_WIDTH=0.2MM
APN:514-0694 1 2
AUD_CONN_GND XW6700
SM
OMIT GND_AUDIO_HP_AMP
0402-LF 1 2
J6700 CRITICAL
PLACE NEAR J6700
49 51
AUDIO-JACK-TRANS-K83 L6704
XW6701
F-RT-TH FERR-220-OHM
SM
CRITICAL AUD_CONN_L AUD_LI_GND
8 1 2
53 1 2 50
BI
2 AUD_CONNJ1_SLEEVEDET 0402
1 CRITICAL
AUD_CONNJ1_TIP AUD_CONN_GND
7 L6705 5353
AUD_CONNJ1_RING FERR-220-OHM
6 AUD_CONN_R
1 2
53
AUDIO BI
0402
PHS DETECT 5 AUD_IP_PERPH_DET_JACK
GND 3
4 AUD_CONNJ1_TIPDET
L6706
FERR-1000-OHM
HP DETECT
9
1 2
AUD_IP_PERPH_DET
OUT 54
MIC CONNECTOR CRITICAL
J6701
A - VIN
10
0402 APN:518S0520 78171-0003
B - VCC M-RT-SM
C - GND 11 R6700 4
10K AUD_J1_SLEEVEDET_R
CRITICAL CRITICAL 1 2 54
OPERATING VOLTAGE 3.3 2 2 OUT
POF DZ6705 DZ6703 5%
1/16W
54 7 BI_MIC_LO 1
1 6.8V-100PF 6.8V-100PF
12 C6700 402 402
MF-LF
402
54 7 BI_MIC_SHIELD 2
SHELL 1UF CRITICAL 54 7 BI_MIC_HI 3

13 10% 2 2 2 CRITICAL
R6701
C SHIELD
PINS
14 2
6.3V
CERM
402
CRITICAL
DZ6702
CRITICAL
DZ6701
DZ6704
6.8V-100PF
402
1 1
DZ6700
6.8V-100PF
2
1
4.7
2
AUD_J1_TIPDET_R
OUT 54 5 C
6.8V-100PF 6.8V-100PF 402 5%
402 402 1/16W
1 1 1 1 C6701 MF-LF
402
1
100PF
5%
50V
2 CERM
402
SPEAKER CONNECTORS
APN:518S0519
CRITICAL
J6702
78171-0002
M-RT-SM
3
52 7 IN SPKRAMP_L_P_OUT 1
R6724 52 7 SPKRAMP_L_N_OUT 2
LEFT PIEZO
IN
=PP5V_S3_AUDIO 0
51 49 8 1 2 PP_MAX14504_VCC
5% C6703 1 1 C6702 4
1/16W
MF-LF 100PF 100PF
5% 5%
402 1
C6710 50V
1UF CERM 2 2 50V
CERM
R6716 10% 402 402
CRITICAL
AUD_LO_AMP_OUTL 1
0
2 AUD_LO_AMP_OUTL_SWITCH 2
10V
X5R APN: 353S2536
51 OUT 402 J6703
5%
78171-0002
1/16W M-RT-SM
AUD_CONN_L
A3
MF-LF MIN_NECK_WIDTH=0.15MM CRITICAL
402 53 L6707 3
B R6717 U6700
VCC
1
R6712
BI
FERR-120-OHM-3A
1 2 SPKRAMP_SUB_P_OUT_CONN
B
0 SPKRAMP_SUB_P_OUT 1
AUD_LO_AMP_OUTR 52 7 IN
51 OUT
1 2 AUD_LO_AMP_OUTR_SWITCH
C4
MAX14504
B4
24K 2 DYN. FULL RANGE
NC1 WLP COM1 5% 52 7 IN SPKRAMP_SUB_N_OUT 0603 SPKRAMP_SUB_N_OUT_CONN
5% 1/16W
C1
1/16W NC2 CRITICAL MF-LF 1 1C6704 CRITICAL
MF-LF
402 2 402 C6705 L6708 4
A4 B1 100PF 100PF FERR-120-OHM-3A
NO1 COM2 5% 5%
R6718 A1
NO2 50V
CERM 2
50V
2 CERM 1 2
AUD_LI_L 0 MIN_LINE_WIDTH=0.2MM 402 402
50 1 2 AUD_LI_L_SWITCH 0603
IN C2 B2 AUD_CONN_R
CB EN* MIN_NECK_WIDTH=0.15MM
5% 53 CRITICAL
BI
1/16W
MF-LF
SWITCH_CP A2 NEG J6704
402 78171-0003
M-RT-SM
R6719 CRITICAL
GND L6709 4
AUD_LI_R 0 FERR-120-OHM-3A
1 2 AUD_LI_R_SWITCH C6711
B3
C3
50 IN 1
5% 0.0033UF
1
R6713 52 7 IN SPKRAMP_R_P_OUT 1 2 SPKRAMP_R_P_OUT_CONN 1
1/16W 10% 24K
MF-LF
402
50V
CERM
2
5%
1/16W
52 7 IN SPKRAMP_R_N_OUT 0603 2 RT. PIEZO
402
MF-LF SPKRAMP_R_N_OUT_CONN 3
2 402 CRITICAL
L6710
C6707 1 1 C6706
R6720 FERR-120-OHM-3A 5
AUD_GPIO_0 0 100PF 100PF
49 1 2 AUD_SWITCH_CTRL 5% 5% 1 2
IN 50V
CERM 2 2 50V
CERM
5% 0603
1/16W 402 402
MF-LF
402 1
R6721
100K
5%
1/16W
ANALOG AUDIO IO SWITCH
MF-LF
402
2
R6715 GPIO0 = 0 AND GPIO1 = 1 --> HP PATH SELECTED
AUD_CONN_GND 0 AUD_SWITCH_GND
A 53 1
5%
1/16W
2 GPIO0 = 1 AND GPIO1 = 0 --> LI PATH SELECTED
MF-LF NOSTUFF
PAGE TITLE
R6714
GND STUFFING OPTIONS FOR CMOS SWITCH
54 50 49
GND_AUDIO_CODEC
402
1
0
2 R6727 AUDIO: JACK
5% 1 2
1/16W
MF-LF 5% Apple Inc. 051-7982 D
402 1/16W REVISION
MF-LF
402
R
C.0.0
67 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PORT B LEFT(HEADSET MIC)
CODEC OUTPUT SIGNAL PATHS
HP=80HZ, LP=8.82KHZ
MIKEY
FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT
L6880 MIN_LINE_WIDTH=0.10MM
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) GPIO_0 AND GPIO_1 0X09 (A) FERR-1000-OHM MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
LINE IN 0X05 (5) 0X05 (5) 0X0C (12) GPIO_0 AND GPIO_1 0X09 (A) AND UI ELEMENT 1 2
54 53 49 8 =PP3V3_S0_AUDIO PP3V3_S0_HS_RX
SATELLITES 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A
0402
DRC MIKEY
SUB 0X03 (3) 0X03 (03) 0X0A (10) GPIO_3 N/A
CRITICAL APN:353S2256
SPDIF OUT N/A 0X08 (8) 0X10 (16) N/A 0X0D (B) MIKEY
C6880 1
CODEC INPUT SIGNAL PATHS
3
1UF MIKEY
10% AVDD
6.3V
FUNCTION CONVERTER PIN COMPLEX VREF/ENABLE DET ASSIGNMENT CERM 2
BUILT-IN MIC 0X06 (6) 0X0D (13,B,RIGHT) MIC_BIAS (80%) N/A

402 U6880
D HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MCP79 GPIO_38 MCP79 GPIO_17 (PERIPH DETECT)
MCP79 GPIO_4 (LOAD DETECT)
PULLUPS ON MCP PAGE
6
CD3275
DRC
1
D
39 IN =I2C_MIKEY_SCL SCL MICBIAS
54 HS_MIC_BIAS
MIKEY
5 2
PORT A DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE) 39 BI =I2C_MIKEY_SDA SDA DETECT HS_SW_DET CRITICAL
1
7 10 C6882
21 OUT AUD_I2C_INT_L INT* BYPASS HS_RX_BP
2.2UF
49 OUT AUD_SENSE_A 8
20%
19 IN AUD_IPHS_SWITCH_EN ENABLE 2 6.3V
TANT
54 PP3V3_S0_AUDIO_F 1 1
GND THM 402
R6806 R6805 MIKEY
11
1
39.2K 20.0K
R6880
MIKEY 1
1
APN:376S0613 1% 1% 100K GND_AUDIO_CODEC 49 50 53 54
R6801 1/16W 1/16W 5% C6881
MF-LF MF-LF 1/16W
300K AUD_OUTJACK_INSERT_L 0.01UF
2
402
2
402 MF-LF
16V 10%
MIKEY MIKEY
5% 402
402 CERM
2
2 1 1
1/16W AUD_PORTA_DET_L NC AUD_PORTB_DET_L NC
MF-LF
R6881 R6882
402 Q6800 D 3
1K 2.2K
2 GND_AUDIO_CODEC
SSM6N15FEAPE Q6801 D 3
Q6801 D 6
54 53 50 49
1%
1/16W
5%
1/16W
SOT563 MIKEY MF-LF MF-LF
SSM6N15FEAPE SSM6N15FEAPE CRITICAL 402 402
R6802 SOT563 SOT563
MIKEY
2 2
47K C6883
53 AUD_J1_TIPDET_R 1 2 AUD_J1_DET_RC 0.1UF
R6884
IN
5 G S 1 2
2.2K
OUT AUD_MIC_INP_L HS_MIC_HI_RC HS_MIC_HI
5% 4 49 1 2 53 54
1 IN
1/16W 5 G S 2 G S
MF-LF C6801 4 1
MIKEY 10%
MIKEY 5%
402 CRITICAL 1/16W
0.1UF 25V 1
MIKEY MF-LF
2
20% 10V C6886 X5R R6883 1 402 MIKEY
CERM 402 402 1
0.1UF 100K C6884
1 2
5%
0.0082UF
C6885
54 53 50 49 GND_AUDIO_CODEC 49 OUT AUD_MIC_INN_L 1/16W
10% 25V 27PF
MF-LF 2 X7R 402 5% 50V
402 2
R6803 10% 2
CRITICAL
CERM 402
220K 25V
CRITICAL
X5R
54 PP3V3_S0_AUDIO_F 1 2 AUD_J1_SLEEVEDET_INV
402
XW6880
SM
5%
1
R6804 1/16W 54 53 50 49 GND_AUDIO_CODEC 1 2 HS_MIC_LO IN 53
MF-LF
220K 402
D 6 PLACE NEAR C6886
C 5%
1/16W
MF-LF
Q6800
SSM6N15FEAPE
SOT563
54 53 AUD_J1_SLEEVEDET_R
C
402
2
PORT B RIGHT(BUILT-IN MIC)
54 53 AUD_J1_SLEEVEDET_R
IN
1
C6802 2 G S R6850 R6851
1 100 2.4K
0.01UF 49 AUD_CODEC_MICBIAS 1 2 MIC_BIAS_FILT 1 2
10% IN
16V 1% 1%
2
CERM
1/16W CRITICAL 1/16W
402 1
54 53 50 49 GND_AUDIO_CODEC MF-LF
C6852 MF
402 402-1
2.2UF
20%
2 6.3V
MIN_LINE_WIDTH=0.10MM TANT
MIN_NECK_WIDTH=0.10MM 402
54 53 50 49 GND_AUDIO_CODEC
54 PP3V3_S0_AUDIO_F
VOLTAGE=3.3V CRITICAL
C6850 L6850
EXTRACTION NOTIFICATION CKT FERR-1000-OHM
L6862 0.1UF
FERR-1000-OHM 1 2 1 2
49 OUT AUD_MIC_INP_R BI_MIC_HI_F BI_MIC_HI
IN 7 53
=PP3V3_S0_AUDIO 1 2 0402
54 53 49 8 IN CRITICAL 10%
0402 C6851 25V 1
CRITICAL CRITICAL
MIKEY 0.1UF
X5R R6852 1 1
1 402
PLACE L6800/C6800 CLOSE TO JACK TRANS. AREA R6864 1 2
100K C6853 C6854
1
49 OUT AUD_MIC_INN_R 5%
0.001UF 27PF
220K 1/16W
50V 10% 5% 50V
C6861 5% 10%
MF-LF 402 CERM
2 2
CERM 402
L6851
0.1UF
1/16W MIKEY 25V 2
402 FERR-1000-OHM
MF-LF
10V 20% 1 X5R R6853
402 CERM
2
2
402
R6865 402
2.4K BI_MIC_LO_F 1 2 BI_MIC_LO IN 7 53
100K 54 53 50 49 GND_AUDIO_CODEC 1 2
5% 0402
1MIKEY 1/16W 1%
R6862 MIKEY
MF-LF
402 MIKEY XW6851
1/16W
MF
300K 2 402-1
5% Q6802 D 6 R6861 SM
1/16W 0 1 2 BI_MIC_SHIELD
IN 7 53
MF-LF SSM6N15FEAPE AUD_PERPH_DET_R AUD_IP_PERIPHERAL_DET 17
OUT
2 402 SOT563 PLACE NEAR J6701
5% HP=80HZ
B MIKEY
Q6802 D 3
1/16W
MF-LF
402
B
2 G S 1 SSM6N15FEAPE
MIKEY SOT563
R6860
15K PERPH_DET_FILT
53 AUD_IP_PERPH_DET 1 2
5% MIKEY 5 G S 4
1/16W
MF-LF
402
1
C6860
0.1UF AUD_J1_TIPDET_INV
20%
10V
2 CERM
402
54 53 50 49 GND_AUDIO_CODEC
MIKEY MIC LOAD DET CKT
PP3V3_S0_AUDIO_F
54
54 HS_MIC_BIAS MIKEY_LOAD_DET
MIKEY_LOAD_DET 1
1
MIKEY_LOAD_DET MIKEY_LOAD_DET
CRITICAL 1 C6872 R6872
R6870 0.1UF 100K
2.21K U6870 10% 1%
1/16W
1%
A1 MAX9028EBT+ 16V
2 X5R MF-LF MIKEY_LOAD_DET
VCC
1/16W UCSP 402 2 402 R6873

MF-LF 54 53 HS_MIC_HI B3
0
2 402 A2 MIC_LOAD_COMP_OUT 1 2 MIKEY_MIC_LOAD_DET
VEE1
OUT 9
HS_MIC_BIAS_COMP B1 5%
VEE0
COMP. TRIP PT. = 2.64V 1/16W
A MIKEY_LOAD_DET A3
B2
OUTPUT HIGH WHEN MIC BIAS LOADED

MF-LF
402
MIKEY_LOAD_DET MIKEY_LOAD_DET PAGE TITLE
1
R6871
100K
1 C6870
27PF
1 C6871
27PF
OUTPUT LOW WHEN MIC BIAS UNLOADED
AUDIO: JACK TRANSLATORS
1% 5% 5% DRAWING NUMBER SIZE
1/16W
MF-LF 2 50V
CERM 2 50V
CERM
2 402 402 402 REVISION
GND_AUDIO_CODEC
R
C.0.0
54 53 50 49 NOTICE OF PROPRIETARY PROPERTY: BRANCH
68 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MagSafe DC Power Jack

CRITICAL
J6900 CRITICAL
78048-0573 F6905
M-RT-SM
6AMP-24V
1 7 PP18V5_DCIN_FUSE 1 2 =PP18V5_DCIN_CONN 8 55
MIN_LINE_WIDTH=1mm
2
VOLTAGE=18.5V 1206-1
3
1
C6905
D
4
5 7 ADAPTER_SENSE 1
R6928
0
2
0.01UF
20%
50V
=PP3V42_G3H_ONEWIRE 8 D
2
CERM
5%
603
SMC_BC_ACOK_VCC SOT665
1/16W
MF-LF R6929 TC7SZ08AFEAPE
402 2.0K 5
1
518S0656 402
A
2 SMC_BC_ACOK 36 37
MF-LF
1/16W
VCC 4
5% Y U6901
ONEWIRE_PU U6900 B
1
1
C6908
1
MAX9940
SC70-5 3 0.1UF
36 SYS_ONEWIRE 4 INT EXT 5 20% PLACEMENT_NOTE=PLACE NEAR U6901
BI 10V
2 CERM
402
GND NC
3
NC
1-Wire OverVoltage Protection

ADAPTER_SENSE_R
C C
516S0787
J6955
ASP-146700-03
F-ST-SM
8 =PP3V42_G3H_HALL 1 2
3 4
5 6
R6905 D6905
47
HN2D01JEAPE
=PP18V5_DCIN_CONN 1 2 PPDCIN_S5_P3V42G3H SOT665
55 8
5%
3.425V "G3Hot" Supply
1/8W 1 5 R6961
VOLTAGE=18.5V
MF-LF Supply needs to guarantee 3.31V delivered to SMC VRef generator 0
805 7 SMC_LID_R 1 2 SMC_LID 36 37 44
1/16W 402
3 4 5% NOSTUFF
MF-LF
1
C6955
56 55 7 BATT_POS_F PPVIN_G3H_P3V42G3H
2 0.001UF
NC NC MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm P3V42G3H_BOOST 10%
50V
VOLTAGE=12.6V VOLTAGE=18.5V DIDT=TRUE 2
CERM
402
6
3
1 1
C6990 C6994
10UF VIN BOOST 0.22uF CRITICAL
10% 20%
25V
X5R
2 U6990 6.3V
X5R
2 L6995
805 LT3470A 402 33UH-20%-0.44A-0.455OHM
=PP3V42_G3H_REG 8
8 SHDN* SW 4 P3V42G3H_SW 1 2 HALL EFFECT CONNECTOR
DFN
2
D52LC-SM
Vout = 3.425V
BIAS MIN_NECK_WIDTH=0.25 mm
CRITICAL SWITCH_NODE=TRUE DIDT=TRUE
7 NC 250MA MAX OUTPUT
NC
B THRM
FB 1 <Ra>
R6995
1
(Switcher limit) B
GND PAD 1
C6995
348K
5
22pF 1%
5%
1/16W
50V
2 CERM MF-LF CRITICAL
402
402 2 1
C6999
P3V42G3H_FB 22UF
20%
6.3V
<Rb> 2
CERM
1 805
R6996
200K
1%
1/16W
MF-LF
402
2
Vout = 1.25V * (1 + Ra / Rb)
CRITICAL
J6950 BATTERY CONNECTOR
BAT-K24
M-RT-TH
P1 1
P2 2 56 55 7 BATT_POS_F
P3 3
7 SYS_DETECT_L
P4 4
=SMBUS_BATT_SDA
P5 5
P6 6 39
P7 7 =SMBUS_BATT_SCL 39
A P8 8
9
CRITICAL
D6950 1
C6950 1
1
P9 RCLAMP2402B R6950 PAGE TITLE
SHLD_PIN 10
SC-75 10K
5%
1/16W
0.1UF
10%
25V
2
DC-In & Battery Connectors
NOSTUFF
SHLD_PIN 11 MF-LF
X5R
SHLD_PIN 12
402
2

3
SHLD_PIN 13 REVISION
R
C.0.0
518-0359 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
69 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PBUS SUPPLY / BATTERY CHARGER

Q7001
HAT1128R01
SOI
Q7000 CRITICAL
HAT1128R01 8
PPVDCIN_G3H_PRE2 D4 3 PPVDCIN_G3H_PRE
SOI 7 S3
8 =PP18V5_G3H_CHGR D3 MIN_LINE_WIDTH=0.6 MM
CRITICAL S2 2
8 MIN_LINE_WIDTH=0.6 MM 6 MIN_NECK_WIDTH=0.3 MM
3 D4 MIN_NECK_WIDTH=0.3 MM D2 1
S3 7 D1 S1
5
D3
D D7010
2
1
S2
S1
D2
D1
6
5
GATE D
1SS418 R7098 1 4
=PP3V42_G3H_CHGR
R7099
2
SOD-723-HF
C7063 1
100K GATE 56 8
100K
0.1UF 5%
4 CHGR_LOWCURRENT_GATE_R 1 2
10% 1/16W
25V MF-LF 1 C7060
1
2 2 5%
X5R 402 1 0.1UF
402 R7060 10%
25V
R7062 1
1/16W
MF-LF
R7001 57.6K X5R 62K 402
1% 2 402 5%
1
62K 1/16W 1/16W
MF-LF
R7010 CHGR_SGATE 1 2 402 2
MF-LF
402
5
CHGR_DCIN 30.1K 5% 56 41 CHGR_AMON 1
1% 2
56 1/16W 1/16W
MF-LF VCC
MF-LF 402 4 CHGR_LOWCURRENT_GATE
402
2 1
R7061 GND
CHGR_LOWCURRENT_REF3 CRITICAL
1.82K 2 U7060
1%
1/16W
MF-LF
TL331
402 SOT23-5
2
R7023 PLACEMENT_NOT=PLACE XW7020 ON PAD OF R7020

(CHGR_ACIN) 56 1 2 CHGR_VDD 1 2 CHGR_VDDP 10
C7010 1 5%
XW7020 PLACEMENT_NOT=PLACE XW7021 ON PAD OF R7020
0.1UF R7040 1 C7040
1/16W
MF-LF OMIT
10% C7041 4.7 402
SM
25V 5% 1UF
X5R 2 56 8 =PP3V42_G3H_CHGR 1UF 1/16W
10%
1 2 1 2
10% MF-LF
402 10V 402 10V CHGR_CSIP_XW7020
X5R 2 CRITICAL
R7011
1 C7047 1
402-1
X5R
402-1 C7024 1 1
R7020
9.31K
1UF
10%
0.047UF
10%
R7021 0.02 MIN_NECK_WIDTH=0.3 MM
1% 10V 10 OMIT 0.5% MIN_LINE_WIDTH=0.6 MM
19
20
10V 5%
1/16W X5R 2 CERM 2 1W PLACEMENT_NOTE=PLACE C7027 ACROSS PIN 5 OF Q7020 AND PINS 1/2/3 OF Q7021
MF-LF 402-1 402
1/16W XW7021 MF PP18V5_S5_CHGR_SW_R
MF-LF SM
402 VDD VDDP 402 2 0612-1 CRITICAL CRITICAL
2
1 2 1 2
1 1 1 1 1 C7027
12 VHST AGATE 1 CHGR_AGATE C7020 C7021 C7022 C7023 0.001UF
C 39 =SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
11
10
SCL
CRITICAL
CSIP 28
27
CHGR_CSIP
CHGR_CSIN 1 C7061
CHGR_CSIN_XW7021
1 C7062 20%
22UF
20%
22UF 1UF
10%
25V
1UF
10%
25V
20%
50V
CERM
C
39 SDA CSIN 0.1UF 0.1UF 2 25V
POLY-TANT
2 25V
POLY-TANT
2 X5R 2 X5R 2 402
U7000 10%
25V
10%
25V
CASE-D2-SM CASE-D2-SM 603-1 603-1
QFN BGATE 16 56 CHGR_BGATE 5
4 X5R X5R
NC VREF 2 402 2 402
DCIN 2 CHGR_DCIN 56
3 ACIN CRITICAL
ISL6258AHRTZ
CHGR_ACIN GND_CHGR_SGND 56
DIDT=TRUE
BOOT 25 CHGR_BOOT
Q7020 CRITICAL TO SYSTEM
CHGR_ICOMP 5 ICOMP UGATE 24 CHGR_UGATE 4
RJK0305DPB
CHGR_VCOMP 7 23 CHGR_PHASE LFPAK-HF 1 2 =PPBUS_G3H
VCOMP PHASE MIN_NECK_WIDTH=0.2 MM 8
DIDT=TRUE
C7042 1
CHGR_VNEG 8 VNEG
21 CHGR_LGATE
C7025 1 CRITICAL
0.033UF LGATE 0.1UF F7000
CHGR_CSOP 18 CSOP 10% R7008
10%
TRKL* 13 TP_CHGR_TRKL 7AMP
16V CHGR_CSON 17 CSON 25V
CRITICAL 0.01 1206
X5R 9 CHGR_AMON 41 56 X5R 0.5%
2 AMON 402 2 1 2 3
402
R7045 1 L7000 1W
THRM_PAD
C7043 BMON 15 CHGR_BMON 41 MIN_NECK_WIDTH=0.25 MM
MF
0612-1
56.2K
1% 1UF ACOK 14 =CHGR_ACOK 37 1 2 PPVBAT_G3H_CHGR_REG 1 2 PPVBAT_G3H_CHGR_OUT 56
1 C7044
AGND
PGND
1/16W MIN_LINE_WIDTH=0.5 MM
MF-LF
1 2 3 4
0.01UF MIN_NECK_WIDTH=0.2 MM 4.7UH-9.5A 1
10% 402 2 DIDT=TRUE
IHLP4040DZ-SM
C7011
16V 5 CRITICAL 1UF
2 CHGR_VCOMP_R 10% C7028
29
26
6
22
CERM 16V 1 1 10%
402 X5R 0.001UF C7008 2
25V
20% 33UF X5R
C7045 1 402
CHGR_PIN6 50V 20% 603-1
56
56 GND_CHGR_SGND 0.001UF 2
CERM
2 16V
10% 4 402 POLY-TANT
50V CHGR_PIN26 CASED2E-SM
CERM 2 56 MIN_LINE_WIDTH=0.5 MM
402 MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
OMIT CRITICAL
1 2
Q7021 PWM FREQ. = 400 kHz
R7046 1 XW7000
1 C7026 RJK0305DPB 1 2 3 MAX CURRENT = 7A
3.01K SM
0.001UF LFPAK-HF
1%
10%
1/16W PLACEMENT_NOT=PLACE XW7000 CLOSE TO U7000 50V
2 X7R (??? limited)
MF-LF 402
402
2 56 GND_CHGR_SGND
R7031
B CHGR_VNEG_R
(CHGR_CSOP) 1
2.2
2 76 CHGR_CSO_R_P
B
C7046 1
5%
470PF 1/16W
10% MF-LF R7047
50V 402 0
CERM 2
402
1 2 76 CHGR_CSO_R_N
(CHGR_CSON) 5%
1/16W
MF-LF
(CHGR_CSO_R_N) 402
AMON PULLDOWN LOGIC
56 41 CHGR_AMON
56 8 =PP3V42_G3H_CHGR
Q7070 NOSTUFF CHGR_PIN26

BATTERY CHARGE LIMITING FETS
1 SSM6N15FEAPE D 6 1 56
R7074 SOT563 R7075
1M 1M OMIT
5% 5% Q7050
1/16W 1/16W 1 2 GND_CHGR_SGND
MF-LF MF-LF 56 SI7137DP
402 2 402 SO-8
2 CRITICAL
2 G S 1
XW7052 PLACEMENT_NOT=PLACE XW7052 CLOSE TO U7000
SM
S
56 PPVBAT_G3H_CHGR_OUT
D
BATT_POS_F 7 55
1 C7050 1 C7051
2
CHGR_VDD_L
5
CHGR_PIN6 0.01uF 0.1UF
1
56
10% 10%
G
16V 16V
D 3 2 2
Q7070 OMIT
CERM
402
X5R
402
4
SSM6N15FEAPE
A 56 CHGR_VDD
SOT563 1 2 GND_CHGR_SGND 56
XW7054 PAGE TITLE
1
5 G S 4
SM
PLACEMENT_NOT=PLACE XW7054 CLOSE TO U7000
CHGR_BGATE 56 PBUS Supply/Battery Charger
R7073 DRAWING NUMBER SIZE
1K Apple Inc. 051-7982 D

5%
1/16W REVISION
MF-LF
402 2
R
C.0.0
CHGR_VDD_R PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
70 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
- COPY THIS PAGE FROM K36 CSA.76
D
5V S3/3.3V S5 POWER SUPPLY D
VOUT = (2 * RA / RB) + 2 VOUT = (2 * RC / RD) + 2
<RA> <RB> <RD> <RC>

OMIT R7267
15.0K
R7268
10K
R7269
10K
R7270
6.49K OMIT
ROUTING NOTE: ROUTING NOTE:
Place XW7203 by Pin1 OF L7260.
XW7203 1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
XW7204 Place XW7204 by Pin 2 of L7220.
SM 402 402 402 402 SM
2 1 5V_S3_VFB_XW7203 1 2 1 2 1 2 1 2 3V3S5_VFB_R7270 2 1
PLACEMENT_NOT=PLACE XW7203 BY PIN 1 OF L7260 PLACEMENT_NOT=PLACE XW7204 BY PIN 2 OF L7220
57
GND_5V3V3S5_SGND
OMIT
ROUTING NOTE:
XW7205
SM Place XW7205 by C7252.
2 1
C =PPVIN_S3_5VS3
PLACEMENT_NOT=PLACE XW7205 BY C7252
C
57 8
OMIT
ROUTING NOTE:
Place XW7202 by C7292.
XW7202 1 C7272
SM 1UF
10%
2 1 25V
2 X5R
603-1
PLACEMENT_NOT=PLACE XW7202 BY C7292
PLACEMENT_NOTE=PLACE C7230 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7220

5V3V3S5_REG3
57 8 =PPVIN_S3_5VS3 =PPVIN_S5_3V3S5
5VS3_3V3S5_VREF 8
CRITICAL
1
EMI request
C7232 1 1 C7281
CRITICAL 1 C7270
10UF
EMI request
0.001UF C7280
68UF 1UF 1
C7282 20%
1 C7230 C7241 C7240
CRITICAL
1 1
20% 10% 39UF-0.027OHM 2 6.3V 0.001UF
50V 20%
2 25V 1 C7271 X5R 20% 1UF 39UF-0.027OHM
16
2 CERM 2 16V X5R 20% 603 50V 10%
3
ELEC
402 C6-SM 603-1 2 16V
POLY
B1A-SM
C7260 0.22UF
10% VIN VREF C7220 2 CERM
402 2 25V
X5R
20%
2 16V
POLY
0.1UF
10% 2 10V
CERM
14 SKIPSEL VREG3 8 0.1UF
10%
603-1 B1A-SM
D 16V 402 16V
X5R 4 TONSEL VREG5 17 5V3V3S5_REG5 X5R
CRITICAL 402 MIN_LINE_WIDTH=0.6 MM 402 2 3 7
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM
2 1 22 VBST1 CRITICAL VBST2 9 CRITICAL
Q7260 DIDT=TRUE 5V_S3_VBST DIDT=TRUE 3V3S5_VBST 2 1
SIS426DN MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM 5V_S3_DRVH 21 DRVH1
U7200 MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM
Q7220
PWRPK-12128 DRVH2 10 3V3S5_DRVH SIZ700DT
G MIN_LINE_WIDTH=0.6 MM DIDT=TRUE QFN DIDT=TRUE 1 POWERPAK-6X3.7
20 LL1 MIN_LINE_WIDTH=0.6 MM
LL2 11
S MIN_NECK_WIDTH=0.2 MM 5V_S3_LL 3V3S5_LL
PWM FREQ. = 375 KHZ
TPS51125
PWM FREQ. = 300 KHZ L7260 DIDT=TRUE MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 8 L7220
4.7UH-13A-15MOHM DIDT=TRUE 5V_S3_DRVL 19 DRVL1 DRVL2 12
DIDT=TRUE
3V3S5_DRVL 4.7UH-10A
MAX CURRENT = 10A 1 2 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM 5V_S3_VO1 24 VO1 VO2 7
3V3S5V02VO2
DIDT=TRUE EMI request
NO STUFF
1 2 MAX CURRENT = 4A
B PCMB104E4R7-SM
CRITICAL
1
NO STUFF
R7294 5V_S3_VFB 2 VFB1 VFB2 5 3V3S5_VFB
6 1
R7295
2.2
PCMC063T-SM
CRITICAL B
2.2
8
=PP5V_S3_REG 5%
D
CRITICAL 1 ENTRIP1
5% =PP3V3_S5_REG 8
VOLTAGE=5V 1/16W 5V_S3_ENTRIP ENTRIP2 6 3V3S5_ENTRIP 1/16W
EMI request
CRITICAL CRITICAL
MF-LF
402
Q7261 4 5 2
MF-LF
402
EMI request CRITICAL
VOLTAGE=3.3V
2 MIN_NECK_WIDTH=0.25 mm
SIS426DN VCLK 18 NC 3V3S5_LL_SNUBBER
C7291 C7292 5V_S3_LL_SNUBBER PWRPK-12128 1 C7231 C7252
1 C7233 1 C7290
10UF
1 150UF-.025-OHM
20%
1150UF-.025-OHM
20% EMI request G 1 R7271 PGOOD 23 1 R7272 EMI request 0.001UF 1 150UF-.025-OHM
20%
1 C7250
10UF
0.001UF 20% 6.3V
TANT
6.3V
TANT
NO STUFF S 75K EN0 13
1 C7273 75K 1
NO STUFF
C7295
20%
50V 6.3V
TANT 20%
20%
2 50V 2 6.3V
X5R 2 CASE-B2-SM 2 CASE-B2-SM
1 C7294 1%
1/16W
10UF
20%
1%
1/16W 100PF
2 CERM
402 2 CASE-B2-SM 2 6.3V
X5R
CERM 100PF GND THRM_PAD
402 603 5%
MF-LF
2 6.3V MF-LF 5% 603
X5R
15
25
50V 402 402 50V
2 CERM 2 603 2 2 CERM
402 402
OMIT
57 GND_5V3V3S5_SGND 1 2
XW7201
SM
D 6 Q7221 R7273 PLACEMENT_NOT=PLACE XW7201 BETWEEN PIN 15 AND PIN 25 OF U7200
SMC_PM_G2_EN 1
100K 2 5V3V3_REG_EN
SSM6N15FEAPE 63 36 7
P5V3V3_PGOOD
5% 63
SOT563 1/16W
MF-LF
402 ROUTING NOTE:
=P5VS3_EN_L 2 G S
63 IN
1 Q7221 Place XW7201 between Pin 15 and Pin 25 of U7200.
D 3
SSM6N15FEAPE
SOT563
A 63
=P3V3S5_EN_L 5 G S 4
A
IN PAGE TITLE
5V/3.3V SUPPLY
DRAWING NUMBER SIZE

REVISION
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3. R
C.0.0
72 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V/0.75V(DDR3) POWER SUPPLY D

D VOUT = 0.75V * (1 + RA / RB)
<RB> NO STUFF
1 2
1 2 1V5S3_VDDQSET
R7322
20K <RA> C7303
0.1% 100PF
1/16W
MF 5%
402 50V
CERM
26 8 =PPVTT_S3_DDR_BUF R7321 402
20.0K
1%
1 2 1/16W
MF-LF
402
C7340 1 C7301
0.033UF 10UF
10% 20%
16V 6.3V
2 X5R
X5R
PLACEMENT_NOT=PLACE XW7304 BY C7300 402 603
XW7304
1 2 1V5S3_V5FILT_XW 1 2 1V5S3_V5FILT 1 2 =PP5V_S3_1V5S30V75S0
OMIT
SM C7300 R7307 1 C7302
1UF 4.7 10UF
20%
10% 5% 6.3V
10V 1/16W 2 X5R PLACEMENT_NOTE=PLACE XW7301 BY L7320
X5R MF-LF 603 OMIT
402-1 402 ROUTING NOTE:
1V5S3_VTTSNS
XW7301
SM
Place XW7301 by L7320. ISNS_1V5_S3_P OUT 47 76
=PP0V75_S0_REG 1V5S3_VDDQSNS 1 2
ISNS_1V5_S3_N OUT
C 8
1V5S3_VBST 1 2 =PPVIN_S5_1V5S30V75S0
47 76
C
1V5S3_VBST_RC
8
DIDT=TRUE
CRITICAL CRITICAL
23
24
14
22
15
R7300 1 C7332 C7333
9
2
1 1 1
0 5 C7331 1UF
C7345 0.001UF
1
R7310 VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS
5%
1/16W DIDT=TRUE 39UF-0.027OHM
20% 10%
39UF-0.027OHM
20% 20%
10.7K MF-LF D CRITICAL 2 16V 2 25V
X5R 2 16V 2 50V
CERM
1% 402 Q7320 POLY
603-1 POLY
402
1/16W B1A-SM B1A-SM
MF-LF
C7309 1
4 G CSD58858Q3 CRITICAL
2 402 3.3X3.3-QFN
0.1uF
16V CRITICAL PLACEMENT_NOTE=PLACE C7333 ACROSS Q7320 PWR AND Q7321 GND
64 25 =DDRVTT_EN 10 S3 PGOOD 13 10%

X5R
402
2 S L7320
1.0UH-13A-5.6M-OHM
11 S5 CRITICAL DIDT=TRUE
MIN_LINE_WIDTH=1 mm SM-IHLP-1
DRVH 21 1V5S3_DRVH MIN_NECK_WIDTH=0.25 mm 1 2 3
63 =DDRREG_EN U7300 20 1V5S3_LL MIN_LINE_WIDTH=1 mm 1 2 2 1 VOLTAGE=1.5V =PP1V5_S3_REG
XW7303
SYM (1 OF 2) LL 8
6 COMP TPS51116 DIDT=TRUE NO STUFF
1
PP1V5_S3_REG_R 4 3 MIN_LINE_WIDTH=1.5 mm
MIN_NECK_WIDTH=0.25 mm CRITICAL
2
QFN MIN_LINE_WIDTH=1 mm R7390 R7350 C7343

SM
OMIT DRVL 19 1V5S3_DRVL MIN_NECK_WIDTH=0.25 mm 5 2.2 EMI request 0.001 330UF

PLACEMENT_NOT=PLACE XW7303 BY C7308 1V5S3_CS 16 CS DIDT=TRUE 5%
PLACE NEXT TO L73201% 20%
ROUTING NOTE: ROUTING NOTE:
MODE 4 D CRITICAL
1/16W
MF-LF
1W
MF-1
1 C7344 C7342
0.001UF 330UF
1 C7341
10UF
2.5V
TANT
1
2 402 0612 CASE-B2-SM

Place XW7303 by C7308.
CONNECT CS_GND TO
Q7321 PIN1,2.3
USING KEVIN CONNECTION.
NC0
NC1
7 NC
12 NC
4 G
Q7321
CSD58858Q3
1V5S3_LL_SNUBBER
2
20%
50V
CERM
20%
2.5V
TANT
20%
2 6.3V
X5R
MAX CURRENT = 13A
3.3X3.3-QFN
NO STUFF
402
PLACE CLOSE TO L7320
CASE-B2-SM 603
PWM FREQ. = 400 KHZ
1 C7307 1 C7308 THRM_PAD CS_GND GND PGND VTTGND S
1 C7390 CRITICAL
100PF
22UF 22UF
25
17
18
1
5%
20% 20% 1 2 3 2 50V
2 6.3V
X5R-CERM-1 2 6.3V
X5R-CERM-1
CERM
402
603 603 EMI request
B OMIT
DDRREG_PGOOD
B
GND_1V5S3_SGND 1 2 63
ROUTING NOTE: XW7300

SM
ROUTING NOTE: R7399
100K
PUT 6 VIAS UNDER THE THERMAL PAD Place XW7300 between 5%
OMIT Pin 3 and Pin 25 1/16W
MF-LF
of U7300. 402
GND_1V5S3_CSGND 1 2 1 2 =PP3V3_S3_PDCISENS 8
XW7302
SM ROUTING NOTE:
Place XW7302 by Q7321.
PLACEMENT_NOT=PLACE XW7300 BETWEEN PIN 3 AND PIN 25 OF U7300

STATE PM_SLP_S4_L PM_SLP_S3_L PP1V5_S3 PP0V75_S0
PLACEMENT_NOT=PLACE XW7302 BY Q7321
S0 HIGH HIGH 1.5V 0.75V

S3 HIGH LOW 1.5V 0.0V
S5/G3HOT LOW LOW 0.0V 0.0V
A A
PAGE TITLE
1.5V/0.75V DDR3 SUPPLY

DRAWING NUMBER SIZE

REVISION
R
C.0.0
73 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACEMENT_NOTE=PLACE C7419 ACROSS PINS 1/2/5/6 OF Q7400 AND PINS 3/4 OF Q7401
8 =PP5V_S0_CPU_IMVP 59 8 =PPVIN_S5_CPU_IMVP
CRITICAL CRITICAL
1 2 PP5V_S0_IMVP6_VDD Q7400
IRF6710
1
C7409 1
C7417 1 C7418 1 C7419
0.001UF
C7426 MIN_NECK_WIDTH=0.2 MM S1 33UF 33UF 1UF 20%
R7412
1
1UF VOLTAGE=5V
C7435
DPRSLPVR DPRSTP* PSI* OPERATION MODE
D
1
2
20%
16V 2
20%
16V
10%
25V
2
50V
CERM PWM FREQ. = 300 KHZ
10 10% 1 2 POLY-TANT POLY-TANT 2
X5R 402
5% 6.3V 10UF DIDT=TRUE
CASED2E-SM CASED2E-SM 603-1
1/16W 2
CERM 20% 0 1 1 2-PHASE CCM 5 MAX CURRENT = 44A
D
MF-LF
402
402
2
6.3V
X5R
603
4 G 6
LOAD LINE SLOPE = -2.1 MV/A
D
=PPVIN_S5_CPU_IMVP 1 2 PPVIN_S5_IMVP6_VIN 0 1 0 1-PHASE CCM 3 S
59 8
MIN_LINE_WIDTH=0.25 MM CRITICAL CRITICALL7400
R7420 1
C7496 1 0 1 1-PHASE DCM 0.36UH-20%-40A-0.00075OHM
10 0.01UF DIDT=TRUE (IMVP6_PHASE1) =PPVCORE_S0_CPU_REG
5% 10% 1 2 8
1/16W
MF-LF 2
16V
CERM 1 0 0 1-PHASE DCM PIMA104E-SM
402
70 21
IN
PM_DPRSLPVR 402 PIMA104E-R36MN0R755
DCR=0.75MOHM
MIN_NECK_WIDTH=0.2 MM 1 2 IMVP6_BOOT1_RC 1 2 6 7
=PP3V3_S0_IMVP PP3V3_S0_IMVP6_3V3 DIDT=TRUE
1 C7420
8 1 2 DIDT=TRUE
D CRITICAL PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7400
0.001UF
C7430 R7424 Q7401 2 2 20%
50V
1 0
R7421 0.1uF 1 R7447 5% IRF6795 OMIT OMIT 2
CERM
10 10%
2.0K 1/16W 5 G 402
5% 16V
5% MF-LF
DIRECTFET-MX XW7401 XW7402
1/16W X5R
1/16W 402 S SM SM
PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7400
MF-LF 402
2 MF-LF 1 1
402 1 2 IMVP6_BOOT2_RC 3 4
GND_IMVP6_SGND 2 402 20 22 31
59 DIDT=TRUE
PPVCORE_S0_CPU_XW
C7415
VIN VDD PVCC DIDT=TRUE
R7425 C7427 1
0.1UF 1 2 1 2 1 2
0 1 0.1UF IMVP6_PHASE1_XW
CPU_VID<6> 43 36 59 IMVP6_BOOT1 5% 10%
70 11 VID6 BOOT1 10%
CRITICAL 1/16W 16V
70 11 CPU_VID<5> 42
VID5 BOOT2
26 59 IMVP6_BOOT2 MF-LF 16V 2
R7400 C7403 R7404
CPU_VID<4> 41 U7400 DIDT=TRUE 402 2 X5R
X5R
402
10K
1%
0.22uF 1
5%
70 11 VID4 QFN 402 10%
1/16W 1/16W
ISL9504BCRZ
CPU_VID<3> 40 35 59 IMVP6_UGATE1 MF-LF 6.3V MF-LF
70 11 VID3 UGATE1 CERM-X5R
1 402 402
R7445 70 11 CPU_VID<2> 39
VID2 34
402
499 38 PHASE1 59 IMVP6_PHASE1
1% 70 11 CPU_VID<1> VID1
1/16W 37 32
MF-LF 70 11 CPU_VID<0> VID0 LGATE1 59 IMVP6_LGATE1
2 402
(GND)
46 PGND1 33
IN CPU_DPRSTP_L
70 14 10 DPRSTP*
70 IMVP_DPRSLPVR 45 24 59 IMVP6_ISEN1
(IMVP6_ISEN1)
DPRSLPVR ISEN1
C 10 IN CPU_PSI_L
IMVP6_IMON
2
3
PSI*
27 IMVP6_UGATE2
C
OUT 41 IMON UGATE2 59 PLACEMENT_NOTE=PLACE C7422 ACROSS PINS 1/2/5/6 OF Q7402 AND PINS 3/4 OF Q7403
28
59 8 =PPVIN_S5_CPU_IMVP
48 PHASE2 59 IMVP6_PHASE2
3V3 CRITICAL CRITICAL
47 30 CRITICAL 1 1 C74111 C7422
(NC) CLK_EN* LGATE2 59 IMVP6_LGATE2
Q7402
1
C7401 C7408 1UF 0.001UF
FROM SMC 36 IN IMVP_VR_ON 44
VR_ON (GND) 33UF 33UF 10% 20% 1
R7401
PGND2 29 IRF6710 20% 20% 25V 50V
VR_PWRGOOD_DELAY 1 S1 16V 16V X5R CERM 3.65K
25
OUT PGOOD 1 2 2 2 603-1 2 402
1 2 POLY-TANT POLY-TANT 1%
IMVP6_VR_TT 5 D CASED2E-SM CASED2E-SM
9 VR_TT* 23 DIDT=TRUE
2 1/16W
ISEN2 59 IMVP6_ISEN2
R7408 IMVP6_NTC 6
NTC
MF-LF
402
C7405 147K
9
5 2
0.015uF 1%
4 6
10%
1/16W
7 VSUM 19 59 IMVP6_VSUM G
MF-LF 59 IMVP6_SOFT SOFT
16V 402 OCSET 8 59 IMVP6_OCSET S
X7R
402 1 2 IMVP6_RBIAS 4 18 IMVP6_VO
3 L7401
59 RBIAS VO 59 NO STUFF 1 0.36UH-20%-40A-0.00075OHM
16 CRITICAL
DROOP 59 IMVP6_DROOP
C7416 (IMVP6_PHASE2) 1 2 PLACEMENT_NOTE=PLACE C7423 CLOSE TO PIN 2 OF L7401
IMVP6_VDIFF 13
59 VDIFF 0.001UF DIDT=TRUE
PIMA104E-SM
2 PLACEMENT_NOTE=PLACE CLOSE TO PIN 2 OF L7401
R7413 DFB 17 59 IMVP6_DFB 1 2 10%
1
C7406 1 2 IMVP6_FB2 12
50V 2 PIMA104E-R36MN0R755 1
C7423
0.001UF 59 FB2 CERM DCR=0.75MOHM 2 0.001UF
1
R7418 OMIT
10%
50V
1K 59 IMVP6_FB 11
FB VSEN
14 R7417 1 C7429 402
XW7403 OMIT 20%
50V
CERM
1%
10
1K 5.36K 180pF 1 2 6 7 XW7404 CERM
1
2 402
1/16W 59 IMVP6_COMP COMP RTN 15 C7431 1% 1%
5%
1
R7416
SM
SM
2 402
R7409 MF-LF
IMVP6_VW 9 1/16W 1/16W DIDT=TRUE D CRITICAL 1
402 59 VW 0.001UF MF-LF MF-LF 2 50V 13.7K PLACEMENT_NOTE=PLACE CLOSE TO PIN 1 OF L7401 1
1K
1% IMVP6_VDIFF_RC 1 2 2
402 402
CERM
402
1%
1/16W
Q7403 1 2 1 2 1 2
IRF6795
IMVP6_PHASE2_XW
IMVP6_VSEN
1/16W MF-LF
25 5 G
IMVP6_RTN
MF-LF NC 402 DIRECTFET-MX PPVCORE_S0_CPU_XW_2

1 20% 2
2
402 R7411 50V
(IMVP6_VO) S R7405 C7404 R7407
255 GND TPAD CERM 10K 0.22uF 1
402 1% 5%
1% 3 4
21 49 1/16W 10% 1/16W
1/16W 1 6.3V
MF-LF MF-LF
MF-LF
402 59 59
R7430 402 CERM-X5R 402
2 3.92K 402
1 2
(IMVP6_FB) 1%
59 GND_IMVP6_SGND 1/16W
B VOLTAGE=0V
C7432
0.001UF 1
NOSTUFF
C7434 1 C7428 1
R7415 2
MF-LF
402
1
B
1
C7414 20% 0.12UF 0.47UF
IMVP6_VO_R
R7443
470PF 50V 10% 10%
10.5K
10%
(IMVP6_VW) CERM 10.0V 6.3V 1%
1
3.65K
50V CERM-X5R CERM-X5R 1/16W 1%
402
CERM 2 402 2 402 MF-LF 1/16W
2 402 C7433 2
402 CRITICAL MF-LF
402
C7413 0.001UF R7431 2
1 1
220PF 1
C7407 R7410 1 2 10KOHM-5%
IMVP6_COMP_RC 5% 0.001UF 6.81K (IMVP6_ISEN2)
25V 10% 0603-LF
CERM 50V 1%
20%
2 402 CERM 1/16W 50V 2
2 402 MF-LF
1 CERM
R7414 2
402
402
ERT-J1VR103J (IMVP6_VSUM)
97.6K
1% (IMVP6_VO)
1/16W
MF-LF
2 402
(IMVP6_COMP)
1 2
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
1 1
PLACEMENT_NOTE=PLACE CLOSE TO PIN 21 OF U7400 2
C7421 R7423 R7422
OMIT 0.22uF 0 0
XW7400 10%
5%
1/16W
5%
1/16W
SM 6.3V
MF-LF MF-LF
CERM-X5R
1 402 2 402 2 402
CPU_VCCSENSE_P 11 70 MIN_LINE_WIDTH MIN_NECK_WIDTH
CPU_VCCSENSE_N 11 70 59
IMVP6_OCSET 0.25 MM 0.20 MM
59
IMVP6_VSUM 0.25 MM 0.20 MM
59
GND_IMVP6_SGND 0.50 MM 0.20 MM
IMVP6_VO
IMVP6 CPU VCORE REGULATOR 59
59
59
IMVP6_DROOP
IMVP6_DFB
0.25 MM
0.25 MM
0.25 MM
0.20 MM
0.20 MM
0.20 MM
A 59
IMVP6_SOFT
IMVP6_RBIAS
0.25 MM
0.25 MM
0.20 MM
0.20 MM
59 PAGE TITLE
59
IMVP6_PHASE1
MIN_LINE_WIDTH
1.5 MM
MIN_NECK_WIDTH
0.25 MM 59
IMVP6_PHASE2
MIN_LINE_WIDTH
0.25 MM
MIN_NECK_WIDTH
0.25 MM
59
59
IMVP6_VDIFF
IMVP6_FB2
0.25 MM
0.25 MM
0.20 MM
0.20 MM
IMVP6 CPU VCore Regulator
DRAWING NUMBER SIZE
IMVP6_BOOT1 0.25 MM 0.25 MM IMVP6_BOOT2 0.25 MM 0.25 MM IMVP6_FB 0.25 MM 0.20 MM
59
IMVP6_UGATE1 1.5 MM 0.25 MM
59
IMVP6_UGATE2 0.25 MM 0.25 MM
59
IMVP6_COMP 0.25 MM 0.20 MM Apple Inc. 051-7982 D
59 59 59
REVISION
IMVP6_LGATE1 1.5 MM 0.25 MM IMVP6_LGATE2 0.25 MM 0.25 MM IMVP6_VW 0.25 MM 0.25 MM
59
IMVP6_ISEN1 0.25 MM 0.25 MM
59
IMVP6_ISEN2 0.25 MM 0.25 MM
59 R
C.0.0
59 59
59
IMVP6_RTN 0.25 MM 0.25 MM PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
IMVP6_VSEN 0.25 MM 0.25 MM
59 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
74 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACEMENT_NOTE=PLACE C7563 ACROSS PIN 5 OF Q7560 AND PINS 1/2/3 OF Q7565

8 =PPVIN_S0_MCPCORE
R7560
D VOLTAGE=5V
5V_S0_MCPREG_VIN
1
2.2
2 =PP5V_S0_MCPREG 8
CRITICAL
1
CRITICAL
1 1
D
MIN_NECK_WIDTH=0.2 MM 5%
C7563 1
C7560 C7571 1 C7561 C7590
2.2UF
1/10W 0.001UF
10%
68UF 68UF 1UF
10% 10%
MF-LF 20% 20%
R7593 603 50V
X7R 2 2 16V 2 16V 2
25V
X5R 2 16V
X5R
5 ELEC ELEC
1 1 402 603-1 603
MCPCORES0_IMON 1
0
2
C7550 C7562 C6-SM C6-SM
41
1UF 1UF D
5% 10% 10%
16V 16V
1/16W CRITICAL
16
22
X5R 2 2 X5R
1
MF-LF
402 R7561 402 402 Q7560
1K VDD PVCC 4
SIS426DN
5% (MCPCORES0_UGATE) PWRPK-12128
R7590 1/16W MIN_LINE_WIDTH=0.5 MM G
MF-LF MIN_NECK_WIDTH=0.2 MM
0 402 GATE_NODE=TRUE S
21 IN MCP_VID<0> 1 2 2 U7500 DIDT=TRUE
MCPCORES0_RBIAS 1 RBIAS QFN VIN 14
1 2 3
5%
R7565 C7564
ISL6263D
1/16W 0.22UF
MF-LF R7591 MCPCORES0_SOFT 2 SOFT 1
MCPCORES0_UGATE 1
MCPCORES0_BOOT_R 2
MCP_VID<1>
402
1
0
2
UGATE 18 1 2 R7525
21 IN 0.25 MM CRITICAL 0.001 MAX CURRENT: 13A
5% 0.2 MM DIDT=TRUE CERM-X7R
R7592 5% MCPCORES0_IMON_R 28 IMON BOOT 17 MCPCORES0_BOOT 1/10W
10V L7560 1%
1W
1/16W DIDT=TRUE 0.2 MM MF-LF 603 0.68UH-16A (Q7560 Limit)
0 MF-LF 0.25 MM 603 5%
MF
21 IN MCP_VID<2> 1 2 402 63 OUT MCPCORES0_PGOOD 31 PGOOD PHASE 19 0612
MCPCORES0_PHASE (MCPCORES0_PHASE) 1 2 PPMCPCORE_S0_R 2 1 =PPMCPCORE_S0_REG 8 60
5% MCP_VID0_R 25 VID0 MIN_LINE_WIDTH=0.5 MM SWITCHNODE MIN_LINE_WIDTH=0.5 MM
PCMB065T-SM 4 3
1NO STUFF
1/16W MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
MF-LF MCP_VID1_R 26 VID1 SWITCH_NODE=TRUE 5 R7589 VOLTAGE=1V 1
402
MCP_VID2_R 27
DIDT=TRUE
1
C7566
VID2 D 10UF
5% 1 20%
MCPCORES0_OS0 23 OFFSET0 CRITICAL 1/10W C7569 4V
NOSTUFF
1 1
NOSTUFF MF-LF
0.001UF X5R 2
R7580 R7581 MCPCORES0_OS1 24 OFFSET1 Q7565 2 603 10% 603 f = 300 kHz
PLACEMENT_NOTE=PLACE R7580 ON THE BOTTOM SIDE
20.0K 20.0K 63 IN =MCPCORES0_EN 29 VR_ON (MCPCORES0_LGATE)
4
SIS426DN MCPCORE_SNUBBER 50V
2 X7R CRITICAL
1% 1% PWRPK-12128 402 1
CRITICAL
1/16W 1/16W MCPCORES0_FDE 30 AF_EN LGATE 21 MCPCORES0_LGATE MIN_LINE_WIDTH=0.5 MM G C7565 1
PLACEMENT_NOTE=PLACE R7581 ON THE BOTTOM SIDE MF-LF MF-LF
32 FDE
S 270UF C7568
2 402 2 402 GATE_NODE=TRUE
1 1 270UF
MCPCORES0_VSEN 8 DIDT=TRUE NO STUFF C7567 20%
VSEN 1 2 3 10UF 2 2V 20%
MCPCORES0_RTN 9
C7589 20%
TANT
CASE-B4-SM
2 2V
TANT
RTN 0.001UF 4V
C MCPCORES0_VW 4 VW
2 50V 10%
X7R 402
2 X5R
603
CASE-B4-SM
C
PLACEMENT_NOTE=PLACE R7582 ON THE BOTTOM SIDE 1 1
R7582 R7583
PLACEMENT_NOTE=PLACE R7583 ON THE BOTTOM SIDE 20.0K 20.0K
1% 1% VO 12 MCPCORES0_VO (MCPCORES0_VO)
1/16W 1/16W
MF-LF MF-LF
MCPCORES0_COMP 5 COMP OCSET 3 R7569
2 402 2 402 11.3K
MCPCORES0_OCSET 1 2
MCPCORES0_FB 6 FB ISP 13 MCPCORES0_ISP 1%

1/16W
ISN 11 MCPCORES0_ISN MF-LF
1
MCPCORES0_VDIFF 7 VDIFF 402
R7573
PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP
PLACEMENT_NOT=PLACE XW7562 NEAR THE MCP, CONNECT SENSE LINSE TO CLOSEST MCPCORE AND GND BALL OF MCP ICOMP 10 MCPCORES0_ICOMP 10K C7573 1
1%
60 8 =PPMCPCORE_S0_REG 1/16W
47PF
PGND VSS THRM_PAD MF-LF
5%
50V
402 2
20
15
33
1 2 CERM
R7563 402
100 1
1% C7576 1 R7572 R7500
1/16W 0.022UF 150K 100
MF-LF 1% 1 2 MCPCORES0_ISP_R
XW7562 R7566 2
402 10%
16V 1/16W OMIT
1%
SM CERM-X5R 2 MF-LF
20 (MCPCORES0_VSEN) 402 2 402
1/16W
60 8 =PPMCPCORE_S0_REG 1 2 MCPCORES0_RSEN_P 1 2 XW7561 MF-LF
402
SM
OMIT 1%
1
1/16W
MF-LF
C7570 GND_MCPCORES0_AGND 1 2
402 0.001UF VOLTAGE=0V (MCPCORES0_ISN)
XW7563 R7568
10%
50V MIN_LINE_WIDTH=0.6 mm
SM 2 X7R MIN_NECK_WIDTH=0.2 MM
20 402 1 1
1 2 MCPCORES0_RSEN_N 1 2
R7575 C7575
(MCPCORES0_RTN) 47PF
OMIT 1% PLACEMENT_NOTE=PLACE XW7561 CLOSE TO PIN 15 OF U7500 47.0K 5%
1/16W 1%
MF-LF 50V
1/16W 2 CERM
402 MF-LF
1 402
R7571 2 402
OCP=14.5A
100 (MCPCORES0_ICOMP)
1%
1/16W
B MF-LF
2 402
B
(MCPCORES0_VW)
C7579 1
0.001UF
C7580 10%
50V
68PF X7R 2 1
1 2 402 R7576 VID<2:0> MCP TARGET
6.98K
1%
5% 1/16W 000 +1.05V
50V MF-LF
CERM C7581 402
R7577 402-1 560PF 2 001 +1.00V
133K 1 2
1 2 MCPCORES0_COMP_C
(MCPCORES0_COMP) 010 +0.95V
1%
1/16W 10%
50V
MF-LF
CERM 011 +0.90V
402
402 (MCPCORES0_FB)
C7582 100 +0.85V
R7578 560PF
100 1 2 101 +0.80V
1 2 MCPCORES0_VDIF_C
1%
10% 110 +0.75V
1/16W
MF-LF R7579 50V
402 2.21K CERM 111 +0.70V
1 2 402
(MCPCORES0_VDIFF)
1%
1/16W
MF-LF
402
PAGE TITLE
MCP CORE REGULATOR

DRAWING NUMBER SIZE

REVISION
R
C.0.0
75 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
CPUVTT POWER SUPPLY D
8 =PPVIN_S0_CPUVTTS0
PLACEMENT_NOTE=PLACE C7696 ACROSS PINS 2/3/7 AND PINS 4/5 OF Q7620
CRITICAL
C7630
1 1
C7695 1
C7696
33UF 1UF 0.001UF
20% 10% 20%
16V 25V 50V
2 2 X5R CERM
POLY-TANT 2
CASED2E-SM 603-1 402
C C
5
D CRITICAL
Q7620
4 G CSD58858Q3 =PPCPUVTT_S0_REG
8 =PP5V_S0_CPUVTTS0 3.3X3.3-QFN
L7620 8
2.2UH-8.0A
S
R7601 1 2 CRITICAL VOUT = 1.052V
301 7.2A MAX OUTPUT
1 2 PP5V_S0_CPUVTTS0_V5FILT
1
1 2 3 PCMB065T-SM
MIN_LINE_WIDTH=0.6 mm R7603 F = 320 KHZ
1% MIN_NECK_WIDTH=0.2 mm
1/16W VOLTAGE=5V 200K
10
1 1
4
MF-LF C7601 C7604 1% PLACEMENT_NOTE=Place XW7665 next to L7620

402
1UF 4.7UF 1/16W 5
MF-LF
10% V5FILT V5DRV 10%
402 2
1
C7665
10V 6.3V 2
2 2
X5R
402-1 CRITICAL
X5R-CERM
603
D CRITICAL XW7665
10UF
C7661
20% 1
U7600 Q7621 SM
2
6.3V 0.001UF
4 G CSD58858Q3 OMIT X5R
603
20%
50V
TPS51117RGY_QFN14
SYM
QFN
2 C7603 1 3.3X3.3-QFN
1
CRITICAL 2
CERM
402
63 IN =CPUVTTS0_EN 1 EN_PSV TON 2 CPUVTTS0_TON
0.1UF
DIDT=TRUE
10%
S
C7660 1
63 OUT CPUVTTS0_PGOOD 6 PGOOD VBST 14 CPUVTTS0_VBST 50V
2
330UF
X7R
MIN_LINE_WIDTH=0.6MM 20%
603-1
MIN_NECK_WIDTH=0.2MM 2.5V
(=PPCPUVTT_S0_REG) 3 VOUT DRVH 13 CPUVTTS0_DRVH 1 2 3 TANT 2
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM CASE-B2-SM
MIN_NECK_WIDTH=0.2MM DIDT=TRUE
CPUVTTS0_VFB 5 VFB LL 12 CPUVTTS0_LL
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM DIDT=TRUE
CPUVTTS0_TRIP 11 TRIP DRVL 9 CPUVTTS0_DRVL
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM CPUVTTS0_VSNS
GND THRM_PAD PGND MIN_NECK_WIDTH=0.2MM DIDT=TRUE
NO STUFF
1
15
R7670 1
7
C7670
8.06K
B 1
R7604
6.04K
1%
1/16W
MF-LF
100PF
5%
50V
CERM
2
B
1% OMIT 402
402
1/16W XW7600 2
OMIT
MF-LF SM <Ra> 2
XW7601
402
2 1 2 (GND)
SM
PLACEMENT_NOT=PLACE XW7600 BETWEEN PIN 7 AND PIN 15 OF U7600 1
R7671 1
ROUTING NOTE: 20.0K PLACEMENT_NOT=PLACE XW7601 BY C7660
1%
1/16W
Place XW7600 between Pin 7 and Pin 15 of U7600. MF-LF ROUTING NOTE:
402
2
<Rb> Place XW7601 by C7660.
GND_CPUVTTS0_SGND
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)

(CPUVTTS0_VFB)
CPUVTTS0_VOUT (=PPCPUVTT_S0_REG)
PAGE TITLE
CPU VTT(1.05V) SUPPLY

DRAWING NUMBER SIZE

REVISION
R
C.0.0
76 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 1.8V S0 SWITCHER D
8 =PP3V3_S0_P1V8S0
1 CRITICAL
CRITICAL
VI
C7760 1
U7760 L7760
10uF TPS62202 10UH-0.55A-330MOHM
20% PCAA031B-SM
6.3V SOT23-5 MAX CURRENT = 200MA
X5R
2
4
FB
603
63 =P1V8S0_EN 3
EN SW 5 P1V8S0_SW 1 2 =PP1V8_S0_REG 8
DIDT=TRUE
GND 1
2 C7762
10uF
20%
6.3V
X5R 2
603
C C
1.05V S0 PLL LDO
LDO_YES
R7743
=PP3V3_S0_MCP_PLL_VLDO 100 PP3V3_S0_MCP_PLL_VLDO_BIAS
8 1 2
5% MIN_LINE_WIDTH=0.2 MM
1/16W VOLTAGE=3.3V
MF-LF LDO_NO
402
C7740 1 R7745
1UF =PP1V05_S0_MCP_PLL_UF_R 0
8 1 2
10%
LDO_YES 6.3V
2 5%
CERM 1/16W
402 MF-LF
Vout = 1.05V 402
=PP1V05_S0_MCP_PLL_UF 8 23
4
CRITICAL MAX CURRENT = 0.5A
BIAS R7744
=PP1V5_S0_MCP_PLL_VLDO 1 9 PP1V05_S0_MCP_PLL_UF_LDO 0
8 IN0 OUT0 1 2
2
IN1 LDO_YES OUT1 10
<Ra>
LDO_YES
VOLTAGE=1.05V
5%
1/16W
TPS74701 MF-LF
2
DIDT=TRUE
402
1.37K
C7741 1 SON
1/16W
MF-LF
5 8
402
1
C7742
1%
1UF EN FB LDO_YES
LDO_YES 10% 4.7UF
6.3V
U7740 20%
MCP 1.05V S5 (AUXC) SUPPLY 2
R7746
1
CERM P1V05S0_LDO_SS 4V
402 7 3 2 X5R
SS PG P1V05S0_LDO_FB 402
NOSTUFF
B C7743 1
GND THRML_PAD
<Rb> LDO_YES B
2
0.0022UF
4.42K
10%
1/16W
MF-LF
6
11
402
50V
1%
CERM
2 LDO_YES
CRITICAL 402
R7747
1
1 C7750
8 =PP3V3_S5_P1V05S5 22UF
20%
6.3V
2 CERM
NOSTUFF
1
805 VOUT = 0.8V * (1 + RA / RB)
R7782
0
5% LDO_YES
1/16W 1 R7748
MF-LF CRITICAL
2 402 VIN 0
P1V05S0_PGOOD1 2 P1V05S0_LDO_PGOOD 63
U7750 L7770
2.2UH-3.25A 5%
ISL8009B
PP3V3_S5_P1V05S5_R_SKIP
1/16W
IHLP1616BZ-SM MF-LF
DFN 402
63 IN =P1V05_S5_EN 2
EN CRITICAL LX 8 1V05S5_SW
DIDT=TRUE
1 2 =PP1V05_S5_REG 8
63 P1V05_S5_PGOOD 3
POR VFB 6 1V05S5_FB 1 <Ra> Vout = 1.05V
C7776 1
R7780
4
SKIP RSI
5 47PF 25.5K MAX CURRENT = 0.8A
5% 1% CRITICAL
50V
1 GND THRM_PAD CERM 2 1/16W
R7783 402 2
MF-LF 1 C7771 FREQ = 1.6MHZ
7 9 402 47UF
0
5%
1/16W
<Rb> 2
20%
6.3V
1 X5R
MF-LF R7781 0805
2 402 80.6K
1%
1/16W
MF-LF
402
2
PAGE TITLE
MISC POWER SUPPLIES

VOUT = 0.8V * (1 + RA / RB) DRAWING NUMBER SIZE

REVISION
R
C.0.0
77 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V 1.05V S5 ENABLE

R7802 Power Control Signals
100K
63 8 =PP3V42_G3H_PWRCTL 2 1 PM_G2_P3V3S5_EN_L =P3V3S5_EN_L 57
OUT 3.3V_S0, 1.8V_S0 ENABLE
MAKE_BASE=TRUE
5%
1/16W
State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
MCPDDR, CPUVTT,MCPCORES0 ENABLE
MF-LF NO STUFF
402 1
C7802 1.5V S0 AND 1.05V S0 ENABLE
0.068UF
Run (S0) 1 1 1
Q7800
D
10%
D
10V
2 1 1 0
SSM3K15FV D 3 CERM
Sleep (S3)
402
SOD-VESM-HF
SMC_PM_G2_EN Soft-Off (S5) 1 0 0

57 36 7 IN
Battery Off (G3Hot) 0 0 0
1
R7800
100K
1 G S 2
5%
1/16W
R7801
MF-LF
402 5.1K
2 2 1 PM_G2_P1V05S5_EN =P1V05_S5_EN 62
MAKE_BASE=TRUE
OUT
5%
1/16W
MF-LF 1
402 C7801
0.47UF
10%
6.3V
2 CERM-X5R
402 R7859
(PM_SLP_S3_L)
100
67 36 32 21 7 PM_SLP_S3_L 2 1
IN PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
5%
1/16W
MF-LF =P5VS0_EN 64
402
OUT
=PBUSVSENS_EN 40
1
R7880 R7881 R7882 R7883 OUT
2
R7879 2 2 2 2 R7884
5% 5% 5% 5%
100K 1/16W 1/16W 1/16W 1/16W 5%
S3 ENABLE 5% MF-LF MF-LF MF-LF MF-LF 1/16W
1/16W 402 MF-LF
402 402 402
MF-LF 1 1 1 1 10K 402
22K 33K 0
402 5.1K
1
2
R7813
68K
=PP3V42_G3H_PWRCTL 2 1
63 8
5%
1/16W
Q7813
MF-LF
D 3 SSM3K15FV PM_SLP_S3_L_INVERT =P5VS3_EN_L
OUT 57 P3V3S0_EN =P3V3S0_EN
OUT 64
402
SOD-VESM-HF
NO STUFF
1 P1V8S0_EN =P1V8S0_EN 62
37 36 21 7 PM_SLP_S4_L C7813 OUT
IN
C
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE
0.068UF
MCPDDR_EN =MCPDDR_EN 64
10%
10V
OUT
MAKE_BASE=TRUE
2
CERM
1
1 G S 2 402 CPUVTTS0_EN =CPUVTTS0_EN 61
R7810 OUT
(PM_S4_STATE_L) MAKE_BASE=TRUE
100K
MCPCORES0_EN =MCPCORES0_EN 60
5% OUT
1/16W MAKE_BASE=TRUE
MF-LF
402
2
NO STUFF
C7810
1 1 1 1
R7811 0.47UF C7880 C7881 C7882 C7883 1 C7884
5.1K 0.47UF 0.47UF 0.47UF 0.47UF
1 2 0.47UF
10% 10% 10% 10%
1 2 10%
6.3V 6.3V 6.3V 6.3V
5% 6.3V
2 2 2 2
10%
CERM-X5R CERM-X5R CERM-X5R CERM-X5R 2 CERM-X5R
1/16W
402 402 402 402
MF-LF 6.3V 402
402 CERM-X5R
402
DDRREG_EN =DDRREG_EN
OUT 58
MAKE_BASE=TRUE
=USB_PWR_EN 35
OUT
NO STUFF
C7812
R7812 0.47UF
0
1 2 VOLTAGE MONITOR
1 2
5%
1/16W 10%
MF-LF 6.3V
402 CERM-X5R
402 63 8 =PP3V42_G3H_PWRCTL
P3V3S3_EN =P3V3S3_EN
OUT 64
MAKE_BASE=TRUE
8 =PP3V3_S5_PWRCTL
1
C7840
1
B
0.1uF
B 20%
10V
CERM
2
R7840
100K
5%
402
1/16W
MF-LF
6 402
2
VDD
5 SENSE 1
U7840 RESET* RSMRST_PWRGD
R7895
36
TPS3808G33DBVRG4
0
4 SOT23-6 3 1 2
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT =PP5V_S0_VMON
CT CT MR* P1V05_S5_PGOOD 62
8
TP_U7840_MR_L 5%
GND 1/16W
MF-LF
2
1 TPS3808 MR* HAS INTERNAL PULLUP
R7870 402
10K
OTHER S0 RAILS PGOOD C7841 1
1%
1/16W
0.001UF
MF-LF 8 =PP3V3_S0_PWRCTL 20%
402 50V
2
CERM
2
PP3V3_VMON_VDD 1 402
R7820
10K
353S2310
2
1 5%
1 R7871
C7870 1/16W
VDD 20.0K MF-LF
OMIT 0.1uF
1%
402
2
20%
U7870 10V
CERM
2
1/16W
MF-LF R7890
ISL88042IRTEZ 402
402
2
1
0 2
TDFN 57 P5V3V3_PGOOD
IN
8 =PP3V3_S0_VMON 3 V2MON MR* 1 5%
NC 1/16W
=PP1V5_S0_VMON
8 5 V3MON MF-LF
S0PGOOD_PWROK
402
=PP1V05_S0_VMON 6 V4MON RST* 8
8
GND THRM_PAD R7892

0
4
60 MCPCORES0_PGOOD 1 2
IN Unused PGOOD signal
5%
1/16W
A MF-LF
402
TP_DDRREG_PGOOD DDRREG_PGOOD
MAKE_BASE=TRUE
58
A
PAGE TITLE
R7891
V2MON THRESHOLD IS 2.866V
V3MON THRESHOLD IS 0.6V 61 IN CPUVTTS0_PGOOD 1
0 2
POWER SEQUENCING
V4MON THRESHOLD IS 0.6V DRAWING NUMBER SIZE
5%
1/16W
MF-LF
402 R7893 REVISION
62
0
IN P1V05S0_LDO_PGOOD 1 2
R
C.0.0
5%
1/16W
ALL_SYS_PWRGD
R7894 MF-LF
402
OUT 25 36 THE INFORMATION CONTAINED HEREIN IS THE
1
0 2 (S0PGOOD_PWROK)
5%
78 OF 109
1/16W SHEET
MF-LF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
402 IV ALL RIGHTS RESERVED <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V S0 FET
3.3V S3 FET
CRITICAL
Q7910 (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)
FDC638P_G
SM
=PP3V3_S3_FET
3.3V S3 FET
8
8 =PP3V3_S5_P3V3S3FET
6
MOSFET FDC638P =PP1V5_S3_P1V5S0FET

5 8
4
2
CHANNEL P-TYPE
9
R7912
1
C7911 1
1
CRITICAL
10K 0.033UF RDS(ON) 48 mOhm @4.5V
5%
10%
Q7901
D
16V
1/16W 2 D ROME
D MF-LF
402
2
R7910
X5R
402 3
C7910
C7902 1
DFN
NC 8
0.01UF
47K 0.1UF
1 2
P3V3S3_EN_L P3V3S3_SS
41
1 2
20% 4 G
10V
2
5% CERM KELVIN 6 P1V5_S0_KELVIN OUT
R7901
SENSE
10%
1/16W 402
MF-LF
16V 8 =PP5V_S3_MCPDDRFET S
Q7903 10K
GND
CERM
402
402
1 2 MCPDDR_SS
SSM3K15FV D 3
5%
41
SOD-VESM-HF
1/16W 7 1 2 3 5
MF-LF
1
Q7971 D 6
P1V5_S0_SENSE OUT
R7903 402
100K SSM6N15FEAPE
5% SOT563 =PP1V5_S0_FET 8
1/16W
1 G S 2 MF-LF
63 =P3V3S3_EN 402
IN 2
R7971 2 G S 1
1
C7903
47K 0.068UF 1.5V S0 FET
MCPDDR_EN_L 1 2 10%
10V
2
5%
CERM MOSFET Rome SenseFET
402
1/16W
MF-LF
Q7971 D 3
402 CHANNEL N-TYPE
MCPDDR_EN_L_RC
SSM6N15FEAPE
SOT563 RDS(ON) 6.3 mOHM @4.5V VGS
CRITICAL
LOADING 5A (EDP)
Q7930
3.3V S0 FET FDC606P_G
SOT-6
5 G S 4
3.3V S0 FET
6
=PP3V3_S0_FET 8 63 =MCPDDR_EN
IN
8 =PP3V3_S5_P3V3S0FET
5
MOSFET FDC606P
D
4
2
1
CHANNEL P-TYPE
R7932
1
C7931 1
100K 0.033UF G RDS(ON) 26 MOHM @4.5V
C 5%
10%
C
3
16V
1/16W 2
X5R
MF-LF
402
402
2 C7930
R7930 0.01UF
47K
1 2
P3V3S0_EN_L 1 2 P3V3S0_SS
5%
10%
1/16W
16V
MF-LF
Q7905 402
CERM
402
SSM3K15FV D 3
SOD-VESM-HF
1 G S 2
63 =P3V3S0_EN
IN
376S0778
CRITICAL
Q7940 MCP79 DDRVTT FET
5.0V RT S0 FET TPCP8102
5.0V RT S0 FET
23V1K-SM =PP5VRT_S0_FET 8
8 =PP5V_S3_P5VRTS0FET MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
8
3
MOSFET TPCP8102 NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

7
2
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE

6
CHANNEL P-TYPE
1
R7942
1
C7941 1
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
5
0.033UF
G
47K 10%
RDS(ON) 13.5 MOHM @4.5V BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
4
5%
16V
1/16W 2 UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
X5R
MF-LF
402
WILL EXIT SELF-REFRESH PREMATURELY.
402
2 C7940
B P5V0RTS0_EN_L 1
R7940
47K
2 P5V0RTS0_SS
0.01UF
1 2
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

B
5% LOW THROUGH VTT TERMINATION RESISTORS.
10%
1/16W
16V
MF-LF
Q7945 402
CERM
402
SSM3K15FV D 3
SOD-VESM-HF
R7975
1 G S 2 10
64 63 IN =P5VS0_EN 8 =PPVTT_S0_VTTCLAMP 2 1 VTTCLAMP_L 90mA max load @ 0.9V
5% 81mW max power
1/10W
376S0778 MF-LF
603
CRITICAL CKT FROM T18

8 =PP5V_S3_VTTCLAMP
5.0V LT S0 FET Q7948 Q7975 D 6
TPCP8102 SSM6N15FEAPE
5.0V LT S0 FET R7976
1
SOT563
23V1K-SM =PP5VLT_S0_FET 8
8 =PP5V_S3_P5VLTS0FET 100K
8
5%
3
MOSFET TPCP8102 1/16W

7
MF-LF
2
402 2 G S
6
2 1
CHANNEL P-TYPE
1
R7943
1
C7942 1
5
VTTCLAMP_EN
0.033UF
G
47K 10%
RDS(ON) 13.5 MOHM @4.5V
4
5%
16V
1/16W 2
X5R
MF-LF LOADING 1.302 A (EDP) D 3 NO STUFF
402
402
C7943 Q7975
2
R7944 SSM6N15FEAPE
C7976 1
0.01UF 0.001UF
47K SOT563
20%
1 2
P5V0LTS0_EN_L 1 2 P5V0LTS0_SS
50V
2
CERM
5%
402
A Q7947
1/16W
MF-LF
402
10%
16V
CERM
402
5 G S 4
SSM3K15FV D 3
58 25 =DDRVTT_EN PAGE TITLE
IN
SOD-VESM-HF
POWER FETS
DRAWING NUMBER SIZE

1 G S REVISION
2
64 63 IN =P5VS0_EN
R
C.0.0
79 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

LCD CONNECTOR
18 LVDS_IG_PANEL_PWR LVDS CONNECTOR:518S0650
FOUR GROUNDING VIAS SHOULD BE DISTRIBUTED
1
R9014 ALONG THE GROUND SHAPE THAT BOUND THE CONNECTOR BODY
CRITICAL
1K
5% J9000
1/16W
MF-LF 20474-030E-11
F-RT-SM
2 402 31
CRITICAL C9015 1
C9010 1
32
U9000 0.001UF
10%
0.001UF
10%
FPF1009 50V
X7R 2
50V
X7R 2
1
1 ON MFET-2X2 L9004 402 402
FERR-120-OHM-1.5A 2
8 =PP3V3_S5_LCD 2 VIN_1 VOUT_1 4 PP3V3_LCDVDD_SW 1 2 7 PP3V3_LCDVDD_SW_F 3

CRITICAL MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V MIN_LINE_WIDTH=0.30 MM
3 VIN_2
VOLTAGE=3.3V 0402-LF L9008 4
VOUT_2 5 MIN_LINE_WIDTH=0.30 MM 120-OHM-0.3A-EMI 5
C GND THRM
PAD 1 C9011 1 C9012
MIN_NECK_WIDTH=0.20 MM 1 2
7 PP3V3_S0_LCD_F
VOLTAGE=3.3V
6
7
C
1
C9009 6 7 0.1UF 10UF
0402-LF MIN_NECK_WIDTH=0.20 MM 72 18 7 LVDS_IG_A_DATA_N<0>
0.1UF 10% 20% 72 18 7 LVDS_IG_A_DATA_P<0> 8
10% 16V 6.3V
2 X5R 2 X5R
2
16V
X5R 402 603 8 =PP3V3_S0_LCD (LVDS DDC POWER) 9
402
72 18 7 LVDS_IG_A_DATA_N<1> 10
1 LVDS_IG_A_DATA_P<1> 11
1 R9009 72 18 7
R9008 100K 72 18 7 LVDS_IG_A_DATA_N<2> 12 LVDS I/F
100K 5%
13
5% 1/16W 72 18 7 LVDS_IG_A_DATA_P<2>
1/16W MF-LF 14
MF-LF 402 72 7 LVDS_IG_A_CLK_F_N
2
402
2 72 7 LVDS_IG_A_CLK_F_P 15
18 7 LVDS_IG_DDC_CLK CRITICAL
16
18 7 LVDS_IG_DDC_DATA L9080 17
90-OHM-200MA NC
AMC2012-SM 68 47 7 PPVOUT_S0_LCDBKLT 18
SYM_VER-1
PLACEMENT_NOTE=PLACE CLOSE TO J9000

19 LED BKLT I/F
72 18 LVDS_IG_A_CLK_N 4 1 1 C9017 20
1000PF NC
5% 68 7 LED_RETURN_6 21
3 2 2 50V
C0G-CERM 22
72 18 LVDS_IG_A_CLK_P
603 68 7 LED_RETURN_5
68 7 LED_RETURN_4 23
L9050 LED_RETURN_1 26
68 7
8 =PP5V_S3_CAMERA 2 1 7 PP5V_S3_CAMERA_F 27
MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
28
FERR-120-OHM-1.5A MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V VOLTAGE=5V
0402-LF 29
C9016 1
30
0.1uF CAMERA I/F
20%
10V
B CERM
402
2
33
34
B
CRITICAL
L9060
90-OHM
DLP0NS
CAMERA
SYM_VER-1
USB_CAMERA_P 3 4 73 7 USB_CAMERA_CONN_P
73 20 OUT
73 20 USB_CAMERA_N 2 1 73 7 USB_CAMERA_CONN_N
OUT
PLACEMENT_NOTE=PLACE CLOSE TO J9000.
PAGE TITLE
LVDS CONNECTOR
DRAWING NUMBER SIZE

REVISION
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8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
18 =MCP_HDMI_TXC_P DP_ML_P<3> 67 72
MAKE_BASE=TRUE
18 =MCP_HDMI_TXC_N DP_ML_N<3> 67 72
MAKE_BASE=TRUE
18 =MCP_HDMI_TXD_P<0> DP_ML_P<2> 67 72
MAKE_BASE=TRUE
18 =MCP_HDMI_TXD_N<0> DP_ML_N<2> 67 72
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
18 =MCP_HDMI_HPD DP_HPD 67
D 18 =MCP_HDMI_DDC_CLK DP_IG_DDC_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
66 D
18 =MCP_HDMI_DDC_DATA DP_IG_DDC_DATA 66
MAKE_BASE=TRUE
DP_AUX_CH_C_N
BI 67 72
C9300
R9300 0.1UF
DP_IG_DDC_DATA 1
33
2 1 2
72 DP_AUX_CH_SW_N
66 BI
5%
1/16W 10%
MF-LF 16V
402 X5R
402
Display Port Interoperability spec says that sources
DP_AUX_CH_C_P
or sinks which do both DP and DVI must depend on the BI 67 72
external adapter for pull ups on DDC lines (since DP

AUX CH has 100K pull up/down on the MLB)..
C9301
R9301 0.1UF
DP_IG_DDC_CLK 1
33
2 1 2
72 DP_AUX_CH_SW_P
66 BI
5%
1/16W 10%
MF-LF 16V
402 X5R
402
C 3 D D 6
C
Q9300 Q9300
SSM6N15FEAPE SSM6N15FEAPE
SOT563 SOT563
4
S G 5 2 G S 1
DP_IG_AUX_CH_P
72 18 BI
DP_IG_AUX_CH_N
72 18 BI
=PP5V_S0_DP_AUX_MUX
8
1
R9302
100K
1 5%
R9306 1/16W
MF-LF
1K 2
402
5%
1/16W
MF-LF
402
2
DDC_CA_DET_LS5V_L
B B
Q9301
3 D SSM3K15FV
SOD-VESM-HF
2
S G 1
DP_CA_DET
67 IN
DP_IG_CA_DET
OUT 18
PAGE TITLE
DISPLAYPORT SUPPORT
DRAWING NUMBER SIZE

REVISION
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8 7 6 5 4 3 2 1
POR IS PLASTIC MINI DP CONNECTOR BUT METAL PART’S SCHEMATIC AND CAD SUMBOLS
HAVE BEEN USED BEACUSE ITS LAND PATTERN CAN ACCOMODATE BOTH TYPES
Port Power Switch
DP_ESD DP_ESD
D CRITICAL CRITICAL
D9410
CRITICAL
D9410
D
U9480 L9400 RCLAMP0524P RCLAMP0524P
TPS2051B FERR-120-OHM-3A SLP2510P8 SLP2510P8
SOT23
5 1 1 2
8 =PP3V3_S5_DP_PORT_PWR IN OUT PP3V3_S0_DPILIM PP3V3_S0_DPPWR
MIN_LINE_WIDTH=0.38 MM MIN_LINE_WIDTH=0.38 MM
0603
MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
PM_SLP_S3_L 4 3 IO IO IO IO
63 36 32 21 7 IN EN OC* TP_DPPWR_OC_L VOLTAGE=3.3V
1
VOLTAGE=3.3V
2 1 5 4
C9400
GND 9 NC NC 10 6 NC NC 7
4.7UF
2 20%
GND
GND
6.3V
2
X5R-CERM
402
3 3
CRITICAL
1 1
C9480 C9481
22UF 4.7UF
C9485 1 1
C9486
20% 20% 22UF 22UF
6.3V 6.3V 20% 20%
X5R-CERM-1 2 2 X5R-CERM 6.3V 6.3V
2 2
603 402 X5R-CERM-1 X5R-CERM-1
603 603
1
R9420
100K
5%
1/16W
MF-LF
402
2
CRITICAL OMIT
HDMI_CEC
J9400
MINIDSPLYPRT-K83
F-RT-THSM
1 FL9400
R9425 12-OHM-100MA
C 1M
5%
BOT ROW TOP ROW 72 DP_ML_CONN_P<0> 1
TCM1210-4SM
SYM_VER-2 4
72 DP_ML_C_P<0> C9410 1 2 DP_ML_P<0>
C
1/16W TH PINS SM PINS IN 66 72
MF-LF 72 DP_ML_CONN_N<0> 10% 16V X5R 402
2 1 0.1uF
402 HOT_PLUG_DETECT GND
FL9403 2
4 3
FL9401 2 3 72 DP_ML_C_N<0> C9411 1 2 DP_ML_N<0>
12-OHM-100MA CONFIG1 ML_LANE0P 12-OHM-100MA IN 66 72
10% 16V X5R 402
TCM1210-4SM 6 5 TCM1210-4SM 0.1uF
4 SYM_VER-2 1 CONFIG2 ML_LANE0N 1 SYM_VER-2 4
72 66 IN DP_ML_P<3> C9414 1 2 72 DP_ML_C_P<3> 8
GND
7 72 DP_ML_C_P<1> C9412 1 2 DP_ML_P<1> IN 66 72
10% 16V X5R 402
GND 10% 16V X5R 402
0.1uF DP_ML_CONN_P<3> 10 9 DP_ML_CONN_P<1> 0.1uF
72 ML_LANE3P ML_LANE1P
72
DP_ML_N<3> C9415 1 2 72 DP_ML_C_N<3> 3 2 72 DP_ML_CONN_N<3> 12 11 72 DP_ML_CONN_N<1> 2 3 FL9402 72 DP_ML_C_N<1> C9413 1 2 DP_ML_N<1>

72 66 IN ML_LANE3N ML_LANE1N 12-OHM-100MA IN 66 72
10% 16V X5R 402 10% 16V X5R 402
0.1uF 14 13 TCM1210-4SM 0.1uF
GND GND 1 SYM_VER-2 4
72 66 BI DP_AUX_CH_C_P 16
AUX_CHP ML_LANE2P
15 72 DP_ML_CONN_P<2> 72 DP_ML_C_P<2> C9416 1 2 DP_ML_P<2> IN 66 72
10% 16V X5R 402
18 17 0.1uF
AUX_CHN ML_LANE2N
DP_AUX_CH_C_N 20 19 72 DP_ML_CONN_N<2> 2 3 72 DP_ML_C_N<2> C9417 1 2 DP_ML_N<2>
72 66 BI DP_PWR RETURN IN 66 72
10% 16V X5R 402
DP_ESD 0.1uF
67 8 =PP3V3_S0_DPCONN
CRITICAL SHIELD PINS
1
R9443 1 D9411 22 21
100K R9442 RCLAMP0524P 514-0691
1
5% 100K
1/16W 5%
R9421 SLP2510P8
MF-LF 1/16W 100K

402 MF-LF 5%
2
402 1/16W
DP_CA_DET 2
66 OUT MF-LF
402
2 IO IO 1
2
6 9 NC NC 10 DP_ESD
D CRITICAL
GND
Q9440 DP_ESD
2N7002DW-X-G
SOT-363 CRITICAL
D9411
S G 2 DP_CA_DET_L_Q 3 RCLAMP0524P
D9400 SLP2510P8
3
1 RCLAMP0504F
SC70-6-1
D
Q9440
B 2N7002DW-X-G
SOT-363
S G 5 DP_CA_DET_Q 1
6
5
6
IO
NC
IO
NC
4
7
B
DP to DVI/HDMI
GND
4
1 2 5
R9422 Cable Adapter
1M (CA) has 100k 3
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm 5%
4
1/16W pull-up to DP_PWR.
MF-LF
3
402
2
67 8 =PP3V3_S0_DPCONN
1
R9445 1
10K
R9444
5% 10K
1/16W 5%
MF-LF 1/16W
402 MF-LF
2
402
DP_HPD 2
66 OUT
6
MCP79 requires pull

R9446
1
Q9441 D
down HPD input with
100K 2N7002DW-X-G
5% 100K if DP_HPD is used. SOT-363
1/16W S G 2 DP_HPD_L_Q
MF-LF
402
2 3
1
D
Q9441
A 2N7002DW-X-G
SOT-363
S G 5 DP_HPD_Q SYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009 A
PAGE TITLE
4
R9423
1
DP Source must pull
down HPD input with
DisplayPort Connector
100K DRAWING NUMBER SIZE
greater than or equal
1/16W
MF-LF
5%
to 100K (DPv1.1a). Apple Inc. 051-7982 D

402
2
REVISION
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8 7 6 5 4 3 2 1
D D
CRITICAL PLACEMENT_NOTE=PLACE NEAR L9710

R9700 CRITICAL
0.020 MIN_LINE_WIDTH=0.5 MM CRITICAL
1% MIN_NECK_WIDTH=0.38 MM L9710
0.25W
MF-LF VOLTAGE=9V 10UH-2.1A D9710
SOD-123
805 PLACEMENT_NOTE=PLACE CLOSE TO L9710 PLACEMENT_NOTE=PLACE C9717 CLOSE TO D9710 PIN 2 & XW9701
69 PPBUS_S0_LCDBKLT_PWR 1 2 PPVIN_BKL 1 2 PPVOUT_S0_LCDBKLT_SW 1 2 PPVOUT_S0_LCDBKLT 7 47 65
3 4 1 C9713 IHLP2020BZ11-SM
MIN_LINE_WIDTH=0.5 MM NOSTUFF MIN_LINE_WIDTH=0.5 MM
CRITICAL 1
MIN_NECK_WIDTH=0.38 MM CRITICAL CRITICAL MIN_NECK_WIDTH=0.24 MM
0.1UF
PLACEMENT_NOTE=PLACE CLOSE TO L9710 C9710 1 R9730 VOLTAGE=50V
SWITCH_NODE=TRUE
RB160M-40 1
C9715 1
C9716 1
C9717
VOLTAGE=50V
10%
25V 10UF 10 DIDT=TRUE 4.7UF 2.2UF 1000PF
2 5% OMIT
X5R
402
10%
25V 1/16W f = 600kHz 20%
50V
10%
50V
10%
100V
XW9701
PLACEMENT_NOTEs: X5R 2 MF-LF 2 X7R-CERM 2 X7R 2 X7R
76 47 OUT ISNS_LCDBKLT_P 805 2
402
1206 1206 603
SM
GND_LCDBKLT_PGND 68 68 GND_LCDBKLT_PGND 1 2
LCDBKLT_VIN MIN_LINE_WIDTH=0.6 mm
76 47 OUT ISNS_LCDBKLT_N (C9710-C9711) MIN_NECK_WIDTH=0.4 MM
1
WF: C9711 AND C9717 NOT IN REF SCHEMATIC.
VIN
20 4
1 C9711 PP2V5_S0_LCDBKLT VDC1 SWA
1UF MIN_NECK_WIDTH=0.2 MM SWB 3
10%
25V VOLTAGE=2.5V
2 X5R 23 24
1 PLACEMENT_NOTE=PLACE CLOSE TO U9700 PIN 1 603-1
PP5V5_S0_LCDBKLT VDC2 VOUT NOSTUFF NOSTUFF PLACEMENT_NOTEs:
C9727 MIN_LINE_WIDTH=0.3 MM NOSTUFF
C 5%
1000PF
50V
VOLTAGE=5.5V
CRITICAL R9715 1
1
C9721
100PF
1
C9723
100PF
1
C9725
100PF PLACE NEAR U9700 C
2 C0G-CERM C9700 1 1
C9701 5%
50V
5%
50V
5%
50V
603 2.2UF 2.2UF U9700 1M
1%
2 CERM 2 CERM 2 CERM (C9721-C9726)
20% 20% 402 402 402
10V 10V MC34845 OVP = Vovp * (1 + Ra/Rb) 1/16W
X5R-CERM 2 2 X5R-CERM MF-LF NOSTUFF
402 402
LLP VOVP = 6.9V +/- 0.35V 402 NOSTUFF NOSTUFF
2
C9722 1
C9724 1
C9726 1
(SGND) 22 <Ra> 100PF 100PF 100PF
R9725 OVP LCDBKLT_OVP 5% 5% 5%
2
0 1 16
50V
CERM 2
50V
CERM 2
50V
CERM 2
R9717
69 18 IN LVDS_IG_BKL_PWM LVDS_IG_BKL_PWM_R PWM 402 402 402
18 7 10.2
5% WAKE CH1 BKL_MC_CH1 1 2 LED_RETURN_1 IN 7 65
1/16W MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
MF-LF MIN_NECK_WIDTH=0.20 mm 1% R9718 MIN_NECK_WIDTH=0.20 mm
402 6 8
1/16W 10.2
EN CH2 BKL_MC_CH2 MF-LF 1 2 LED_RETURN_2 IN 7 65
MIN_LINE_WIDTH=0.5 mm 402 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm 1% R9719 MIN_NECK_WIDTH=0.20 mm
17 9
1/16W 10.2
1
LCDBKLT_COMP COMP CH3 BKL_MC_CH3 MF-LF 1 2 LED_RETURN_3 IN 7 65
MIN_LINE_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 mm 402 MIN_LINE_WIDTH=0.5 mm
R9726 MIN_NECK_WIDTH=0.20 mm
R9720 1% MIN_NECK_WIDTH=0.20 mm
LCDBKLT_ISET 15
22K ISET 10 BKL_MC_CH4
10.2 1/16W
5% MIN_LINE_WIDTH=0.2 MM CH4 1 2 MF-LF LED_RETURN_4 IN 7 65
1/16W
MF-LF C9705 MIN_NECK_WIDTH=0.20 mm 1% R9721 MIN_NECK_WIDTH=0.20 mm
1 1 1/16W 10.2
2 402 10% 50V R9710 CH5 11 BKL_MC_CH5 MF-LF 1 2 LED_RETURN_5 7 65
0.0022UF IN
CERM 402 7.68K MIN_LINE_WIDTH=0.5 mm 402
R9722 MIN_LINE_WIDTH=0.5 mm
1% MIN_NECK_WIDTH=0.20 mm 1% MIN_NECK_WIDTH=0.20 mm
2 1/16W 12 BKL_MC_CH6
1/16W 10.2
MF-LF CH6 MF-LF 1 2 LED_RETURN_6 IN 7 65
2 402 1%
MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm
LCDBKLT_COMP_RC <Riset> 1/16W
MF-LF
402
14 LCDBKLT_FAIL
1 FAIL
R9705 1
PGNDA
PGNDB
10K C9706 1 R9716
R9702 1
GND
1% 56PF 243K
1/16W THRM 0 1%
5% PAD
MF-LF 50V NOSTUFF 5% 1/16W OMIT
2 402 CERM 2 1/16W MF-LF
XW9700
5
2
13
19
21
25
402 MF-LF 402 2
402 SM
2
<Rb>
B ISET = 153mA / <Riset>
GND_LCDBKLT_SGND
1 2
B
VOLTAGE=0V
PLACEMENT_NOT=PLACE XW9700 FAR FROM THE NOISY PINS 3 AND 4
13.3 Inch Panel (9 LEDs per string)

TARGET: ISET = 20MA, OVP = 35V
ACTUAL: ISET = 19.9MA, OVP = 35.2V
A SYNC_MASTER=VEMURI_K19I SYNC_DATE=02/09/2009 A
PAGE TITLE
LCD Backlight Driver (MC34845)

DRAWING NUMBER SIZE

REVISION
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8 7 6 5 4 3 2 1
CRITICAL
Q9806
FDC638APZ_SBMS001 PPBUS S0 LCDBkLT FET
SSOT6-HF
F9800 MOSFET FDC638APZ
6
2AMP-32V
5
CHANNEL P-TYPE
4
1 2
8 =PPBUS_S0_LCDBKLT PPBUS_S0_LCDBKLT_FUSED
IN
D
2
D MIN_LINE_WIDTH=0.4 mm
RDS(ON) 43 mOhm @4.5V
1
1
VOLTAGE=12.6V 0402-HF VOLTAGE=12.6V
R9808 1
C9802
301K
0.1UF LOADING 0.4 A (EDP)
1%
3
10%
1/16W
16V
MF-LF 2
X5R
402
2 402
PPBUS_S0_LCDBKLT_EN_DIV
1
R9809
147K
1%
1/16W
MF-LF
402
2
PPBUS_S0_LCDBKLT_EN_L
Q9807 D 3
SSM6N15FEAPE
SOT563
5 G S 4
PPBUS_S0_LCDBKLT_PWR
OUT 68
69 18 LVDS_IG_BKL_ON
IN BKLT_EN_L
VOLTAGE=12.6V
Q9807 D 6
SSM6N15FEAPE
SOT563
C BKLT_PLT_RST_L
2 G S 1
C
25 IN
B B
LVDS_IG_BKL_ON 18 69
LVDS_IG_BKL_PWM 18 68
1 1
R9840 R9841
1K 1K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 402
2 2
MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS
PAGE TITLE
LCD Backlight Support

DRAWING NUMBER SIZE

REVISION
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8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
TABLE_PHYSICAL_RULE_HEAD
NET_TYPE
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM
FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_D_L<15..0> 10 14
FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DINV_L<0> 10 14
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<0> 10 14

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<0> 10 14

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
FSB 4X Signal Groups

FSB_DATA * =2x_DIELECTRIC ? FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ?
FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DINV_L<1> 10 14
FSB_DSTB * =3x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<1> 10 14
D FSB_ADDR * =STANDARD ?
TABLE_SPACING_RULE_ITEM
FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ?


D

FSB_ADSTB * =2x_DIELECTRIC ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ?
FSB_1X * =STANDARD ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<2> 10 14

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<3> 10 14
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_A_L<16..3> 10 14
FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_REQ_L<4..0> 10 14
Signals
FSB 2X
FSB 2X signals / groups shown in signal table on right.
FSB_ADSTB0 FSB_50S FSB_ADSTB FSB_ADSTB_L<0> 10 14
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_A_L<35..17> 10 14
FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_ADSTB_L<1> 10 14

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. FSB_1X FSB_50S FSB_1X FSB_ADS_L 10 14
FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ0_L 10 14

Design Guide recommends each strobe/signal group is routed on the same layer.
FSB_BREQ1_L FSB_50S FSB_1X FSB_BREQ1_L 14
Intel Design Guide recommends FSB signals be routed only on internal layers.
FSB_1X FSB_50S FSB_1X FSB_BNR_L 10 14
FSB 1X Signals
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. FSB_1X FSB_50S FSB_1X FSB_BPRI_L 10 14
FSB_1X FSB_50S FSB_1X FSB_DBSY_L 10 14

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
FSB_1X FSB_50S FSB_1X FSB_DEFER_L 10 14
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
FSB_1X FSB_50S FSB_1X FSB_DRDY_L 10 14
FSB_1X FSB_50S FSB_1X FSB_HIT_L 10 14

CPU Signal Constraints FSB_HITM_L 10 14
FSB_1X FSB_50S FSB_1X
ALLOW ROUTE
C PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_50S
FSB_1X
FSB_1X
FSB_LOCK_L
FSB_CPURST_L
10 14
10 13 14
C
CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_1X FSB_50S FSB_1X FSB_RS_L<2..0> 10 14
CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL FSB_1X FSB_50S FSB_1X FSB_TRDY_L 10 14
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. CPU_ASYNC CPU_50S CPU_AGTL CPU_A20M_L 10 14
CPU_BSEL CPU_50S CPU_AGTL CPU_BSEL<2..0> 9 10

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_FERR_L CPU_50S CPU_8MIL CPU_FERR_L 10 14
CPU_ASYNC CPU_50S CPU_AGTL CPU_IGNNE_L 10 14

CPU_AGTL * =STANDARD ? CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ?
CPU_INIT_L CPU_50S CPU_AGTL CPU_INIT_L 10 14
CPU_8MIL * 8 MIL ? CPU_ASYNC_R CPU_50S CPU_AGTL CPU_INTR 10 14

CPU_ASYNC_R CPU_50S CPU_AGTL CPU_NMI 10 14

CPU_COMP * 25 MIL ?
CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PROCHOT_L 10 14 37
CPU_GTLREF * 25 MIL ? SR DG recommends at least 25 mils, >50 mils preferred CPU_PWRGD CPU_50S CPU_AGTL CPU_PWRGD 10 13 14
CPU_ASYNC CPU_50S CPU_AGTL CPU_SMI_L 10 14
CPU_ITP * =2:1_SPACING ?
CPU_ASYNC CPU_50S CPU_AGTL CPU_STPCLK_L 10 14
CPU_VCCSENSE * 25 MIL ? PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L 10 14 37
FSB_CPUSLP_L CPU_50S CPU_AGTL FSB_CPUSLP_L 10 14

Most CPU signals with impedance requirements are 55-ohm single-ended.
CPU_FROM_SB CPU_50S CPU_AGTL CPU_DPSLP_L 10 14
Some signals require 27.4-ohm single-ended impedance.
CPU_DPRSTP_L CPU_50S CPU_AGTL CPU_DPRSTP_L 10 14 59
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 CPU_ASYNC CPU_50S CPU_AGTL FSB_DPWR_L 10 14
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_VDD 14
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_GND 14
MCP FSB COMP Signal Constraints MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_VCC 14

MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_GND 14

ON LAYER?
FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 10 14

MCP_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_CLK_CPU_N 10 14
B TABLE_SPACING_RULE_HEAD
FSB_CLK_CPU
FSB_CLK_ITP
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB
CLK_FSB FSB_CLK_ITP_P 13 14 B
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N 13 14
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_P 14
MCP_FSB_COMP * 8 MIL ?
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_N 14
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU_IERR_L CPU_50S CPU_IERR_L 10
FSB Clock Constraints PM_DPRSLPVR CPU_50S CPU_AGTL PM_DPRSLPVR 21 59

(See above) CPU_50S CPU_AGTL IMVP_DPRSLPVR 59

ON LAYER?
CPU_GTLREF CPU_50S CPU_GTLREF CPU_GTLREF 10 26

CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
CPU_COMP CPU_50S CPU_COMP CPU_COMP<3> 10
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 10

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_COMP CPU_50S CPU_COMP CPU_COMP<1> 10
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<0> 10
CLK_FSB * =3x_DIELECTRIC ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC ?
XDP_TDI CPU_50S CPU_ITP XDP_TDI 10 13

XDP_TDO CPU_50S CPU_ITP XDP_TDO 10 13
XDP_TMS CPU_50S CPU_ITP XDP_TMS 10 13
XDP_TCK CPU_50S CPU_ITP XDP_TCK 10 13
XDP_TRST_L CPU_50S CPU_ITP XDP_TRST_L 10 13
XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L<4..0> 10 13
XDP_BPM_L5 CPU_50S CPU_ITP XDP_BPM_L<5> 10 13
(FSB_CPURST_L) CPU_50S CPU_ITP XDP_CPURST_L 13
CPU_50S CPU_8MIL CPU_VID<6..0> 11 59
CPU_50S CPU_8MIL IMVP6_VID<6..0>
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 11 59
A CPU_VCCSENSE
(CPU_VCCSENSE)
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE_N
IMVP6_VSEN_P
11 59
PAGE TITLE
(CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N
CPU/FSB Constraints
DRAWING NUMBER SIZE

REVISION
R
C.0.0
100 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Memory Bus Constraints Memory Net Properties
NET_TYPE
MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD

MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK_P<5..0> 15 27
MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK_N<5..0> 15 27
MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CKE<3..0> 15 27
MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CS_L<3..0> 15 27

MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF
MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_ODT<3..0> 15 27
TABLE_SPACING_RULE_HEAD
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_A<14..0> 15 27

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
MEM_A_BA<2..0> 15 27
D
MEM_A_CMD MEM_40S_VDD MEM_CMD
D MEM_CLK2MEM * =4:1_SPACING ?
MEM_A_CMD
MEM_A_CMD
MEM_40S_VDD
MEM_40S_VDD
MEM_CMD
MEM_CMD
MEM_A_RAS_L
MEM_A_CAS_L
15 27
15 27
MEM_CTRL2CTRL * =2:1_SPACING ?
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_WE_L 15 27
MEM_CTRL2MEM * =2.5:1_SPACING ?
MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ<7..0> 15 27
MEM_CMD2CMD * =1.5:1_SPACING ? MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ<15..8> 15 27

MEM_CMD2MEM * =3:1_SPACING ?
MEM_DATA2DATA * =1.5:1_SPACING ? MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ<39..32> 15 27


MEM_DATA2MEM * =3:1_SPACING ?
MEM_DQS2MEM * =3:1_SPACING ? MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQ<63..56> 15 27

MEM_2OTHER * 25 MIL ? MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DM<0> 15 27
MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DM<1> 15 27

Memory Bus Spacing Group Assignments MEM_A_DM<3>
MEM_A_DQ_BYTE3 MEM_40S MEM_DATA 15 27
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DM<4> 15 27
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM
MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DM<7> 15 27
MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_P<0> 15 27
MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_N<0> 15 27

MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_DATA * MEM_CMD2MEM
MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_P<1> 15 27
MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_N<1> 15 27

C NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
15 27
15 27
C
MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_A_DQS3 MEM_70D MEM_DQS

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_DATA MEM_CTRL * MEM_DATA2MEM
MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS_P<5> 15 27
MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA
MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS_N<6> 15 27

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_P<5..0> 15 28

MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_CLK * * MEM_2OTHER
MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_N<5..0> 15 28
MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER

MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CKE<3..0> 15 28
MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CS_L<3..0> 15 28

MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_ODT<3..0> 15 28

MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DATA * * MEM_2OTHER
MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_A<14..0> 15 28

MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_DQS * * MEM_2OTHER
MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_BA<2..0> 15 28
Need to support MEM_*-style wildcards! MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_RAS_L 15 28
DDR2: MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CAS_L 15 28
DQ signals should be matched within 20 ps of associated DQS pair. MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_WE_L 15 28
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.

MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ<7..0> 15 28
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
B DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
15 28
15 28
B
DDR3: MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ<55..48> 15 28
DQ signals should be matched within 5 ps of associated DQS pair. MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQ<63..56> 15 28
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DM<0> 15 28
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DM<6> 15 28
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DM<7> 15 28
MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS_P<0> 15 28

MCP MEM COMP Signal Constraints MEM_B_DQS_N<0>
MEM_B_DQS0 MEM_70D MEM_DQS 15 28
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_P<1> 15 28
ON LAYER?
MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_N<1> 15 28

MCP_MEM_COMP * Y 7 MIL 7 MIL =STANDARD =STANDARD =STANDARD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS_P<3> 15 28


MCP_MEM_COMP * 8 MIL ?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS_N<4> 15 28
A MEM_B_DQS6
MEM_B_DQS7
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
15 28
15 28
PAGE TITLE
Memory Constraints
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD 16 DRAWING NUMBER SIZE
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND 16
REVISION
R
C.0.0
101 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
PCI-Express ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
ON LAYER? PCIE_90D PCIE PCIE_MINI_R2D_P 30
PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF PCIE_90D PCIE PCIE_MINI_R2D_N 30
PCIE_MINI_R2D PCIE_90D PCIE PCIE_MINI_R2D_C_P 17 30

CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
PCIE_90D PCIE PCIE_MINI_R2D_C_N 17 30
PCIE_MINI_D2R PCIE_90D PCIE PCIE_MINI_D2R_P 17 30

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCIE_90D PCIE PCIE_MINI_D2R_N 17 30
PCIE * =3X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ?

PCIE_90D PCIE PCIE_FW_R2D_P
CLK_PCIE * 20 MIL ? PCIE_90D PCIE PCIE_FW_R2D_N
D MCP_PEX_COMP * 8 MIL ?
PCIE_FW_R2D PCIE_90D
PCIE_90D
PCIE
PCIE
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
9 17
9 17
D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_FW_D2R PCIE_90D PCIE PCIE_FW_D2R_P 9 17
PCIE_90D PCIE PCIE_FW_D2R_N 9 17
PCIE_90D PCIE PCIE_FW_D2R_C_P
PCIE_90D PCIE PCIE_FW_D2R_C_N
MCP_PE1_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P 17 30
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N 17 30
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CONN_P 7 30
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CONN_N 7 30
MCP_PE4_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FC_P
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_FC_N
PCIE_90D PCIE CONN_PCIE_MINI_R2D_P 7 30
PCIE_90D PCIE CONN_PCIE_MINI_R2D_N 7 30
PCIE_90D
PCIE CONN_PCIE_MINI_D2R_P 7 30
PCIE_90D
PCIE CONN_PCIE_MINI_D2R_N 7 30
MCP_PEX_CLK_COMP MCP_PEX_COMP MCP_PEX_CLK_COMP 17
C Digital Video Signal Constraints

C
ON LAYER?
DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_P
TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_N

MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD
TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_N<2..0>

DP_ML DP_100D DISPLAYPORT DP_ML_P<3..0> 66 67
DISPLAYPORT * =3x_DIELECTRIC ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? DP_100D DISPLAYPORT DP_ML_C_P<3..0> 67

DP_ML DP_100D DISPLAYPORT DP_ML_N<3..0> 66 67

LVDS * =3x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ?
DP_100D DISPLAYPORT DP_ML_C_N<3..0> 67
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DP_AUX_CH DP_100D DISPLAYPORT DP_IG_AUX_CH_P 18 66
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DP_100D DISPLAYPORT DP_IG_AUX_CH_N 18 66
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. DP_100D DISPLAYPORT DP_AUX_CH_SW_P 66
Max length of LVDS/DisplayPort/TMDS traces: 12 inches. DP_100D DISPLAYPORT DP_AUX_CH_SW_N 66
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4. DP_100D DISPLAYPORT DP_AUX_CH_C_P 66 67
DP_100D DISPLAYPORT DP_AUX_CH_C_N 66 67
SATA Interface Constraints MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_RSET 18 24

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_HDMI_VPROBE MCP_DV_COMP MCP_HDMI_VPROBE 18 24
ON LAYER?
SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_P 18 65
LVDS_100D LVDS LVDS_IG_A_CLK_F_P 7 65

SATA_90D_HDD * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_N 18 65
LVDS_100D LVDS LVDS_IG_A_CLK_F_N 7 65

B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
7 18 65
7 18 65
B
SATA * =4x_DIELECTRIC ? SATA TOP,BOTTOM =3x_DIELECTRIC ?
SATA_TERMP * 8 MIL ?
I183 DP_ML DP_100D DISPLAYPORT DP_ML_CONN_P<3..0> 67

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
DP_100D DISPLAYPORT DP_ML_CONN_N<3..0> 67
I182
MCP_IFPAB_RSET MCP_DV_COMP MCP_IFPAB_RSET 18 24
MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE 18 24
SATA_HDD_R2D SATA_90D_HDD SATA SATA_HDD_R2D_C_P 20 34
SATA_90D_HDD SATA SATA_HDD_R2D_C_N 20 34
SATA_90D_HDD SATA SATA_HDD_R2D_P 7 34
SATA_90D_HDD SATA SATA_HDD_R2D_N 7 34
SATA_90D_HDD SATA SATA_HDD_R2D_UF_P 34
SATA_90D_HDD SATA SATA_HDD_R2D_UF_N 34
SATA_HDD_D2R SATA_90D_HDD SATA SATA_HDD_D2R_P 20 34
SATA_90D_HDD SATA SATA_HDD_D2R_N 20 34
SATA_90D_HDD SATA SATA_HDD_D2R_C_P 7 34
SATA_90D_HDD SATA SATA_HDD_D2R_C_N 7 34
SATA_90D_HDD SATA SATA_HDD_D2R_UF_P 34
SATA_90D_HDD SATA SATA_HDD_D2R_UF_N 34
SATA_ODD_R2D SATA_100D SATA SATA_ODD_R2D_C_P 20 34
A SATA_100D
SATA_100D
SATA
SATA
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
20 34
7 34
PAGE TITLE
SATA_100D
SATA_100D
SATA
SATA
SATA_ODD_R2D_N
SATA_ODD_R2D_UF_P
7 34
34
MCP Constraints 1
DRAWING NUMBER SIZE
SATA_ODD_R2D_UF_N 34
SATA_ODD_D2R
SATA_100D
SATA_100D
SATA
SATA SATA_ODD_D2R_P 20 34 Apple Inc. 051-7982 D

REVISION
SATA_ODD_D2R_N
SATA_100D
SATA_100D
SATA
SATA SATA_ODD_D2R_C_P
20 34
7 34
R
C.0.0
SATA_ODD_D2R_C_N
SATA_100D SATA 7 34
SATA_100D SATA SATA_ODD_D2R_UF_P 34 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
SATA_ODD_D2R_UF_N
SATA_100D SATA 34
102 OF 109
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP 20 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI Bus Constraints
NET_TYPE
PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

MCP_DEBUG PCI_55S PCI MCP_DEBUG<7..0> 13 19
CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_AD PCI_55S PCI PCI_AD<23..8>
PCI_AD24 PCI_55S PCI PCI_AD<24>

PCI_AD PCI_55S PCI PCI_AD<31..25>

PCI_AD PCI_55S PCI PCI_PAR
PCI * =STANDARD ? PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0>

PCI_CNTL PCI_55S PCI PCI_IRDY_L

CLK_PCI * 8 MIL ?
PCI_DEVSEL_L
D
PCI_CNTL PCI_55S PCI
D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI_CNTL
PCI_CNTL
PCI_55S
PCI_55S
PCI
PCI
PCI_PERR_L
PCI_SERR_L
PCI_CNTL PCI_55S PCI PCI_STOP_L

LPC Bus Constraints PCI_CNTL PCI_55S PCI PCI_TRDY_L
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CNTL PCI_55S PCI PCI_FRAME_L
ON LAYER?
PCI_REQ0_L PCI_55S PCI PCI_REQ0_L 19

LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
PCI_GNT0_L PCI_55S PCI PCI_GNT0_L
CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_REQ1_L PCI_55S PCI PCI_REQ1_L 19
PCI_GNT1_L PCI_55S PCI PCI_GNT1_L

PCI_INTW_L PCI_55S PCI PCI_INTW_L

PCI_INTX_L PCI_55S PCI PCI_INTX_L
LPC * 6 MIL ? PCI_INTY_L PCI_55S PCI PCI_INTY_L

PCI_INTZ_L PCI_55S PCI PCI_INTZ_L
CLK_LPC * 8 MIL ?
MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP_R 19
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1. CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP 19
LPC_AD LPC_55S LPC LPC_AD<3..0> 19 36 38

USB 2.0 Interface Constraints LPC_FRAME_L
LPC_FRAME_L LPC_55S LPC 19 36 38
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_RESET_L LPC_55S LPC LPC_RESET_L 19 25
ON LAYER?
MCP_USB_RBIAS * =STANDARD 8 MIL 8 MIL =STANDARD =STANDARD =STANDARD MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R 19 25
CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC 25 36

USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS 25 38
USB_EXTA USB_90D USB USB_EXTA_P 20 35

USB_90D USB USB_EXTA_N 20 35
USB * =2x_DIELECTRIC ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_90D USB USB_EXTA_MUXED_P 35
C SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

USB_90D
USB_90D
USB
USB
USB_EXTA_MUXED_N
CONN_USB_EXTA_P
35
35
C
USB_90D USB CONN_USB_EXTA_N 35
SMBus Interface Constraints

ON LAYER?
SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
USB_CAMERA USB_90D USB USB_CAMERA_P 20 65

USB_90D USB USB_CAMERA_N 20 65

USB_90D USB USB_CAMERA_CONN_P 7 65
SMB * =2x_DIELECTRIC ? USB_90D USB USB_CAMERA_CONN_N 7 65
USB_BT USB_90D USB USB_BT_P 20 30
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1. USB_90D USB USB_BT_N 20 30
USB_90D USB CONN_USB2_BT_P 7 30
HD Audio Interface Constraints USB_90D USB CONN_USB2_BT_N 7 30

USB_TPAD USB_90D USB USB_TPAD_P 20 44

ON LAYER? USB_90D USB USB_TPAD_N 20 44
HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB USB_TPAD_R_P 44
USB_90D USB USB_TPAD_R_N 44

USB_IR USB_90D USB USB_IR_P 9 20

USB_90D USB USB_IR_N 9 20
HDA * =2x_DIELECTRIC ? USB_EXTB USB_90D USB USB_EXTB_P 20 35

USB_90D USB USB_EXTB_N 20 35

MCP_HDA_COMP * 8 MIL ?
USB_90D USB CONN_USB_EXTB_P 35
USB_90D USB CONN_USB_EXTB_N 35

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.
USB_SD USB_90D USB USB_CARDREADER_P 9 20
USB_CARDREADER_N 9 20
B SIO Signal Constraints

ALLOW ROUTE
USB_90D USB
B
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_USB_RBIAS MCP_USB_RBIAS MCP_USB_RBIAS_GND 20
SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_CLK 13 21 39

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_0_DATA 13 21 39

SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_CLK 21 39

CLK_SLOW * 8 MIL ?
SMBUS_MCP_1_DATA SMB_55S SMB SMBUS_MCP_1_DATA 21 39
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13. HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK 21 49
HDA_55S HDA HDA_BIT_CLK_R 21
SPI Interface Constraints HDA_SYNC HDA_55S HDA HDA_SYNC 21 49

HDA_55S HDA HDA_SYNC_R 21

ON LAYER? HDA_RST_L HDA_55S HDA HDA_RST_R_L 21
SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_55S HDA HDA_RST_L 21 49
HDA_SDIN0 HDA_55S HDA HDA_SDIN0 21 49

HDA_55S HDA HDA_SDIN_CODEC

HDA_SDOUT HDA_55S HDA HDA_SDOUT 21 49
SPI * 8 MIL ? HDA_55S HDA HDA_SDOUT_R 21
MCP_HDA_PULLDN_COMP MCP_HDA_COMP MCP_HDA_PULLDN_COMP 21

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.
MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R 21 25
CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK 25 36
SPI_CLK SPI_55S SPI SPI_CLK_R 21 38 48
SPI_55S SPI SPI_CLK 48
A SPI_MOSI
SPI_55S
SPI_55S
SPI
SPI
SPI_ALT_CLK
SPI_MOSI_R
38
21 38 48 SYNC_MASTER=K24_MLB SYNC_DATE=04/06/2009 A
SPI_55S SPI SPI_MOSI 48
PAGE TITLE
SPI_55S SPI SPI_ALT_MOSI 38 MCP Constraints 2

SPI_MISO SPI_55S SPI SPI_MISO 21 38 48 DRAWING NUMBER SIZE
SPI_55S SPI SPI_MISO_R 48
SPI_55S SPI SPI_ALT_MISO 38 REVISION
SPI_CS0 SPI_55S SPI SPI_CS0_R_L 21 38
R
C.0.0
SPI_55S SPI SPI_CS0_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
SPI_55S SPI SPI_CS1_R_L THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SPI_55S SPI SPI_CS1_R_L_USE_MLB I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
103 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP RGMII (Ethernet) Constraints
NET_TYPE
MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD

MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_VDD 18
ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_GND 18
MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0_R 18 32

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_MII_55S MCP_BUF0_CLK RTL8211_CLK25M_CKXTAL1 31 32

MCP_BUF0_CLK * =3:1_SPACING ? ENET_INTR_L ENET_MII_55S ENET_MII ENET_INTR_L

ENET_MDIO ENET_MII_55S ENET_MII ENET_MDIO 18 31

ENET_MII * 12 MIL ?
ENET_MDC 18 31
D
ENET_MDC ENET_MII_55S ENET_MII
D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_PWRDWN_L
ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK_R 31
88E1116R (Ethernet PHY) Constraints ENET_RXCLK ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK 18 31

ENET_MII_55S ENET_MII ENET_RXD_R<3..0> 31

ON LAYER? ENET_RXD ENET_MII_55S ENET_MII ENET_RXD<0> 18 31
ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD<3..1> 18 31
ENET_RXD ENET_MII_55S ENET_MII ENET_RX_CTRL 18 31

ENET_MII_55S ENET_MII ENET_RXCTL_R 31

ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK_R 31

ENET_MDI * 25 MIL ?
ENET_TXCLK ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK 18 31
ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD<0> 18 31

ENET_TXD ENET_MII_55S ENET_MII ENET_TXD<3..1> 18 31
ENET_TXD ENET_MII_55S ENET_MII ENET_TX_CTRL 18 31
ENET_MII_55S ENET_MII ENET_RESET_L 18 31
ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P<3..0> 31 33
ENET_MDI_100D ENET_MDI ENET_MDI_N<3..0> 31 33
ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_P<3..0> 33
ENET_MDI_100D ENET_MDI ENET_MDI_TRAN_N<3..0> 33
C C
B B
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER SIZE

REVISION
R
C.0.0
104 OF 109
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SMC SMBus Net Properties
NET_TYPE
1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM

SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 7 39
SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 7 39
SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL 39
SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA 39
SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 39
SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SDA 39
SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SCL 7 39
SMBUS_SMC_BSA_SDA 7 39
D
SMBUS_SMC_BSA_SDA SMB_55S SMB
D SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
SMB_55S
SMB_55S
SMB
SMB
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA
39
39
SMBus Charger Net Properties

NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P
1TO1_DIFFPAIR CHGR_CSI_N
CHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P
1TO1_DIFFPAIR CHGR_CSO_N
C C
B B
PAGE TITLE
SMC Constraints
DRAWING NUMBER SIZE

REVISION
R
C.0.0
106 OF 109
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K84 SENSOR NET PROPERTIES
NET_TYPE
DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM

DIFFPAIR CHGR_CSO_R_P 56
DIFFPAIR CHGR_CSO_R_N 56
DIFFPAIR CPUTHMSNS_D2_P 42
DIFFPAIR CPUTHMSNS_D2_N 42
DIFFPAIR CPU_THERMD_P 10 42
DIFFPAIR CPU_THERMD_N 10 42
DIFFPAIR ISNS_CPUVTT_P 41
ISNS_CPUVTT_N 41
D
DIFFPAIR
D DIFFPAIR
DIFFPAIR
ISNS_HDD_P
ISNS_HDD_N
34 47
34 47
DIFFPAIR ISNS_HDD_R_P 47
DIFFPAIR ISNS_HDD_R_N 47
DIFFPAIR MCPTHMSNS_D2_P 42
DIFFPAIR MCPTHMSNS_D2_N 42
DIFFPAIR MCP_THMDIODE_P 21 42
DIFFPAIR MCP_THMDIODE_N 21 42
DIFFPAIR ISNS_ODD_P 34 47
DIFFPAIR ISNS_ODD_N 34 47
DIFFPAIR ISNS_ODD_R_P 47
DIFFPAIR ISNS_ODD_R_N 47
DIFFPAIR ISNS_AIRPORT_P 30 47
DIFFPAIR ISNS_AIRPORT_N 30 47
DIFFPAIR ISNS_AIRPORT_R_P 47
DIFFPAIR ISNS_AIRPORT_R_N 47
DIFFPAIR ISNS_1V5_S3_P 47 58
DIFFPAIR ISNS_1V5_S3_N 47 58
DIFFPAIR ISNS_1V5_S3_R_P 47
DIFFPAIR ISNS_1V5_S3_R_N 47
DIFFPAIR ISNS_LCDBKLT_P 47 68
DIFFPAIR ISNS_LCDBKLT_N 47 68
C C
B B
PAGE TITLE
K84 SPECIAL CONSTRAINTS

DRAWING NUMBER SIZE

REVISION
R
C.0.0
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K84 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
(MIL or MM) VERSION SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1

DEFAULT * 0.1 MM ? * * BGA_P1MM BGA_P1MM MEM_40S BGA_P1MM STANDARD
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
STANDARD * =DEFAULT ? MEM_CLK * BGA_P1MM BGA_P2MM MEM_40S_VDD BGA_P1MM STANDARD

ON LAYER? TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P1MM * =DEFAULT ? CLK_FSB * BGA_P1MM BGA_P2MM

DEFAULT * Y =50_OHM_SE 0.100MM 30 MM 0 MM 0 MM
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P2MM * =DEFAULT ? CLK_LPC * BGA_P1MM BGA_P2MM
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P3MM * =DEFAULT ? CLK_PCI * BGA_P1MM BGA_P2MM

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM
D PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP

CLK_PCIE * BGA_P1MM BGA_P2MM
D
55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM CLK_SLOW * BGA_P1MM BGA_P2MM
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
1.5:1_SPACING * 0.15 MM ?
55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD FSB_DSTB FSB_DSTB BGA_P1MM BGA_P3MM
2:1_SPACING * 0.2 MM ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 2.5:1_SPACING * 0.25 MM ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
50_OHM_SE TOP,BOTTOM Y 0.115 MM 0.115 MM 3:1_SPACING * 0.3 MM ?

50_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD 4:1_SPACING * 0.4 MM ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
ON LAYER?
40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.100 MM 2X_DIELECTRIC TOP,BOTTOM 0.140 MM ?

40_OHM_SE * Y 0.126 MM 0.100 MM =STANDARD =STANDARD =STANDARD 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ?

4X_DIELECTRIC TOP,BOTTOM 0.280 MM ?

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
ON LAYER? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ?

27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM

2X_DIELECTRIC * 0.126 MM ?
27P4_OHM_SE * Y 0.222 MM 0.222 MM =STANDARD =STANDARD =STANDARD

ON LAYER?
70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

C 70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.151 MM 0.100 MM =STANDARD 0.224 MM 0.224 MM

C
70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.100 MM 0.200 MM 0.200 MM
ON LAYER?

90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.234 MM 0.234 MM

ON LAYER?


ON LAYER?
100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

100_OHM_DIFF_HDD ISL3,ISL4,ISL9,ISL10 Y 0.083 MM 0.083 MM 0.400 MM 0.400 MM

100_OHM_DIFF_HDD TOP,BOTTOM Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM
ON LAYER?
B 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

B
ON LAYER?
1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
PAGE TITLE
K84 RULE DEFINITIONS

DRAWING NUMBER SIZE

REVISION
R
C.0.0
109 OF 109
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K84 MLB Schematic: PROD OK2FAB 11/01/2009

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K84 MLB Schematic: PROD OK2FAB 11/01/2009

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K84 MLB SCHEMATIC

Page Contents Sync Page Contents Sync Page Contents Sync

1 01/19/2009 49 04/02/2009 101 04/06/2009

2 01/19/2009 50 02/04/2009 102 03/30/2009

3 51 02/15/2009 103 04/06/2009

4 01/19/2009 52 01/19/2009 104 04/06/2009

5 01/19/2009 53 04/06/2009 106 04/06/2009

6 01/19/2009 54 01/27/2009 107 01/19/2009

7 02/04/2009 55 02/04/2009 109 01/19/2009

16 MCP Memory Misc K24_MLB 51 AUDIO: HEADPHONE FILTER AUDIO

19 MCP PCI & LPC K24_MLB 54 AUDIO: JACK TRANSLATORS AUDIO

21 MCP HDA & MISC K24_MLB 56 PBUS Supply/Battery Charger K24_MLB

22 MCP Power & Ground K24_MLB 57 5V/3.3V SUPPLY

23 MCP Standard Decoupling K24_MLB 58 1.5V/0.75V DDR3 SUPPLY

24 MCP Graphics Support K24_MLB 59 IMVP6 CPU VCore Regulator K24_MLB

46 02/05/2009 100 04/06/2009

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

SPI FAN CONN AND CONTROL

CONN LVDS OUT CTRL

J3401 J5800 J9000 J4600,4610

RGMII PCI HDA

CIRRUS LOGIC CS4206

Apple Inc. 051-7982 D

MINI PCI-E J6700,J6701,J6702,J6703,J6704

VIN ISL8009B U1000

RC CPUVTTS0_EN 16-1 ISL6263D

BOM NUMBER BOM NAME BOM OPTIONS

085-0748 K84 MLB DEVELOPMENT BOM K84_DEVEL_ENG

639-0554 PCBA,MLB,FOX DDR CONN,PVT K84 K84_COMMON_PVT,CPU_2_0GHZ,FOX_DDR_CONN,EEE_CXR

639-0555 PCBA,MLB,MLX DDR CONN,PVT K84 K84_COMMON_PVT,CPU_2_0GHZ,MLX_DDR_CONN,EEE_CY1

085-1076 K84 MLB DEVELOPMENT PVT K84_DEVEL_PVT

338S0710 1 IC,GMCP,MCP79,35X35MM,BGA1437,B03 U1400 CRITICAL MCP_B03

516S0706 1 CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA J3200 CRITICAL FOX_DDR_CONN

C 516-0201 1 CONN,204P,SODIMM,P=0.6MM J3100 CRITICAL FOX_DDR_CONN

516-0213 1 CONN,204P,SODIMM,P=0.6MM,HF J3100 CRITICAL MLX_DDR_CONN

452-1708 4 SCR.M1.6X0.35X6.0,D4,HO.3,BLK,M97 SCREW1,SCREW2,SCREW3,SCREW4 CRITICAL

514-0704 1 CONN,RCPT,RJ45,PLASTIC,HF,K83/K84 J3900 CRITICAL

353S2718 1 IC,ISL88042,4X V MONTR,2.78/2.86V,TDFN8 U7870 CRITICAL

870-1885 3 POGO PIN,MED,NOISE-IMPROVED,K84 ZS0908,ZS0909,ZS0911 CRITICAL 2 GROUND

870-1886 5 POGO PIN,TALL,NOISE-IMPROVED,K84 ZS0912,ZS0913,ZS0914,ZS0915,ZS0919 CRITICAL

518S0774 1 CONN,RCPT,60P,P=0.4,STK HT 1.0 J1300 CRITICAL XDP_CONN 5 GROUND

DEVELOPMENT BOM 8 GROUND

335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK

337S2983 1 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 U5701 CRITICAL WELLSPRING_BLANK

341S2491 1 IC,WELLSPRING CONTROLLER,K84 U5701 CRITICAL WELLSPRING_PROG

LOCKED BOOTROM APN IS 341S2488

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

157S0058 157S0055 ALL DELTA AS ALTERNATE

DRAWING NUMBER SIZE

Apple Inc. 051-7982 D

152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE

THE POSESSOR AGREES TO THE FOLLOWING: PAGE

05/01/2009: RELEASE 12.9.0 (MAJOR):

Functional Test Points

POWER NETS FUNC_TEST

TRUE PP5VRT_S0 TRUE PP3V3_S3_BT_F 30

I15 TRUE FAN_RT_PWM 43 I301 TRUE