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  • SISTEM DIGIT (DIGITAL SYSTEMS) Milestone 1 - Quartus II Familiarization

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    محمد ابو جراد
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    The document describes the students' work on familiarizing themselves with the Quartus II software by implementing basic digital circuits like the half adder (HA), full adder (FA), 4-bit ripple carry adder (RCA), and 4-to-1 multiplexer (MUX). The circuits were synthesized using Quartus II and implemented on a MAX II FPGA device with logic utilization and timing results reported.

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    The document describes the students' work on familiarizing themselves with the Quartus II software by implementing basic digital circuits like the half adder (HA), full adder (FA), 4-bit ripple carry adder (RCA), and 4-to-1 multiplexer (MUX). The circuits were synthesized using Quartus II and implemented on a MAX II FPGA device with logic utilization and timing results reported.

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    © All Rights Reserved
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    94 views23 pages

    SISTEM DIGIT (DIGITAL SYSTEMS) Milestone 1 - Quartus II Familiarization

    Uploaded by

    محمد ابو جراد
    The document describes the students' work on familiarizing themselves with the Quartus II software by implementing basic digital circuits like the half adder (HA), full adder (FA), 4-bit ripple carry adder (RCA), and 4-to-1 multiplexer (MUX). The circuits were synthesized using Quartus II and implemented on a MAX II FPGA device with logic utilization and timing results reported.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 23

    SEEE2263-14 SISTEM DIGIT (DIGITAL SYSTEMS)

    Milestone 1 − Quartus II Familiarization


    Dr. Amirjan bin Nawabjan

    Students:
    Mohammed A M Abujarad - A19EE4071
    ISMAIEL HAITHAM EISSA - A19EE4055
    SAMI IMAD LABABIDI - A19EE0482
    Date: March 28, 2021 HA.bdf Project: RCA

    AND2
    A INPUT
    VCC OUTPUT C
    B INPUT
    VCC
    inst

    XOR
    OUTPUT S
    inst1

    Page 1 of 1 Revision: RCA


    Flow Status Successful - Sun Mar 28 02:29:58 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name RCA
    Top-level Entity Name HA
    Family MAX II
    Total logic elements 2 / 240 ( < 1 % )
    Total pins 4 / 80 ( 5 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    Date: March 28, 2021 FA.bdf Project: RCA

    HA
    A INPUT
    VCC A C
    B INPUT HA
    VCC B S
    A C
    inst OUTPUT S
    B S
    OR2
    INPUT
    inst1 OUTPUT
    Cin VCC Cout
    inst2

    Page 1 of 1 Revision: RCA


    Flow Status Successful - Sun Mar 28 02:36:19 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name RCA
    Top-level Entity Name FA
    Family MAX II
    Total logic elements 2 / 240 ( < 1 % )
    Total pins 5 / 80 ( 6 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    Date: March 28, 2021 RCA.bdf Project: RCA

    INPUT
    A[0..3]
    A[0..3] VCC
    B[0..3]
    B[0..3] INPUT
    VCC

    Cin INPUT
    VCC

    B3

    B2

    B1

    B0
    A3

    A2

    A1

    A0
    FA

    FA

    FA

    FA
    inst1

    inst2

    inst3
    inst
    Cin

    Cin

    Cin

    Cin
    Cout B

    Cout B

    Cout B

    Cout B
    A

    A
    S

    S
    OUT PUT Cout

    S3

    S2

    S1

    S0
    S[0..3] OUT PUT S[0..3]

    Page 1 of 1 Revision: RCA


    Flow Status Successful - Sun Mar 28 02:42:43 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name RCA
    Top-level Entity Name RCA
    Family MAX II
    Total logic elements 10 / 240 ( 4 % )
    Total pins 14 / 80 ( 18 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    Date: March 28, 2021 MUX.bdf Project: BM

    A INPUT
    VCC AND2
    NOT

    inst3 inst OR2


    OUTPUT Y
    inst2
    B INPUT
    VCC
    AND2
    S INPUT
    VCC

    inst1

    Page 1 of 1 Revision: BM
    Flow Status Successful - Sun Mar 28 02:48:06 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name BM
    Top-level Entity Name MUX
    Family MAX II
    Total logic elements 1 / 240 ( < 1 % )
    Total pins 4 / 80 ( 5 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    Date: March 28, 2021 busmux4bit.bdf Project: BM
    A[3..0]
    A[3..0] INPUT MUX
    VCC Y[3..0]
    A[3] Y[3] OUTPUT Y[3..0]
    B[3] A Y
    B[3..0] B
    B[3..0] INPUT
    VCC S
    inst

    MUX
    A[2] Y[2]
    B[2] A Y
    B
    S
    inst1

    MUX
    A[1] Y[1]
    B[1] A Y
    B
    S
    inst2

    MUX
    A[0] Y[0]
    B[0] A Y
    B
    S
    inst3

    S INPUT
    VCC

    Page 1 of 1 Revision: BM
    Flow Status Successful - Sun Mar 28 02:51:40 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name BM
    Top-level Entity Name busmux4bit
    Family MAX II
    Total logic elements 4 / 240 ( 2 % )
    Total pins 13 / 80 ( 16 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    Date: March 28, 2021 regcell.bdf Project: RD

    MUX DFF
    PRN OUTPUT dout
    A Y D Q
    din INPUT
    VCC B
    Id INPUT
    VCC S CLRN
    inst inst3

    clock INPUT
    VCC

    Page 1 of 1 Revision: RD
    Flow Status Successful - Sun Mar 28 17:20:58 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name RD
    Top-level Entity Name regcell
    Family MAX II
    Total logic elements 1 / 240 ( < 1 % )
    Total pins 4 / 80 ( 5 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    Date: March 28, 2021 reg4bit.bdf Project: RD

    INPUT regcell
    d[3..0] VCC d[3] q[3] OUTPUT
    din dout q[3..0]
    Id
    clock
    inst

    regcell
    d[2] q[2]
    din dout
    Id
    clock
    inst1

    regcell
    d[1] q[1]
    din dout
    Id
    clock
    inst2

    regcell
    d[0] q[0]
    din dout
    load INPUT
    VCC Id
    clock INPUT
    VCC clock
    inst3

    Page 1 of 1 Revision: RD
    Flow Status Successful - Sun Mar 28 17:44:53 2021
    Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version
    Revision Name RD
    Top-level Entity Name reg4bit
    Family MAX II
    Total logic elements 4 / 240 ( 2 % )
    Total pins 10 / 80 ( 13 % )
    Total virtual pins 0
    UFM blocks 0/1(0%)
    Device EPM240T100C3
    Timing Models Final

    1
    References:

    1- Floyd, Thomas L. Digital Fundamentals, Global Edition. Pearson Education Limited, 2014.
    2- SADIAH, SHAHIDATUL. “Quartus Tutorial SEEE1223 [UTM].” YouTube, YouTube, 14 Apr. 2020,
    www.youtube.com/playlist?list=PLbnXeqW-iDllQAFm9qFrXjP5ZLmxP8Q_5.
    3- Zabidi, Muhammad mun'im, and Ismahani Ismail. Design of Digital Systems. 2021.

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