SN Computer Science (2020) 1:133

https://doi.org/10.1007/s42979-020-00128-9

REVIEW ARTICLE

FPGA Implementations of SVM Classifiers: A Review

Shereen Afifi1   · Hamid GholamHosseini1 · Roopak Sinha2

Received: 28 April 2019 / Accepted: 30 March 2020 / Published online: 23 April 2020
© Springer Nature Singapore Pte Ltd 2020

Abstract
Support vector machine (SVM) is a robust machine learning model with high classification accuracy. SVM is widely utilized
for online classification in various real-time embedded applications. However, implementing SVM classification algorithm
for an embedded system is challenging due to intensive and complicated computations required. Several works attempted
to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA)
as it is a promising platform for meeting challenging embedded systems constraints. This article presents a comprehensive
survey of hardware architectures used for implementing SVM on FPGA over the period 2010–2019. We performed a criti-
cal analysis and comparison of existing works with in-depth discussions around limitations, challenges, and research gaps.
We concluded that the primary research gap is overcoming the challenging trade-off between meeting critical embedded
systems constraints and achieving efficient and precise classification. Finally, some future research directions are proposed,
aiming to address such research gaps.

Keywords  SVM · FPGA implementation · FPGA hardware architecture · Embedded system · System on chip

Introduction has shown very high classification accuracy that outperforms

Support vector machine (SVM) is a robust machine learning
model that is widely used in different classification prob-
lems. SVM is recognized by its high classification accu-
racy for several applications such as face recognition, image
classification, object detection, bioinformatics, and cancer
classification [1]. An SVM model is trained using a training
dataset of data samples. Then, this trained model is utilized
for classifying/predicting any new data using defined sup-
port vectors obtained from the training process. SVM has
found use in numerous real-world applications/problems and
* Shereen Afifi
safifi@aut.ac.nz
Hamid GholamHosseini
hgholamh@aut.ac.nz
Roopak Sinha
rsinha@aut.ac.nz
1
Department of Electrical and Electronic Engineering,
Auckland University of Technology, Auckland 1010,
New Zealand
2
Department of IT and Software Engineering, Auckland
University of Technology, Auckland 1010, New Zealand
other known classifiers [2–5].
Several existing software implementations of the SVM
algorithm provide high classification accuracy. However,
these implementations cannot be used in embedded sys-
tems and applications, because of the intensive computations
required by the SVM algorithm. Also, embedded systems
development requires meeting challenging constraints such
as real time, low cost, limited resources and low power con-
sumption. Accordingly, using special-purpose hardware or
reconfigurable computing is required to achieve necessary
high-performance computing with low cost and power con-
sumption [6].
Field-programmable gate arrays (FPGAs) are massive
parallel processing reconfigurable devices. FPGAs have
been widely used for achieving the required performance
of embedded systems, while effectively utilizing hardware
resources and achieving low power consumption. For vari-
ous applications, FPGAs have demonstrated significant
performance and acceleration with efficient hardware
implementation results, outperforming other comparable
platforms such as general-purpose processors and graphics
processing units (GPUs) [7–12]. Subsequently, FPGAs have
been widely used for implementing and accelerating SVM
onto hardware for online and embedded classification.

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This paper reviews existing hardware implementations of
SVM classification algorithm on FPGAs. The primary aim
of this study is to identify the strengths and limitations of
the surveyed works, research gaps, and future directions for
investigation. To the best of our knowledge, this is the first
comprehensive survey of this topic, and it can drive future
hardware implementations of SVM. This study extends our
previous work [13], which reviewed papers related to FPGA
implementations of both training and classification phases
of SVM for the period of 2010 to 2015. However, this study
emphasizes the implementation of classification phase only.
In this study, the methodological framework is around iden-
tifying and classifying different FPGA implementations of
the SVM classification phase. Accordingly, we propose the
following six categories of hardware implementation of SVM
classifiers based on well-established hardware architectures:
A. Parallel pipelined architectures
B. Systolic array architectures
C. Dynamic partially reconfiguration-based architectures
D. Multiplier-less architectures
E. Development tool-based architectures
F. Cascaded classification-based architectures
A total of 44 papers published during 2010–2019 are
reviewed and discussed. In addition, this study presents
an extensive analysis and comprehensive comparison with
in-depth discussions around limitations, challenges, and
research gaps of the surveyed work. Moreover, leading
research groups in the area are identified, and key future
research directions are proposed, which could be considered
by hardware designers for future implementations. Specifi-
cally, we seek to answer the following research questions:
1. How to find optimum hardware architecture for the SVM
classifier to meet embedded systems constraints?
2. How do existing FPGA-based implementations of SVM
compare with respect to efficiency and precision?
3. What is the best trade-off (optimum solution) for achiev-
ing higher classification accuracy while meeting embed-
ded systems constraints?
4. To what extent, can we reach satisfied flexibility and
scalability of a hardware design for big data problems?
5. How to integrate an embedded SVM classifier efficiently
into a complete detection/classification system for real-
world problems/applications?
We find that the primary challenge in this area is the
trade-off between meeting vital embedded systems con-
straints while achieving efficient classification with high
accuracy. The rest of this article is organized as follows. In
the next section, we present basic background information
about SVM. Then, the research methodology used in this
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SN Computer Science (2020) 1:133
study is presented in Sect. 3. Section 4 presents different
architectures for implementing SVM on FPGAs and classi-
fies these into the proposed categories. Section 5 provides
the critical analysis, comparisons, and discussions, followed
by the conclusion and future research directions in Sect. 6.
SVM Background
Support vector machine is a powerful machine learning algo-
rithm, which shows high accuracy in different classification
problems [1]. SVM is based on decision boundary theory,
which efficiently differentiates between two different classes
of data samples. Two main phases exist in such a supervised
learning model, learning/training and classification phases.
In the training phase, a trained model is developed using
an input training dataset, in which a decision boundary is
formed from an optimum separating hyperplane that best
separates data samples of the two classes. Support vectors
(SVs) are data samples that lie on the decision boundary,
which are defined in the training phase and are then used for
the classification task in the classification phase.
In the classification phase, the main classification/deci-
sion function (1) is used to classify new test data x⃗ (dimen-
sional vector), which depends on the number of SVs n. (α, y,
and b are parameters specified in the training phase.)
( n )
∑ ( )
f (x) = sign 𝛼i ⋅ yi ⋅ K x⃗i, x⃗ + b (1)
i=1
The function consists of complicated calculation between
each SV denoted as x⃗i and the test vector x⃗ , which is per-
formed by one of the kernel tricks K. The common used
kernel functions are as follows [14, 15]:
( )
• Linear K x⃗i, x⃗( = x⃗)i ⋅ x⃗ ( )n
• Polynomial( K x⃗)i, x⃗ = x⃗(i ⋅ x⃗ )
• Sigmoid K x⃗i, x⃗ = tanh x⃗i ⋅ x⃗ + 𝜃
• G a u s s i a n ( r a d i a)l b a s i s f u n c t i o n (RBF):
( ) −||x⃗i−⃗x||2
2
K x⃗i, x⃗ = e 2𝜎 ( )
• Hardware-friendly K x⃗i, x⃗ = 2−𝛾 ||x⃗i−⃗x||1
SVM is originally a binary classifier, while the multi-
class classification is based on multibinary SVMs. Different
methods are used to realize multiclass SVM classification as
“one-against-one” and “one-against-all” [16].
Research Methodology
This review began with a comprehensive search involving
thousands of publications within the initial scope of SVM
implementation on FPGA. Five scientific databases were
SN Computer Science (2020) 1:133 Page 3 of 17  133
considered for the searching process: IEEE Xplore, Scopus,
Google Scholar, ACM Digital Library, and ScienceDirect.
The keywords used for the search task were support vec-
tor machine, SVM classifier, SVM classification, FPGA,
embedded system, and hardware implementation. The result-
ing collection of papers was narrowed down to only include
conference and journal publications from 2010 onward. This
cutoff ensures a current view of technology given the signifi-
cant advances in FPGA technology since 2010.
Additional refinement was applied manually based on a
screening of the remaining articles, so that only those works
that focus on FPGA implementation of standalone online SVM
classification were considered. Hardware implementation stud-
ies for the training phase have been explicitly excluded in this
study. We also excluded works that implement large systems
for specific applications and integrate SVM classifier as only
a small part of a whole system, or those that do not provide
separate design and detailed implementation results for SVM.
We also focused on image processing and classification appli-
cations in this study. Finally, a total of 44 papers were studied,
reviewed, and analyzed in this study.
Main FPGA Architectures for SVM Classifiers
Numerous techniques implement the SVM classifica-
tion stage in hardware on FPGAs. In order to implement
the classification stage on hardware, SVM is first trained
offline in software, and then a trained model is extracted
for the FPGA implementation of the classifier. MATLAB
was the mostly used platform for the SVM training stage.
The 44 works reviewed and discussed in this section pre-
sent different hardware architectures and implementation
techniques. We have classified implemented architectures
into six main categories, where some works apply multiple
architectures and are therefore categorized into multiple
categories.
Parallel Pipelined Architectures
The pipelining technique breaks a process into smaller
stages, which allows for the concurrent execution of jobs.
Pipelining can significantly boost the whole process and
increases data throughput. Many implementations use the
pipelined technique by exploiting the parallel processing
capabilities of FPGAs, aiming to achieve efficient parallel
pipelined architectures.
A fully pipelined architecture is proposed for implement-
ing and accelerating the SVM classification, while present-
ing three different configurations to implement RBF, poly-
nomial, and sigmoid kernel functions [17]. A new processor
is designed in a fully pipelined architecture by effectively
exploiting embedded DSP slices and block RAMs of the
FPGA. The proposed architecture uses 768 DSPs and 800
BRAMs for implementing an SVM classifier, including
760 SVs. A high throughput of 2.89 × 106 times per sec-
ond is achieved at 370.096 MHz, for classifying 128 feature
dimensions.
Another fully pipelined structure is proposed in [11, 18],
emphasizing a comparison between FPGA and GPU imple-
mentations. Regarding the FPGA implementation, compli-
cated hardware modules are designed in a fully pipelined
architecture using traditional hardware description language
(HDL), whereas other basic modules, finite-state machines
(FSMs), FIFO, and interfaces are implemented using the
high-level language (HLL) (Impulse C). For few image pix-
els, the FPGA implementation is faster than the GPU and
CPU implementations [11]. However, for larger number of
pixels, the GPU implementation is the fastest, but it dissi-
pates very high power, which makes it infeasible for embed-
ded applications.
A pipelined architecture is proposed to realize a multi-
purpose SVM with high flexibility in terms of input data
and kernel type in [19]. A pipelined design is presented for
a complete SVM core that allows dynamic selection of lin-
ear, polynomial, or RBF kernel at run-time. The dot-product
operation is computed with parallel embedded DSP-based
MAC units and a LUT-based adder tree. The Xilinx Coor-
dinate Rotation Digital Computer (CORDIC) [20] IP core
is used to implement the exponential function. Also, two
different number formats are used in the core, a fixed-point
number format for the dot-product calculation, and a single
precision floating point format for other computations. This
flexible SVM core is simulated and verified at 50 MHz for
the RBF kernel. (A maximum frequency of 92 MHz might
be achieved.)
An FPGA pipelined design is introduced in [21], where a
simplified algorithm based on posterior probability is imple-
mented. The proposed pipelined structure exploits a LUT
method for computing the sigmoid function, while for other
computations, adders, multipliers, and dividers are utilized.
A mean absolute error of 1­ 0–4 order of magnitude is achieved
from the FPGA implementation of the proposed simplified
algorithm (fixed-point) compared to the original C algorithm
(floating-point), showing little loss in the recognition rate. In
addition, the computation complexity is reduced and 0.7 ms
time delay is achieved, which is promising for meeting real-
time constraints for the targeted application.
A hardware architecture exploiting inherent FPGA
parallelism and pipelining features is proposed in [22]. A
block diagram is drawn for the proposed hardware archi-
tecture using the standard single precision floating-point
format. This architecture is based on using counters for
address generation to different stored data in BRAMs for
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performing required calculations. A maximum clock fre-
quency of 200 MHz is achieved with promising hardware
results based on synthesis results, while 97.87% accuracy is
obtained based on simulation results.
A pipelined architecture is presented in [23], aiming to
reach a universal coarse-grained reconfigurable architec-
ture that implements one of three types of machine learn-
ing tools including SVM. The proposed pipelined structure
is designed as a 1D or 2D array of simple reconfigurable
blocks in order to implement one of the three classifiers.
For the SVM implementation, the classification process is
divided into partial sums controlled by an FSM model based
on reconfigurable blocks utilizing adders and multipliers
(and a subtractor in case of a radial kernel). The proposed
implementation gained an acceleration of 1–2 orders of mag-
nitude, compared to a software implementation (R project-
based), while achieving acceptable utilization of hardware
resources. (Additional classification speedup experiments/
comparisons are provided in [24]).
A parallel architecture with two-stage pipeline is pre-
sented in [25]. It uses resource sharing for realizing a unified
circuit for both linear and nonlinear SVM classification. The
proposed architecture includes shared adders and multipliers
for inner product computations required by linear and non-
linear SVM. The table-driven algorithm proposed in [26] is
exploited for computing the RBF kernel, aiming to boost the
exponential function calculation (fixed-point) and increase
accuracy. The synthesized circuit utilizes 661,261 gates at
a maximum frequency of 152 MHz and achieves a speed of
33.8 fps.
Another two-pipelined-stage architecture implements a
three-class SVM identification system [27, 28]. The first
pipelined stage computes the inner product, while the second
stage calculates the summation. The proposed architecture is
implemented using fixed-point number format and is evalu-
ated for different bit lengths, demonstrating the trade-off
between the identification accuracy and hardware area. A
customized architecture is also presented that is based on
their previous implementation in [29], which combines two-
class classifiers. As a result, an increase in the processing
speed of 18% for the inner-product computations is achieved
from the overlap of input data. Finally, an improved two-
pipelined-stage architecture is introduced to avoid the dupli-
cation in the inner-product process, where common inner
products are calculated at the first stage (similar to the above
architecture described [25]). The implementation results
show a system throughput > 21.2 fps at 100 MHz [27], with
sufficient identification accuracy > 90% and good hardware
size.
A pipelined adder is proposed to execute the accumu-
lation operation replacing traditional adders in the main
processing element, targeting acceleration of the SVM
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classification process [30]. The proposed pipelined adder-
based processing element outperforms RCA and KS adders
by 1.44 and 1.21, respectively, while utilizing few extra
resources. This implementation is realized on an ASIC; how-
ever, 3.5 × GMACs are achieved compared to other FPGA
implementations.
A pipelined digital architecture is proposed in [31], where
two SVMs are working in parallel for three-class classifica-
tion using fixed-point arithmetic. The proposed implementa-
tion is based on using subtraction, multiplication, and addi-
tion operations with comparison blocks. Pipelining with the
time multiplexing technique is exploited to decrease hard-
ware resources utilization and processing clock cycles. The
implemented system shows high accuracy rates (> 81%) with
low resources utilization, while processing a hyperspectral
cube in 25 ms at 100 MHz with low dynamic power con-
sumption of 67 mW.
A parallel hardware architecture is presented in [32],
which uses feature extraction algorithms with SVM for real-
time image classification. The implemented SVM uses mul-
tipliers and accumulators for parallel kernel processing using
fixed-point numbers, while a Xilinx CORDIC IP is utilized
for performing the exponential function. The proposed hard-
ware system achieves 75% and 85% classification accuracy
for two challenging datasets used, with 3% loss in accuracy
compared to the software implementation. Also, a speedup
of 5.7 × is achieved compared to the software implementa-
tion, while moderate hardware resources are utilized with
0.25 ms processing time for an image.
Table 1 summarizes the architectures presented in cat-
egory A.
Systolic Array Architectures
The systolic array architecture is a configurable modular
platform that combines both parallelism and pipelining
techniques for enhancing computing speed. The systolic
architecture is designed as an array of simple processors
or processing elements (PEs), which provides efficient data
flow and memory management. A 2D systolic array architec-
ture is depicted in Fig. 1 [33], which demonstrates a prom-
ising platform for achieving scalable designs and decreas-
ing hardware complexity. Parallel FPGA is widely used for
implementing the systolic array architecture for numerous
applications, especially matrix multiplication-based applica-
tions. Several SVM implementations exist in the literature
that exploit the FPGA-based systolic array architecture for
gaining accelerated parallel processing.
A parallel architecture proposed in [34] is based on a
systolic array of PEs [14] (an initial implementation work),
aiming to reach a scalable, flexible and adaptive array pro-
cessing system. The proposed systolic architecture consists
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Table 1  Category A: parallel pipelined architectures

SVM References Kernel App FPGA Tool

Binary [17] RBF Polynomial Sigmoid – Xilinx Virtex-6 (6VLX240T-FF1156) Xilinx ISE 14.1
[11, 18] Gaussian Skin classification Xilinx Virtex-5 (LX220) Xilinx Spar-
tan 6(XC6SLX75)
[19] Linear RBFPolynomial Pedestrian detection Xilinx ML505 (XC5VLX110T) –
[23] RBF Polynomial 18 UCI datasets Xilinx Virtex-7 Vivado 2014.2
[25] RBF – – –
[30] Linear MNIST dataset ASIC Synopsys
Multiclass [21] Linear Sigmoid Language Recognition Xilinx Virtex-5 ISE 10.1
[22] Linear Facial expression classification Xilinx ML510 (Virtex-5 FXT) ModelSim
10.1C, Xilinx
ISE 14.2
[27, 28] Linear Colorectal cancer detection Altera Stratix-IV (EP4SE360F35C2) –
[31] Linear Bruised apple detection Xilinx Zynq Z-7010 –
[32] RBF Image classification Xilinx ML509 (Virtex-5 LX110T) Xilinx ISE
Caltech-256, Belgium Traffic
Sign datasets

an additional hardware technique, the partial reconfigura-

tion technology (to be presented in the following category).
Table 2 summarizes the architectures presented in cat-
egory B.

DPR‑Based Architectures

Dynamic partially reconfiguration (DPR) technology allows

Fig. 1  Systolic array architecture
of three main sections, memory control, vector processing
and scalar processing. The implemented array architecture
is evaluated for three types of object detection applications.
High performance of 40, 46, 122 fps is achieved for the three
tested applications. Interestingly, compared to the software
implementation results, no loss is achieved in the detection
accuracy from the hardware implementation of the three
applications (76, 77, 78%).
In addition, different implementations of systolic array
architecture of PEs that is responsible for the complicated
matrix multiplication required for the kernel computation
are presented in [35–38]. Besides gaining advantages from
using the systolic architecture, these implementations use
reconfiguring dynamically selected areas on FPGA on-the-
fly, while other parts are still working, also called run-time
reconfiguration (RTR) [39]. Not all FPGAs support the par-
tial reconfiguration technology. DPR offers design flexibility,
design space expansion, power and area savings with speed-
ups. However, for performance-critical cases, the reconfigu-
ration speed that is responsible for switching between dif-
ferent cores/modules should be taken into consideration as
a significant factor. Two styles of PR exist: module-based
and difference-based. The module-based PR is widely used
for various designs and applications, where reconfigurable
modules (RMs) are reconfigured at run-time as depicted in
Fig. 2. The difference-based PR is efficient for small designs
and not recommended for big design changes, where a par-
tial reconfiguration bitstream is provided to program the dif-
ference only between the two modules/designs instead of the
full configuration bitstream of each module.
DPR is used to implement an SVM classifier in [35], in
addition to using the systolic array architecture (category B)

Table 2  Category B: systolic SVM References Kernel App FPGA Tool

array architectures
Binary [34] RBF Polynomial Object detection Xilinx ML505 (Virtex 5-LX110T) –

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Fig. 2  DRR architecture
that is designed in four blocks. The kernel calculation is imple-
mented in three sub-blocks designed in two pipelined stages
(category A). Compared to an equivalent GPP implementa-
tion, an acceleration of up to 85 × is achieved. Additionally, by
applying the DPR for changing SVM parameters, a speedup
of 8 × is realized compared to the full chip reconfiguration.
This work is extended lately in [36], where two systolic
array-based architectures are proposed to handle various
dataset sizes. (The number of SVs is higher than the dimen-
sion and vice versa.) The two architectures gain speedups
of ~ 61 × and ~ 49x, respectively, compared to equivalent
GPP implementations. Furthermore, two DPR implementa-
tions are presented as a single-core (same as in [35]) and
multicore SVM architecture (quad-core), where different
copies of SVM cores with various parameters are swapped.
The same speedup of 8 × is achieved by using the DPR as
mentioned above [35].
Later, Hussain et al. [37] extended their work by present-
ing a DPR implementation of an adaptive multiclassifier
architecture that provides dynamically interchanging differ-
ent copies of the SVM and K-nearest neighbor (KNN) classi-
fiers with various parameters (based on their previous SVM
and KNN implementations [35, 36, 40, 41]). The proposed
architecture allows users to configure specific region on the
FPGA to work as either SVM or KNN classifier, which could
be extended in future to perform as an ensemble classifier.
The multiclassifier DPR implementation shows a speedup of
8 × in reconfiguration time compared to the single classifier
implementation (same value for previous implementations
[35, 36]) and achieves twice as less area on FPGA as having
both classifiers onto the same chip.
Besides using the systolic array architecture (category
B), the difference-based partial reconfiguration technique
is exploited in [38], targeting low area and power consump-
tion. A power-aware SVM classifier prototype is realized by
using the PR, as a power drop of 3 to 5% is achieved (total
power = 2.021 W).
Table 3 summarizes the architectures presented in cat-
egory C.
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SN Computer Science (2020) 1:133
Multiplier‑less Architectures
The multiplier-less approach aims to reduce hardware
complexity by avoiding the usage of the computationally
intensive multipliers. Different architectures based on the
multiplier-less technique are implemented in the literature.
Many such implementations adopt the hardware-friendly
kernel function proposed in [15], which is based on a sim-
ple multiplier-free design and offers acceptable classification
performance compared to the traditional Gaussian kernel.
An embedded hardware SVM implementation is proposed
in [42], which exploits the proposed hardware-friendly ker-
nel. A simple design of six blocks diagram is proposed that
consists of sum of absolute differences (SAD) [43] and shifts
operations instead of the resource-consuming multiplica-
tions. As a result, low resource utilization of 167 slices is
demonstrated.
Another hardware-friendly kernel-based architecture is
presented in [44]. A SAD-based tree structure is used for the
1-norm computation between vectors, targeting clock cycles
reduction and processing speed improvement. A preliminary
simulation study is presented for the bit precision of fixed-
point arithmetic regarding the classification accuracy level.
An additional implementation that adopts the hardware-
friendly kernel is introduced in [45] for a simple hardware
design. The proposed architecture utilizes the CORDIC
iterative algorithm [20], which is based on exploiting shift
and add operations that replace complex multipliers. The
implemented SVM classification system utilizes an external
memory for storing support vectors with 2 ms speed limita-
tion. From the hardware simulation, the implemented system
demonstrates a 4% error rate, while consuming 75% of the
device logic. These results suggest that there is still some
room for further research and improvement.
An FPGA implementation for a fast SVM is presented
in [46] following the CORDIC-like algorithm implemen-
tation of the proposed hardware-friendly kernel [15]. The
proposed architecture is designed in three sub-circuits for
the kernel calculations. An iterative algorithm is proposed
for simplifying the CORDIC method by using adders and
shifters only. The implemented system is faster than their
previous CORDIC circuit implementation in [47] by a factor
of 6, while very few hardware resources are utilized.
An FPGA core generator tool for embedded SVM is pro-
posed in [48], which automatically generates an optimized
hardware description for a digital implementation, meeting
user requirements and the target device constraints. The pro-
posed hardware-friendly kernel [15] is also adopted in addi-
tion to the proposal in [49], in which the bottleneck 1-norm
(Manhattan norm) calculation is implemented by exploit-
ing the parallel tree structure of the common SAD modules
[43]. For the kernel implementation, three architectures
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Table 3  Category C: DPR- SVM References
based architectures
Binary [35–37]
Multiclass [38]
are proposed. The first architecture uses multiple cas-
cade pipelined stages of multiply-and-accumulate (MAC)
blocks (category A), in order to implement the polynomial
approximation method. The second architecture employs
the CORDIC-like iterative algorithm with multipliers-free
implementation as in [15]. The third architecture uses the
look-up tables (LUTs) or memory blocks for storing kernel
data. The tool is tested for the trade-off between latency,
hardware resources and maximum clock frequency for
implementing the three architectures on low-cost, interme-
diate-class and high-end FPGAs. The second CORDIC-like
and third LUT-based architectures demonstrate higher clas-
sification figures.
A hardware architecture is presented in [50], which
employs the multiplier-less kernel that is similar to the
previous hardware-friendly kernel [15] and appears as the
common radial kernel. The proposed architecture utilizes
simple shifters for implementing the multiplications, while
the CORDIC algorithm is used for implementing the com-
plicated exponential function. The proposed kernel achieves
a comparable classification performance with the original
radial kernel. (No FPGA implementation is presented.)
A multiplier-less kernel implementation for boosting
SVM is presented in [51], which is based on the parallel
pipelined systolic array architecture (category B). Similarly,
simple shift and add operations implement a simplified mul-
tiplier-less kernel for decreasing the hardware complexity
and power consumption. In addition, a different approach
is introduced by applying the CSD (canonic signed digit)
and CSE (common sub-expression elimination) representa-
tion methods for reducing the number of required adders,
which decreases the hardware complexity [52]. A compara-
tive study is presented for the resources utilization of three
different implemented classifiers (binary linear, binary non-
linear, and multiclass), which employ the proposed CSD-
based multiplier-less kernel against the normal vector prod-
uct kernel [51]. Moreover, the three implemented classifiers
achieve power reductions of 1, 2.7, and 3.5% from using the
traditional vector product kernel.
Table 4 summarizes the architectures presented in cat-
egory D.
Kernel App FPGA Tool
Linear Classifying Xilinx ML Xilinx ISE,
microarray/ 403(XC4VSX12) PlanAhead,
biomedical ChipScope
data 12.2
Polynomial Facial expres- Xilinx Virtex-6 (6vlx- Xilinx ISE,
sion recogni- 240tff1156-2) Power
tion analyzer
EDA
Development Tool‑based Architectures
Most existing FPGA implementations in literature are
designed using the traditional HDL approach. However,
very few implementations in the literature exploit the latest
software design tools on the market, which mostly are very
powerful and simplify the complicated hardware design pro-
cess as well as decreasing the development time. In this sec-
tion, the software tools used for the SVM implementations
on FPGA are introduced as well as the proposed designs.
Xilinx System Generator is a common tool, which allows
high-performance system modeling and automatic code
generation from MATLAB/Simulink [53]. The System
Generator is used in [54] to design and implement a simple
hardware architecture. A parallel hardware architecture is
designed using a combination of serial and parallel designs
of simple design blocks and functions of the System Genera-
tor. Additionally, the available CORDIC block of the tool
is instantiated for implementing the complicated exponen-
tial function. Fixed-point numbers are used for quantiza-
tion. The simulation results report maximum frequency of
202.840 MHz for linear classification and 1.33% error rate
for nonlinear classification (98.67% accuracy). Also com-
pared to MATLAB implementation, less computation time
is achieved for both implemented classifiers.
In addition, the Xilinx System Generator is used in [55],
where a DSP slice-based processor is designed in paral-
lel (category A). The proposed hardware design is divided
into three main blocks, kernel implementation, inner-prod-
uct accumulation, and threshold comparison. The design
employs Xilinx DSP slices, block RAMs, multipliers, and
exponential blocks. The simulation results demonstrate the
same accuracy of 93.6% as the software implementation
with less processing time of 0.02 ms and reasonable hard-
ware resources utilization.
The System Generator is also used in [56], where a mix of
parallel and series techniques are used to design a hardware
architecture of linear SVM for three-class facial expression
classification (category A). An architecture is designed for
class 1 using System Generator blocks and is replicated for
the other two classes to be integrated with an output logic,
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Table 4  Category D: multiplier-less architectures

SVM References Kernel App FPGA Tool

Binary [42] Hardware-friendly Satellite onboard/ NASA data- Xilinx Virtex-5 Spartan-3E ModelSim
base
[44] Hardware-friendly UCI standard dataset breast Altera Cyclone III ModelSim
cancer
[46] Hardware-friendly – – –
[48] Hardware-friendly Automotive app/pedestrian Xilinx Spartan-IIE Spartan-3 –
detection Daimler-Chrysler Virtex-II Pro Virtex-4
dataset
[50] Digital kernel 4 UCI datasets – –
Multiclass [45] Hardware-friendly Image recognition COIL dataset Cyclone II (EP2C20) –
Binary and Multiclass [51] Linear polynomial Fisher’s iris dataset Xilinx Virtex-7 Xilinx XPE 14.1
(7vx485tffg1157-2)

forming the full architecture for three-class classification on
FPGA. Synthesis results show low resource utilization with
high accuracy of 97.87% at 132.7 MHz frequency.
The Synopsys Signal Processing Workbench (SPW) soft-
ware is used in [57] to design a digital hardware implemen-
tation using available building blocks. A fixed-point num-
ber representation is used and a decision logic is utilized to
implement a priority scheme required for multiclassification,
targeting accuracy enhancement. The SPW generated cor-
responding VHDL code is analyzed using the Xilinx Simula-
tor. Compared to the software implementation, the hardware
implementation achieves approximately 2.53 times speedup,
while 16.2% accuracy loss is realized.
Also the Synopsys software is used in [30] (category A)
to realize an ASIC implementation as discussed earlier.
The High-level Synthesis (HLS) design methodology
has been recently used to decrease the FPGA development
time and effort by using HLLs instead of HDLs. The Xilinx
Vivado HLS tool [58] is exploited to implement a low-cost
SVM IP [59–64] on a recent FPGA platform “Zynq SoC”
with a hybrid architecture combining a processor with the
FPGA in a single device [65]. An initial hardware/software
co-design is implemented in [59] as an SVM accelerator
to run the complicated processing task onto FPGA. It is
considered the first hardware/software system implemented
for SVM on FPGA/single device that exists in the current
period. The proposed HLS design is successfully extended
in [60, 61, 64] to implement an IP running full SVM algo-
rithm onto FPGA part of the Zynq SoC. By using the avail-
able directives of the HLS tool, some hardware optimiza-
tion techniques are simply applied to the proposed design
as the pipelining (category A) and loop unrolling, which
accelerates the original design/code by 37 ×. The experi-
mental results demonstrate high performance, low area and
low power consumption, meeting embedded systems con-
straints, while preserving classification accuracy rate with-
out any loss. In addition, the implemented embedded SVM
classification system on the recent hybrid Zynq SoC using
the modern UltraFast HLS design methodology is a low-
power system compared to other existing implementations
in the literature (the latest publication [64] reported the least
total power consumption of 1.5 watts).
Another similar design has been recently proposed in
[62], which is based on using BRAM interfaces for pass-
ing required data instead of streaming data using the stream
interface/bus with the DMA IP in [60]. Some extra resources
are utilized compared to [60] and the power is slightly
increased (2.7 W); however, both area and power demon-
strate lesser values compared to some related implementa-
tions in the literature. Moreover, a high acceleration factor of
32 × is achieved compared to a similar software implementa-
tion, while a 97.9% accuracy is achieved with a processing
time of 11.46 µs at 250 MHz.
Another HLS-based implementation with a hardware/
software co-design is recently presented in [66], focusing
on design space exploration. A systematic two-level meth-
odology and prototype framework is proposed for realizing
an efficient HLS-based SVM IP. The proposed method opti-
mizes first the original code structure exploiting data- and
instruction-level parallelism (category A). Then, a second
level optimization applies a derived set of design space
pruning guidelines for refining the applied HLS directives.
The proposed methodology is evaluated based on extensive
analysis and validation results with a case study of ECG-
based arrhythmia detection system. Experimental results
show execution latency gains of up to 98.78% compared to
the default Vivado-HLS optimization of the original SVM
code. A hardware/software co-design including the proposed
IP is implemented on Zynq SoC for the detection system that
achieves speedups of up to 78 × at 25 MHz from an equiva-
lent software implementation.
Also, HLS techniques are used for examining the design
space exploration to optimize a proposed approximate SVM
FPGA accelerator [67]. Two algorithmic approximation

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techniques of precision scaling and loop perforation are

applied for implementing an approximate HLS-based SVM
classifier, aiming to decrease the computational latency.
For the design space exploration, some HLS optimization
techniques/directives have been examined, the loop pipeline
and unrolling with array partition and reshape (category A).
The proposed approximate HLS-SVM classifier achieves an
acceleration of 15 × with a detection accuracy of 96.7% for
detecting arrhythmia based on ECG signal.
The HLS tool is exploited to efficiently implement a pro-
posed pipeline design for an energy-efficient embedded bina-
rized SVM architecture with binarized inputs and weights
[68] (category A). The proposed binarized SVM replaces
the kernel dot-product float multiplication with bit XNOR
(category D), while using the Hamming weights for comput-
ing the binarized vectors for improving the speed and power
consumption. The proposed embedded binarized SVM is
evaluated using MNIST and CIFAR-10 datasets showing
lower power consumption and execution time compared
to CPU and GPU implementations with a slightly loss of
accuracy.
Table 5 summarizes the architectures presented in cat-
egory E.
Cascaded Classification‑Based Architectures
The cascaded classification architecture consists of multi-
classification stages (classifiers) designed in a cascading
structure, targeting accelerated classification process. The
cascaded scheme is depicted in Fig. 3 [69], where the major-
ity of data are rejected at the early stages that are based on
simple classifiers with low complexity, leaving very little
data to be classified in later stages that are more complex
Fig. 3  Cascaded classifier scheme [69]
with higher accuracy. Consequently, a significant speedup
could be achieved by using the cascaded classification archi-
tecture over using a single SVM classifier. This motivates
implementing the cascaded architecture in hardware/FPGA
to realize a real-time embedded classification system with
high performance and low cost.
The first FPGA-based cascaded SVM classifier that
exploits the custom-arithmetic feature of the device hetero-
geneous nature is presented in [70] (following their previous
proposal [71] for accelerating the training phase). A parallel
structure of multipliers with a pipelined adder tree is pro-
posed for implementing the kernel computations (category
A). The proposed data path is divided into two domains:
fixed-point and single floating-point precision. The proposed
heterogeneous architecture efficiently exploits the parallel
processing power of the device heterogeneous resources and
dynamic range diversities among the classification problem’s
features. Additionally, a two cascaded classifier scheme is
implemented that combines a simple faster low-precision
classifier with a complicated high-precision classifier of
higher area cost. Compared to the software implementation,

Table 5  Category E: development tool-based architectures

SVM References Kernel App FPGA Tool

Binary [55] RBF Ultrasonic flaw detection Xilinx Zynq-7000 Xilinx system generator
[59–64] Linear Melanoma detection Xilinx Zynq-7 Xilinx Vivado 2016.1 design
ZC702(XC7Z020CLG484-1) suite, Vivado-HLS
[66] RBF ECG-based arrhythmia detec- Zedboard Zynq (xc7z- Xilinx Vivado-HLS 2015.2,
tion 020clg484-1) Xilinx SDK 2014.4, PetaLinux
2014.4
[67] RBF ECG-based arrhythmia detec- Zynq-7 ZC706 Xilinx Vivado-HLS 2018.2
tion
Multiclass [54] Linear Gaussian Persian handwritten digits Xilinx Virtex-4 (XC4VSX35) System Generator
dataset
[56] Linear Female facial expression clas- Xilinx Virtex-5 System Generator
sification, JAFFE database
[57] RBF Multispeaker phoneme recogni- Xilinx Virtex-II (XC2V3000) Synopsys SPW, Xilinx Simulator
tion, TIMIT corpus
[68] Linear MNIST and CIFAR-10 datasets Xilinx ML605 board (Virtex-6 Xilinx ISE Design Suite, Xpower
LX240T) analyzer

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Table 6  Category F: cascaded classification architectures
SVM References Kernel App
Binary [70, 72] Gaussian polynomial sigmoid MNIST dataset
[69, 73] Linear polynomial Face detection
[74] Linear polynomial Face and pedestrian detection
[75] Linear polynomial Face detection
[62, 63] Linear Melanoma detection
the implemented fully scalable heterogeneous architecture
demonstrates an acceleration of 2–3 orders of magnitude
in addition to a speed-up of 7 × compared to other previous
implementations on FPGAs and GPUs.
As an extension to the previous work architecture [70],
the FPGA reconfigurability feature is applied in [72] (cat-
egory C), in order to switch from the low- to high-precision
classifier in the cascade. Accordingly, higher performance
is achieved, in addition to expanding the potential design
space.
Another cascaded architecture is proposed in [69,
73],where a hardware reduction method is proposed to
decrease area and power dissipation. This method follows
the multiplier-less approach (category D) to implement the
early simple cascade stages, where all multiplication opera-
tions are replaced with shift operations by rounding off the
data to the nearest power of two values. A hybrid cascaded
architecture (4 cascade classifier) is designed to combine
both parallel and sequential processing (as a series of pipe-
lined PEs (category A)) for simple early stages (three clas-
sifiers) and higher complexity SVM (one classifier) respec-
tively. The implemented cascaded architecture demonstrates
an average performance of 70 fps, while an acceleration of
5 × is achieved compared to an implemented single parallel
SVM classifier. By using the proposed hardware reduction
method, resource utilization reduces by 43% and 20% less
power is consumed, while experiencing only a 0.7% loss in
classification accuracy (84%).
Next, the previous work [69] is extended in [74, 75],
where a feature extraction mechanism (local binary pattern
descriptors) is utilized within the proposed architecture to
apply feature extraction before the final stage, aiming to
enhance the detection accuracy. In [75], an additional novel
response evaluation method is incorporated into the pre-
viously proposed architecture. Another type of classifiers
(Neural Network) is used in the proposed response evalua-
tion process to classify the responses of the early stages in
the cascade. Accordingly, the number of tested samples is
reduced before reaching the final high-complex classifica-
tion stage, resulting in improving the classification speed.
The proposed hybrid architecture with the proposed methods
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SN Computer Science (2020) 1:133
FPGA Tool
Altera’s Stratix III (EP3SE260) Altera tools
Xilinx ML505 (Virtex-5-LX110T) –
Xilinx Spartan-6 XC6SLX150T –
Xilinx Spartan-6 XC6SLX150T –
Xilinx Zynq-7 Xilinx Vivado
ZC702(XC7Z020CLG484-1) 2016.1
Design Suite
added demonstrates real-time processing of 40 fps with 80%
detection accuracy [75] (similar behavior for the accuracy
loss as in [69]). Also, a reduction of 25% in area and 20% in
power is achieved. Compared to their previous work [69],
lower values are realized for performance and accuracy with
higher area and power; however, a big test set of higher reso-
lution images is evaluated, aiming to reach real-time embed-
ded processing of online video classification.
Lately, a cascade SVM classifier has been introduced in
[62] based on a proposed scalable multicore architecture,
which is formed from the implemented HLS-based SVM
IPs (category A and E). A two-stage cascade SVM classifier
is implemented using a simplified design of the previously
proposed SVM IP [62] (as described in category E section)
using the control bus for passing required data replacing the
BRAM interface. As a result of the simplified design, lower
resources utilization and power consumption are demon-
strated compared to a single SVM IP implementation, while
enhancing the classification accuracy and speed (1.8 µs) as
well as the diagnosis verification. Next, the hardware imple-
mentation results were optimized by using the powerful DPR
technology (category C), where very low resource utiliza-
tion of 1% slices and power consumption of 1.55 watts were
achieved, while gaining flexibility, adaptability, scalability,
and applicability [63]. The implemented SVM classification
systems on Zynq SoC using the proposed hardware designs
have shown the least power consumption results among
other related implementations, in addition to significantly
low hardware resource utilization and processing time with
significant speedups and high classification accuracy rates
at low cost.
Table 6 summarizes the architectures presented in cat-
egory F.
Critical Analysis and Discussion
Preliminary Analysis
Most existing implementations target binary SVM classifica-
tion (31 works), while only 12 works implement multiclass
SN Computer Science (2020) 1:133 Page 11 of 17  133
classification and only one implements both [51]. This is
probably because implementing a multiclass classifier is
based on combining binary classifiers, and so numerous
works focus on implementing the basic binary classifier to
be then extended if required. Also, various classification
or detection applications have been targeted by the exist-
ing architectures/implementations, especially for different
object detection. Some SVM implementations are tested
using some available or specific datasets, while other imple-
mentations are general without validation for a particular
application/dataset.
Implementing kernels with the inherent complicated cal-
culations is the main challenge and focus for implementing
SVM on FPGA. Some researchers use and implement more
than one type of kernels in their study. A total of 23 studies
implement the simple linear kernel, while others go for dif-
ferent nonlinear kernels that include the basic dot-product
calculation exists in the linear kernel, but with additional
complexity (12 polynomial kernel and 4 sigmoid kernel
existing implementations). Moreover, 15 papers implement
the Gaussian RBF kernel, which basically implements the
complex exponential function. The proposed simplified
hardware-friendly kernel is widely used as an alternative
to the RBF for simple FPGA/hardware implementation (5
papers). Another digital kernel is proposed that is similar
to the hardware-friendly kernel, but no FPGA or hardware
implementation exists using that proposed kernel [50].
Most existing implementations are realized on old ver-
sions of FPGA technology using traditional design meth-
ods, even while using modern development tools. Only four
researchers utilize the recent Xilinx series-7 devices [23,
31, 51, 55]. One unique research work is discriminated by
exploiting the hybrid architecture of the recent Zynq-7 SoC
platform and using the latest UltraFast HLS design method-
ology [59–64] followed by a recent study for design space
exploration based on SVM implementation in [66, 67].
Beside the standard FPGA parallel design, researchers
used various hardware technique(s) for improving their SVM
implementations, which is classified into six categories in
this study. The standard parallel pipelined architecture (cat-
egory A) are widely implemented by 30 papers. The mul-
tiplier-less approach (category D) is commonly applied in
11 implementations, which occupies high interest targeting
multiplier-free architecture with hardware complexity reduc-
tion. Also, the parallel pipelined systolic array architecture
(category B) is implemented in 6 papers with consider-
able interest for reducing multiplication complexity. Only
6 implementations exploit the massive FPGA-based DPR
feature (category C) for enhancing designs and hardware
results. Moreover, only 14 existing implementations are
developed by utilizing software system-design/development
tools (category E), replacing the traditional design method
using the HDL for decreasing FPGA development effort
and time. The cascaded SVM classification (category F) is
implemented on FPGA by only one research group [69, 70,
72–75] (6 papers) that introduces heterogeneous architecture
and hybrid architecture implemented using different tech-
niques of categories A, C, and D. Recently, another research
group [62, 63] added a cascade SVM implementation in the
literature based on a proposed multicore architecture using
different hardware techniques of categories A, C and E.
In addition, some works have studied the quantization
impact on the classification accuracy rate resulted from
applying the fixed-point number formatting (bit-width pre-
cision) in the hardware implementation [23, 27, 28, 32, 44,
74]. They aim to reduce hardware area while maintaining
high accuracy. Moreover, Afifi et al. [60, 61] have studied
the trade-off between the speed/acceleration and hardware
resources utilization/area with applying some different
hardware architectures (HLS optimization directives), fol-
lowed by similar analysis study focusing on design space
exploration presented in [66, 67]. As a result of applying
different techniques for reducing hardware complexity and
gaining acceleration, some implementations reported some
loss in the classification accuracy rate [21, 32, 57, 67–69,
73–75]. Furthermore, many works report classification
speedup results compared to similar software implemen-
tations [23, 32, 35, 36, 54, 55, 57, 61–63, 66–68, 70, 72],
and few works present a comparison with some related
FPGA implementations in the literature [32, 60–63, 70,
72, 74, 75].
Results Comparison and Discussion
Table 7 presents some results provided by selected reviewed
papers (17 papers). Samples of results have been carefully
extracted from the papers, while some parameters are either
unclear or ambiguous to easily define in the proposed table
or not provided/applicable. Also, some articles are excluded
because of few or no hardware implementation results have
been explicitly provided. This comparison includes different
architectures and implementations for various SVM types
and kernels implemented for different applications.
From Table 7, it is clear that low reasonable hardware
resources utilization is achieved in [36, 38, 60, 62, 64],
where [38] is the least. From the limited number of works
that report the power consumption results, only five imple-
mentations [31, 51, 60, 62, 64] achieve low values of around
1.7 watts, which are realized on the latest FPGA generation.
The least power consumption of 1.5 watts is successfully
achieved in [64],while the highest power of 15 W is reported
in [11]. The highest number of SVs of 2048 and highest
dimensionality of 2048 are considered in [19]. Almost all
introduced classification accuracies are realistic and greater
than 75%, while only one [57] has achieved low rate of
60.6% with 16.2% loss in accuracy. The least processing
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Table 7  Comparison of results
Refer- FPGA resources Power FPGA #SVs Dimension Accuracy % Processing time/ Frequency Category SVM
ence (W) speed (MHz)
Slices LUTs BRAM DSP

[17] 58,688 – 800 768 – Virtex-6 760 128 – 0.9 µs 370.096 A Binary RBF
[11] 59,208 122,637 2049 – 15 Virtex-5 16 – – 0.02 s 200 A Binary Gaussian
[19] 12,674 41,135 132 64 – ML505 2048 2048 – 712.66 µs 92 A Binary linear
[27] 42,600 250,552 1001 502 – Stratix-IV 474 500 98 47.2 ms 21.2 fps 100 A Multiclass linear
[31] 7228 5698 14.5 8 1.693 Zynq Z-7010 – – 96.4 25 ms 100 A Multiclass linear
[32] 9646 38,179 60 52 – ML509 100 500 82 0.25 ms 50 A Multiclass RBF
[34] 23,220 8887 74 64 – ML505 818 400 76–78 40–122 fps 100 B Binary RBF polynomial
[36] 1810 1705 21 21 – ML 403 1024 20 – 7.34 µs 142.9 ABC Binary linear
[38] 461 461 – 7 2.021 Virtex-6 192 120 – – – BC Multiclass polynomial
[51] 33,360 33,360 – 0 1.703 Virtex-7 74 – – – – BD Multiclass
[60] 2676 2267 12 5 1.752 Zynq-7 248 27 – 141.38 µs 100 AE Binary linear
[64] 1046 858 1 5 1.54 Zynq-7 61 27 97.9 1.5 µs 100 AE Binary linear
[54] 11,589 9141 99 81 – Virtex-4 18–35 – 98.67 0.27 ms 151.286 E Multiclass Gaussian
[55] 21,305 14,028 106 152 – Zynq-7000 1024 – 93.6 0.02 ms – AE Binary RBF
[57] 6373 11,943 – 64 – Virtex-II – – 60.6 14.18 ms 42.012 E Multiclass RBF
[69] 13,038 31,854 131 59 3.2 ML505 254 400 84 70 fps 84 ADF Cascaded linear polynomial
[75] 20,153 35,532 256 59 4.9 Spartan-6 122 400, 1062 80 40 fps 70 ADF Cascaded linear polynomial
[62] 4304 3414 2 10 1.74 Zynq-7 200 27 97.9 72.5 1.8 µs 250 AEF Cascaded linear
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time of 0.9 µs is achieved with a high frequency of 370 MHz
in [17], while others realize different real-time values of µs
and ms units (47 ms is the highest [27]). Some papers report
the processing speed in terms of frame rate, where real-time
image processing is achieved from 40 fps to the highest 122
fps achieved in [34]. Finally, a variety of good acceptable
results is achieved by various presented implementations,
where 9 papers include more than one architecture (catego-
ries) in their implementations. Still more optimization is
required to achieve the best/optimum trade-off between dif-
ferent parameters discussed in this comparison study.
Limitations and Challenges of Existing Works
This study reveals critical limitations and existing challenges
faced by the surveyed works:
• Various simplification methods are used for reducing the
hardware complexity and achieving efficient/optimized
hardware implementation results (such as the multiplier-
less method), which affect classification accuracy.
• Fully parallelized processing is not effectively addressed
in case of implementing SVM with very large-scale/
dimensionality, which requires an excessive number of
processing cycles when implemented over limited hard-
ware resources.
• In case of implementing SVM with a very high number
of SVs for a large-scale problem/application, the memory
storage and management problem is not effectively stud-
ied.
• Many SVM implementations are designed targeting spe-
cific application, which are not capable of any extensions
and not easily adapted for various applications.
• Some architectures are not simply designed, which have
shortage in meeting flexibility and scalability conditions
of realizing an efficient embedded system.
• The difficulty of meeting all important constraints of
embedded systems such as real-time, high performance,
low cost, low power and others.
• Very few implementations report the power consumption
results, which is very challenging to achieve low-power
embedded system.
• Most existing implementations are implemented on old
versions of FPGAs and designed using traditional meth-
ods and tools/technologies.
• The trade-off exists between classification performance/
speed and hardware resources utilization needs more
optimized solutions/methods.
• The primary trade-off exists between meeting embedded
systems constraints and preserving/maintaining classifi-
cation accuracy level.
Leading Research Groups
From reviewing the presented papers, we identify three lead-
ing research groups that are actively working on implement-
ing SVM on FPGA.
Group 1: One unique research group is exclusively work-
ing on FPGA-based cascaded SVM classification archi-
tecture for object detection [69, 70, 72–75] (category F).
However, another research group has recently implemented
a cascade SVM classifier for melanoma detection [62] (S.
Afifi et al. research group). This research group first pro-
pose a heterogeneous architecture of low-precision and
high-precision classifiers in a cascade (the first cascaded
SVM on FPGA), where DPR is then applied for the switch-
ing (category C). Next, a hybrid cascaded architecture is
proposed for combining parallel and sequential processing
modules in a pipelined design (category A). In addition, a
hardware reduction method (category D) is proposed that is
based on replacing expensive multipliers with simple shift
operations, achieving reduction in area and power con-
sumption. They lately propose an optimized architecture
by adding a response evaluation method (NN classifier) to
improve classification prior to the final classification stage
in the cascade, for boosting the overall classification. Also,
they apply a feature extraction phase before the complicated
final stage for improving the accuracy rate. Good results are
achieved for real-time processing of high-resolution images
in terms of fps. But, their implemented architectures that are
applied for object detection suffer from slight loss in detec-
tion accuracy rates. Also, the power consumption results that
are greater than 3 watts are considered high for embedded
systems deployment. These also prove the existing challeng-
ing trade-off between efficient classification accuracy and
meeting significant embedded systems constraints, in which
they manage to present an adequate compromise in their
latest publication.
Group 2: Another research group led by H. Hussain
[35–37] is working on the parallel systolic array implemen-
tation (category B), exploiting the advantage of the massive
DPR feature in the FPGA aiming to reach flexibility and
scalability (category C). They implement various copies
with different SVM parameters to fulfill user requirements at
run-time and great speedup results are achieved compared to
software implementations on GPP. Then, these implementa-
tions are used to realize a multicore architecture of different
SVM copies with applying DPR, which offers flexibility of
changing cores on-the-fly during run-time to be used then
for ensemble classification. But, no specific application is
applied to employ and use the proposed architectures and so
no classification accuracy is measured. They lately imple-
ment a DPR-based adaptive multiclassifier to be used as an
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SVM or KNN classifier with different parameters saving
more space in the device, which could be extended in the
future as an ensemble classifier targeting classification of
bioinformatics microarray data. But also, no real application
is applied for verifying the usage and classification of the
implemented multiclassifier. From their DPR implementa-
tions, 8 × reduction in reconfiguration time is gained over
reconfiguring the whole FPGA device. Finally, they gained
flexibility and adaptability with good speedup results in
reconfiguration time, but with no verification of the clas-
sification functioning. Also, no optimization methods are
used for reducing hardware resources utilization, and no
power consumption measurements are presented for meet-
ing embedded systems constraints.
Group 3: An interesting and unique research work is pre-
sented by another research group led by S. Afifi [59–64]
which exploit the most recent hybrid Zynq SoC platform and
the modern UltraFast HLS design methodology (category
E). They develop the first HLS SVM IP/core on Zynq SoC
exists in literature targeting low-cost and real-time mela-
noma detection. A hardware/software co-design is first pro-
posed to realize a Zynq accelerator, which is implemented in
HLL (C/C + +) applying available hardware directives/tech-
niques through the HLS tool that simplifies FPGA design
and reduces development effort and time. The implemented
system is considered the first hardware/software SoC exists
in the recent period. Then, the hardware design is extended
to achieve a full SVM IP running on Zynq SoC with high
performance and low cost. They are targeting meeting chal-
lenging embedded systems constraints, while achieving
efficient classification without any loss in the accuracy rate
resulted from the hardware implementation. Their experi-
mental results demonstrate optimized hardware results of
high performance, low resources utilization, and low power
consumption as well as high classification accuracy. Their
implemented low-power embedded system meets the critical
power constraint and shows the least power dissipation of
1.5 watts [64] compared to other reported implementations
(Table 7). Still future testing is required for validating online
classification accuracy rate for melanoma detection. Lately,
they proposed a scalable multicore architecture based on
adding more SVM IPs to implement a cascade SVM classi-
fier on a single device/SoC for improving diagnosis verifi-
cation. The implemented cascade classifier achieved lower
resources utilization and power consumption than imple-
menting a single SVM IP, in addition to improvement in the
classification accuracy and speed. Consequently, this group
added a new FPGA-based cascaded SVM implementation
in the literature besides that first implementation of group 1.
Moreover, the powerful DPR feature of the FPGA was lately
applied to the proposed cascade SVM classifier, where more
optimization in implementation results was achieved, while
gaining flexibility, adaptability, scalability, and applicability.
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In addition from Table 7, this HLS-based implementation
of cascaded SVM [62] showed remarkably lesser hardware
resources utilization and power consumption than group 1′s
implementation [69, 75], which promises meeting challeng-
ing embedded systems constraints.
Although this survey paper clarifies the work that has
been done to address the research questions, however further
effort is required to find answers to all research questions
(listed in Section I). In the next section, we suggest promis-
ing future work to be done in the subject area to fill the gaps
and find answers to the research questions.
Conclusion and Future Directions
This paper is a unique survey study that presents and clas-
sifies different hardware architectures used for implement-
ing SVM classifiers on FPGAs. In addition, it provides
critical analysis and detailed comparison with discussions
and identifies leading research groups, limitations, chal-
lenges, and research gaps. In conclusion, the main research
gap is finding an optimum solution for the challenging
trade-off between achieving efficient classification accu-
racy and meeting significant embedded systems constraints
of high performance, low area, cost and power/energy
consumption.
Finally, the following research directions are suggested
to be used in the future by hardware designers in order to
address the research questions, limitations, gaps and chal-
lenges identified in this reviewed study:
• An optimized hardware architecture is required to over-
come the challenging trade-off, aiming to reach an effi-
cient real-time embedded classification with high perfor-
mance and low cost.
• The existing techniques could be combined efficiently to
achieve optimized results.
• New hardware-based methods are needed targeting
improvement of the online classification accuracy rate
on hardware.
• The hardware-friendly kernel needs more improvement
regarding maintaining the classification accuracy rate.
• Effective techniques need to be studied for decreasing
memory requirements and hardware resources utilization
in case of large-scale applications.
• The massive DPR feature should be widely and effi-
ciently exploited for gaining more flexibility, adaptabil-
ity and scalability in addition to more improvements in
speed, area and power consumption.
• Additional research work is demanded to focus on imple-
menting multiclass classifiers and nonlinear kernel-based
classifiers.
SN Computer Science (2020) 1:133 Page 15 of 17  133
• The evolvable hardware method needs to be investigated
for achieving adaptive classification systems.
• Flow control and memory management should be effec-
tively studied for efficient data transfer in the classifica-
tion system.
• The multicore architecture should be investigated for
working as an ensemble, multiclass or cascaded classifi-
cation (by adding a voting/controller mechanism).
• Using the latest FPGA devices/SoCs and technologies
should be considered in the hardware implementations,
in addition to exploiting modern development tools and
design methodologies (e.g., HLS) for reaching efficient
designs with optimized results.
Conflict of interest  The authors declare that they have no conflict of
interest.
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