Makefile

Introduction
In this wiki I'll be introducing the concepts to design your own makefiles.
The GNU Makers formally defined as a tool that controls generation of executables and non-source files of a program,
from the program source files. This is very important because we can use GNU Make to do more than just compile
but also generate software dependencies, statistical information and many other items.
Makefile provide special directions and procedures to make, in order to create an executable file from a multitude of
input files.
One or more files used to tell make how to build the project,

Each makefile have some build rules or build targets that generate output files e.g:

Note:
All, clean, main.out and main.o are called targets

Makefile Architecture:

Each target contains a special syntax.

The target name is provided first followed by a colon and then a prerequisite list.
You can think of the target name as our output file like objects or executables.
Prerequisite files are target files that must exist before the current target can be executed.
Following the target prerequisites is a recipe or a set of commands that will executed in order to produce this target file.
The commands that are run are the same as the commands you ran from the command line. These include things like
GCC to compile and linking
Putting this altogether, we can tell make to generate a target file by giving make the target name. Make will then search
through a given or a default makefile looking for a matching target name. It then checks if the prerequisites exist
and generates them if not and then it executes the recipe.

Makefiles have their own syntax similar to other software languages. But with the purpose of providing the necessary
directions for compilation. Make does not execute the full makefile nor does it execute every line from top to bottom.
However it has very similar characteristics to the C programming
Makefiles can have comments and they start with a number sign. Write as many comments as you like and document
what your makefile does at the top.

You can include other makefiles with the include command and the included files can contain all the same
characteristics.
If your lines get too long, you can use the backwards slash to make your makefile more readable, this is line
continuation.

You can create variables to make your makefile more readable and portable by reusing the same variable names instead
of retyping all the contents.
You can define many rules with many command recipes.

In each command in the recipe must start with a tab.

Finally, targets can be used by other rules.

Variables are very important for our use in writing makefiles, as they allow us to remove a lot of duplicated code.
There are different types of variables and different ways to get data assigned to them. The most important types is
called recursively expanded variables (=)
You can actually create variables that point to your source files and include paths. This allows us to make even more
generic rules for compiling based on these variables. Let's call one INCLUDE= which could reference every include
directory. Let's call another one SRCS= which can list all of our source files.
Conclusion:
Now you can combine what we have used so far and we can begin to make targets very flexible, readable, and
portable. We can define a makefile rule for a particular target by listing every single command, flags, and prerequisites
for every particular target.

Alternatively, we can create rules that utilize variables and simply the build rule. Given how long a compile command
can be, you can group options into different variables and reuse them in other places.

makefiles have special variables called automatic variables. Automatic variables can be used to reduce the amount of
typing for a particular rule.
Here, we have two automatic variables, one with with the dollar $^, and another one with $@. These mean the target
and pre-requisite list, and you can use these instead of retyping those long statements.