Encyclopedia of
Nanoscience and
SiGe/Si Heterostructures
C. W. Liu
National Taiwan University, Taipei, Taiwan, ROC
L. J. Chen
National Tsing Hua University, Hsinchu, Taiwan, ROC
CONTENTS
1. Introduction
2. Strain Effect
3. Device Performances
4. Fabrication Technologies
Glossary
Acknowledgments
References
1. INTRODUCTION
The Si/SiGe:C heterostructures add a rich variety to the
monotonic Si world. The misfit between Si and Ge, which
is the initial obstacle to fabricating such material systems,
becomes an advantage in tailoring the electronic properties
of Si-based devices. Si/SiGe heterojunction bipolar transis-
tors have a cutoff frequency of 210 GHz [1] and a maximum
oscillation frequency of 285 GHz [2] with carbon incor-
poration in the base. The figures of merit of metal-oxide-
silicon-field-effect transistors (MOSFETs) are also enhanced
to some extent with the use of the strained Si on the relaxed
SiGe buffers for both N and P channel devices [3, 4]. The
reported peak hole mobility is 2700 cm2 /Vs in the strained
Ge channel [5], and the reported peak electron mobility
is 800 cm2 /Vs in the strained Si channel [6]. Heterojunc-
tion devices such as resonant tunneling diodes [7–9] and
modulation-doped FETs [10, 11], which were only possible
with III–V semiconductors in the past, can now be made
from SiGe/Si heterostructures. Table 1 gives a summary of
SiGe device performance.
Si1−x Gex material is a solid solution of Si and Ge with
an intrinsic lattice constant larger than that of Si. A simpli-
fied way to look at Si1−x Gex is that it is made of “Si1−x Gex
atoms” in a diamond structure, and the virtual “Si1−x Gex
atom” inherits the characteristics from both Si and Ge, with
the atomic fraction as a weighting factor. In most cases, a
linear weighting assumption is good for applications. For
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example, the relaxed lattice constant of a Si1−x Gex crystal
is a liner sum of the lattice constants of Si crystal and Ge
crystal. The virtual Si1−x Gex atom approximation ignores the
random nature of Si1−x Gex , where the traveling carriers in
the Si1−x Gex crystal visit Ge atoms with the frequency of x
and visit Si atoms with the frequency of 1 − x, but in the
virtual Si1−x Gex crystal, the carrier sees only one kind of
atom, the Si1−x Gex . This kind of random alloy effect has
to be taken into account when randomness is important.
For example, the alloy scattering allows nonphonon radia-
tive recombination in Si1−x Gex , which does not occur in Si
and reduces the carrier mobility. For a good approximation,
Si1−x Gex is a diamond structure occupied by virtual Si1−x Gex
atoms, and randomness has to be taken into account by alloy
scattering in certain circumstances.
2. STRAIN EFFECT
Si and Ge have the same diamond lattice structures and are
completely miscible for a full range of composition, but have
different lattice constants. The misfit is defined as the lattice
constant difference between Si and Ge with respect to the Si
lattice constant and is around 4%. For a linear assumption,
the misfit between Si1−x Gex and Si is ∼0.04x. For example,
the misfit between Si0!75 Ge0!25 and Si is 1%, that is, the 100
Si lattice units have the same length as the 99 Si0!75 Ge0!25
units. For device applications such as heterojunction bipo-
lar transistors (HBTs), the misfit dislocation at Si/Si1−x Gex
interface has to be avoided, and the virtual SiGe atoms have
to bond with the Si atoms one by one in the underlying
Si substrates. The dislocation-free strained Si1−x Gex is also
described as “pseudomorphic.” The Si1−x Gex on the Si is
under compressive strain, since the lattice constant of Si is
smaller compared with Si1−x Gex . The strain causes changes
in the crystal structures and electronic structure of Si1−x Gex .
2.1. Critical Thickness
Since the Si substrate is much thicker (∼0.7 mm for 200-mm
wafers), the original cubic Si1−x Gex lattice with a lattice con-
stant larger than that of Si has to be distorted into the
Encyclopedia of Nanoscience and Nanotechnology
Edited by H. S. Nalwa
Volume 9: Pages (1–18)
2 SiGe/Si Heterostructures

Table 1. The achieved performance of electronic and optoelectronic devices based on SiGe technology.

Device Figure of merit Growth technique

2
Strained Peak effective electron mobility 800 cm /Vs [6] Relaxed buffer
NMOSFET
Strained Peak effective hole mobility 2700 cm2 /Vs [5] Relaxed buffer
PMOSFET
NPN-HBT fT = 210 GHz [1], fmax = 285 GHz [2] Pseudomorphic
PNP-HBT fT = 59 GHz at RT, fT = 61 GHz at 85 K [12] Pseudomorphic
Heterojunction 1.47 A/W at 850 nm, bandwidth = 1!25 GHz [13] Pseudomorphic
phototransistors
NMODFET Gm = 460 ms/mm fT = 76 GHz, fmax = 107 GHz at RT Relaxed buffer
[14] Gm = 730 ms/mm fT = 105 GHz,
fmax = 170 GHz at 50 K
PMODFET Gm = 300 ms/mm fT = 70 GHz, fmax = 135 GHz at Relaxed buffer
RT [15]
NRTD P/V ≥ 7.6 at RT [7], 2 at 4.2 K [8] Relaxed buffer
PRTD P/V = 1.8 at RT, 2.2 at 4.2 K [9] Pseudomorphic
Detector (IR) 1.3 "m, 1.5 "m [16] Quantum dots
Detector (LWIR) Schottky barrier: #c = 10 "m [17] Pseudomorphic
LED 1.3 "m, 1.5 "m at RT [18, 19] Pseudomorphic,
quantum dots
The last column indicates the growth techniques used to obtain device-quality material.

tetragonal symmetry with the built-up strain energy. The than the critical thickness and/or is annealed at high tem-
in-plane lattice constant of Si1−x Gex is reduced to that of Si, perature. Relaxed Si1−x Gex is not good enough for devices
and the vertical lattice constant increases by 80% of the in- with vertical carrier transportation such as HBTs, since both
plane lattice constant reduction. Si1−x Gex under stress may the threading dislocations and misfit dislocations at the
yield to form dislocations if the compressive strain energy
is high enough. Strained Si1−x Gex with dislocations grown
on Si is shown schematically in Figure 1. The thickness
of strained Si1−x Gex has to be thin enough to prevent the
dislocation formation. The maximum thickness to have a
defect-free Si1−x Gex epilayer is the so-called critical thick-
ness. To minimize the sum of the strain energy and disloca-
tion energy, the thermal equilibrium critical thickness (hc ) : Si Ge virture atoms
[20] can be derived as : Si atoms

x = 0!55 ln$10hc %/hc (1)

Proof's Only
where hc is in nanometers. For example, the critical thick-
ness is ∼13 nm and ∼1.5 nm for strained Si0!8 Ge0!2 and Ge
on Si, respectively. This value is too small to be used in
many applications. The meta-stable growth away from ther-
mal equilibrium is desired to increase the critical thickness.
The selective epitaxial growth [21] and the low temperature dislocation
epi-growth are common meta-stable growth methods. The
enhancement by a factor of at least 4 can be obtained for
x less than ∼0.5, but it really depends on the details of the
growth conditions. Generally speaking, the smaller area of
growth and the lower temperature of growth can have a
larger meta-stable critical thickness. Most Si1−x Gex reactors
have a growth temperature of 550–650 $ C. However, metal-
stable films will generate the defect if the thermal budget
of the further process is too high. This is a challenge in the
integration of Si1−x Gex into a CMOS process.
In ultra-large scale integrated circuits (ULSIs), the build-
ing devices are N-channel or P-channel MOSFETs. Strained
channels can improve the device performance of MOSFET. Figure 1. The strained SiGe grown on (100) Si. The misfit dislocation
Si1−x Gex grown on Si can be relaxed if it is much thicker is the missing bond between the Si and SiGe atom.
SiGe/Si Heterostructures
Si/Si1−x Gex interface can act as recombination centers. The
Si or Ge grown on relaxed Si1−x Gex is under tensile and
compressive strain, respectively. The defects in the strained
Si or Ge layer are the threading dislocation as shown in
Figure 2, and most misfit network exists in the relaxed buffer
layers. The threading dislocations in the strained Si and Ge
channels have a small effect on in-plane carrier transport,
especially for small feature devices, if the density is low
enough (below 105 cm−2 ). The strained Si and Ge channels
increase the carrier mobility, and thus the device speed is
enhanced in the same MOSFET technology node. For the
Si or Ge grown on relaxed Si1−x Gex layers, the same critical
thickness constraint is also applied. Note that the relaxed
Si1−x Gex can be obtained with graded relaxed buffers [22],
silicon on insulators (SOI) [23], and regrowth after smart
cut [24]. Equation (1) can be used to estimate the criti-
cal thickness of strained Si or Ge, but x is the Ge fraction
difference between strained Si (Ge) and relaxed Si1−x Gex
buffers.
Because of the small lattice constant of diamond (made
of carbon), the incorporation of carbon into SiGe on Si can
compensate for the compressive strain from the large Ge
atoms. A strain-free SiGeC film can be obtained if the ratio
of the Ge fraction to the C fraction is ∼11 (compensation
ratio), obtained from the linear interpolation of the lattice
constant between Ge and silicon carbide. Note that the sili-
con carbide is a compound with the same number of Si and
C atoms in the face center cubic sublattices. However, only
up to a few percent ( ∼2.5%) of carbon can be incorporated
into SiGe or Si [25, 26]. Note that Si and Ge can be mixed
at any concentration.
Si1−y Cy and Si1−x−y Gex Cy alloys with tensile strain can be
fabricated by incorporating carbon into Si and incorporating
carbon content above the compensation ratio into Si1−x Gex ,
respectively. In principle, the critical thickness concepts can
still be applied to alloys with tensile strain. However, relax-
ation mechanisms in addition to the misfit dislocations, such
as silicon carbide precipitation, and stacking fault forma-
tion, can also occur for thick and high-temperature annealed
Si1−y Cy and Si1−x−y Gex Cy films.
threading dislocation
strained Si or Ge
relaxed SiGe
Si
Proof's Only
misfit dislocation
Figure 2. The misfit dislocation and threading dislocation. The misfit
dislocation is at the Si/SiGe interface, and threading dislocation ends
at the surface of the epilayers.
3
2.2. Growth Mode, Self-assembled Quantum
Dots, and SiO2 Dots
For Si1−x Gex layers thicker than the critical thickness, the
relaxation is mainly apportioned by misfit dislocation gener-
ation at low Ge fraction (< ∼0.4), although the morphol-
ogy roughening can also lower the elastic energy [27]. For
the high Ge fraction, the roughening is the dominant mech-
anism for relaxation, since the roughening barrier is suf-
ficiently small in energy for most growth conditions. The
roughening can be represented by the Stranski-Krastanow
growth model. After the two-dimensional layer-by-layer
growth reaches some critical thickness, the growth becomes
three-dimensional island growth. Note that the critical thick-
ness here can differ from the thermal equilibrium criti-
cal thickness (Section 2.1). The two-dimensional layer is
also called the “wetting layer,” and the islands are called
“dots” or “quantum dots,” depending on the size. The three-
dimensional islands remain dislocation-free, but the top lay-
ers of the islands start to relax. This relaxation can stop the
build-up of strain energy in the Ge islands. Further growth
can cause the islands to coalesce, and misfit dislocations can
occur.
Because of the different strain conditions on Ge layers,
that is, the strained wetting layer and relaxed islands, the
Si layer grown on the Ge dots has a tensile strain, whereas
the Si layer on the Ge wetting layer is strain-free. If this Si
layer is thinner than the correlation length [28], the strain
condition remains, and the further Ge deposited on the Si
layer (spacer) can vertically align with the underside of the
Ge layers. The Ge dots of individual Ge layers are vertically
self-assembled in a row in the same position [29] (Fig. 3).
Ge quantum dots can also be fabricated with fine structures
such as Ge/Si/Ge composite dots (Fig. 4) to improve uni-
formity, dot area coverage (Fig. 5), and photoluminescence
efficiency. These Ge dot structures are used for photodetec-
tors at wavelengths of 1.3, 1.5, and 10 "m (see Section 3.3.2).
To reduce the thermal budget of Si1−x Gex -based devices,
a low-temperature oxide is often used. Liquid-phase deposi-
tion can provide a low-temperature oxide on Si1−x Gex . It is
interesting that silicon dioxide dots can be deposited on the
Si cap layers of self-assembled Ge dots with a liquid phase
deposition method. The Si capping layer directly above the
Ge dots has a tensile strain, whereas the Si cap on the wet-
ting layer is not strained. The tensile strain can enhance the
silicon dioxide nucleation and deposition on the Si surface,
and SiO2 dots are formed directly above the Ge dots with
the SiO2 wetting layers between the dots [29] (Fig. 3).
2.3. Electronic Structures
Because of the tetragonal distortion of strained Si1−x Gex
grown on relaxed (001) Si1−y Gey layers, the energy bands of
electrons and holes change according to the strain condition.
For the compressive strain, the originally sixfold degener-
ate conduction band valleys split into a low-energy group
of four valleys perpendicular to the growth direction and
a high-energy group of two valleys along the growth direc-
tion. Similarly, the originally degenerate light and heavy hole
bands split into the high-energy heavy-hole band and the
low-energy light-hole band. For tensile strain such as that of
4 SiGe/Si Heterostructures

(a) strained Si on relaxed Si1−x Gex , the results are similar, but
the energy levels switch between the degenerate groups. The
20 nm two conduction valleys along the growth direction are lower
in energy than the other four valleys in the strained Si. So
are the valence bands. The effects are sometimes referred
to as “uniaxial splitting.”
The strained Si1−x Gex on Si has a smaller lattice constant
in the two in-plane directions, and larger lattice constants
in the growth direction as compared with originally relaxed
Si1−x Gex . The net volume decrease (hydrostatic term) of
the tetragonal Si1−x Gex unit cell grown on Si leads to a
(b)
shrinkage of the bandgap, that is, the valence band moves
SiO2 up and the conduction band moves down. Note that the
strained Si on relaxed Si1−x Gex has the opposite effect, and
Si cap the net volume increases. The bandgap of strained Si1−x Gex
Ge
on Si is given in Figure 6 with the relaxed bandgap, and the
optoelectronic devices for optical communication (1.3 and
1.5 "m) can be easily implemented by the strained Si1−x Gex
bandgap. At low Ge concentration, the bandgap reduction is
∼7.5 meV per % Ge for strained Si1−x Gex grown on Si. The
Si spacer conduction band discontinuity between strained Si1−x Gex
Ge
and Si is often negligible. For strained Si grown on relaxed
Si1−x Gex buffers, the bandgap reduction of Si is ∼4 meV
Si spacer
Ge ~100 nm
~6 nm per % Ge. The smaller bandgap reduction of strained Si
~2 nm
on relaxed Si1−x Gex as compared with the strained Si1−x Gex
Si buffer layer ~ 50nm on Si is due to the fact that the tetragonal distorted lat-
tice of strained Si has a net volume expansion to widen the
p-type Si substrate
conduction band edge and valence band edge. The conduc-
tion band edge of strained Si is lower than that of relaxed
Figure 3. (a) TEM micrograph of multilayer Ge dots. The spacer thick-
Si1−x Gex (&Ec ∼ 6 meV/%), and the electron confinement is
ness is ∼20 nm. The SiO2 dots are also formed above the Ge dots.
(b) Schematic diagram showing the strain field in Si layers. Adapted
possible in the relaxed Si1−x Gex /strained-Si structures. The
with permission from [29], C. W. Liu et al., Appl. Phys. Lett. (2003). modulation doped devices can thus be made (Section 3.2.3).
© 2003, American Institute of Physics. The bandgap of strained Si1−y Cy on Si is also reduced with
respect to Si with the experimental value of 68 meV/% C
[30].
There are two effects for carbon incorporation into
Si1−x Gex on the bandgap:

Ge/Si/Ge 1. Carbon can change the strain condition of the pseu-

composite dots
domorphic film, and this effect on band structure can

1
1.2

relaxed SiGe
1.1
1.2
wavelength λ (µm)

1.0
Figure 4. Composite dots with fine structures such as Ge/Si/Ge com-
Energy (eV)

posite dots.
0.9 1.4
(a) (b)
0.8
0.5 µm 0.5 µm 1.6
strained SiGe
0.7 1.8

Proof's Only
2
0.6
2.2
2.4
0.5
0.0 0.2 0.4 0.6 0.8 1.0
Ge mole fraction

Figure 6. The bandgap of strained Si1−x Gex on a (001) Si substrate

and relaxed bandgap of Si1−x Gex alloys. The shadow areas indicate the
optical communication bandwidth of 1.3 and 1.5 "m. Reprinted with
Figure 5. AFM picture of (a) composite dots and (b) conventional dots. permission from [16], B.-C. Hsu et al., “International Electron Device
The composite dots have a larger coverage area. Meeting” 2002, pp. 91–94. © 2002, IEEE.
SiGe/Si Heterostructures 5

be taken account of in a manner similar to that of Ge 1000

incorporation. in-plane
NA=1015cm–3
2. Carbon also changes the fundamental bandgap [25, 31],

Majority Hole Mobility (cm2/Vs)

out-of-plane
and the relaxed Si1−y Cy bandgap decreases with car-
bon concentration initially because of the local lattice NA=1017cm–3
disorder, despite the large bandgap of diamond.

2.4. Mobility NA=1018cm–3

2.4.1. Mobility in Relaxed and Strained

Si1−x Gex alloys 100
NA=1019cm–3

The theoretical calculation [32] and experimental [33] val-

ues of the majority hole mobility in relaxed Si1−x Gex alloys
are plotted in Figure 7. The decrease in mobility with Ge
concentration is due to the alloy scattering, and an alloy
scattering potential of 0.7 eV is used in the calculation to fit
the measurement data.
Because of the impurity scattering, the mobility depends
on the doping concentration. The in-plane and out-of-plane
majority hole mobilities in strained Si1−x Gex layers for dif-
ferent doping concentrations are shown in Figure 8 [34].
Note that the hole mobilities in n-type material and p-type
material are different from the terms of majority hole mobil-
ity and minority hole mobility, respectively. So are electron
mobilities.
In the calculation, the alloy scattering potential deter-
mines the mobility value [37]. The majority hole mobilities
in the strained Si1−x Gex alloys based on Monte Carlo sim-
ulation decrease by a factor of 2–3 if an alloy potential of
1.4 eV is used, as compared with 0.7 eV up to the dop-
ing concentration of 1019 cm−3 . The hole mobility of strained
Si1−x Gex calculated by different groups [31, 35, 36] is qual-
itatively similar. For a doping concentration of ≥ 1019 cm−3 ,
the mobility depends weakly on Ge content, and the alloy
scattering is not important. The majority hole mobility is
important for the p-channel strained Si1−x Gex FET, where
the current is made of the majority hole current.
Both in-plane and out-of-plane minority electron mobil-
ities at different doping concentrations are plotted in
Figure 9 [37, 38]. The out-of-plane mobility is especially
500
0.0 0.1 0.2 0.3 0.4
Ge Mole Fraction
Figure 8. The in-plane and out-of-plane majority hole mobility of SiGe
strained alloys for different doping concentrations.
important for npn Si/SiGe heterojunction bipolar transistor
applications, where the electron transit time in the base is
shortened by the electrical field generated by the graded Ge
profiles. In-plane electron mobility decreases with increas-
ing Ge fraction, whereas out-of-plane electron mobility
increases with Ge fraction at small Ge content. The out-of-
plane mobility is larger than the in-plane mobility.
Klaassen model [39, 40] is commonly used for minority
and majority mobility. Klaassen’s model takes into account
four scattering mechanisms: lattice scattering, ionized impu-
rity scattering, phonon scattering, and carrier-carrier scatter-
ing. The last mechanism makes the minority and majority
carrier mobilities different.
2.4.2. Mobility in Strained Si
Figure 10 shows the in-plane electron and hole mobilities
at 300 K in strained Si, based on [41]. Here the carrier-
carrier scattering is neglected, and majority mobility and
minority mobilities are the same. For tensile strain (posi-
tive strain value), the in-plane electron mobility increases
rapidly, and electrons populate the two lower energy & val-
leys along the growth direction. The lower conductivity mass

450

400 350
out-of-plane
Minority Electron Mobility (cm2/Vs)

in-plane
Hole Mobility (cm2/Vs)

350
300

Proof's Only
300 NA=1018cm–3

250
250 NA=1019cm–3
200
Theoretical mobility
150 Experimental Data 200 NA=1020cm–3
100

50 150

0
0.00 0.04 0.08 0.12 0.16 0.20
100
Ge Mole Fraction 0.00 0.05 0.10 0.15 0.20 0.25 0.30
Ge Mole Fraction
Figure 7. Theoretical values of the hole mobility in relaxed SiGe alloys
at 300 K and a doping concentration of NA = 1016 cm−3 , with experi- Figure 9. In-plane and out-of-plane minority electron mobilities of
mental results of Gaworzewski et al. [33]. SiGe alloys at different doping levels at 300 K.
6 SiGe/Si Heterostructures
(a)
2400
2200
Electron mobility (cm2/Vs)
2000
1800
1600
1400
1200
1000
–1.5 –1.0 –0.5
Strain (ε) (%)
(b) 2500
2000
Hole mobility (cm2/Vs)
1500
Proof's Only
1000
500
–1.5 –1.0 –0.5
Strain (ε) (%)
Figure 10. The in-plane (a) electron and (b) hole mobility in strained
Si. Reprinted with permission from [70], F. Schafer, Semicond. Sci. Tech-
nol. 12, 1515 (1997). © 1997, Institute of Physics Publishing.
is the main cause of increased mobility with the help of the
small decrease of intervalley scattering (the strong g-type
process remains effective). The electron mobility reaches
∼2300 cm2 /Vs at a tensile strain of about 0.8% (correspond-
ing to a fully relaxed Si!8 Ge!2 buffer layer). On the other
hand, the out-of-plane mobility in Si with tensile strain drops
rapidly with strain, since the conductivity mass is now the
large longitudinal mass. However, only the in-plane mobility
matters in the field effect device applications.
For the compressively strained Si, the in-plane electron
mobility initially decreases with the strain, since electrons
mainly populate the four & valleys perpendicular to the
growth direction with a large effective conductive mass. With
the further increase in compressive strain, the separation
energy between the twofold degenerate valleys and fourfold
degenerate valleys increases, and this reduces the intervalley
scattering. The in-plane electron mobility increases again.
Note that the out-of-plane electron mobility, controlled by
the small transverse mass, remains high.
The hole mobility in strained Si increases for strain of
either sign. The principal cause of the enhancement is the
split of the degeneracy between the heavy-hole and light-
hole bands at the ' point in the reciprocal space and
the reduction of the conductivity mass. For tensile strain,
the light hole band has a much higher energy than the
heavy-hole band, whereas for compressive strain the splitting
of these two bands remains comparable to kT. Therefore,
interband scattering in Si with tensile strain is not as effec-
tive as in the compressively strained Si, and this results in
larger hole mobility in Si with tensile strain.
Tensile strain improves both electron and hole mobil-
ities by reducing the effective transport masses and sup-
pressing intervalley phonon scattering. For the MOSFET
applications, the carrier in the inversion layers also suffers
the oxide roughness scattering, which decreases the mobil-
ity value in the Figure 10. The calculated electron and
hole inversion layer mobility enhancements in strained Si
are plotted in Figure 11 [42, 43]. The amount of strain in
0.0 0.5 1.0 1.5
Si is proportional to the Ge content in the relaxed SiGe
buffer layer. The electron and hole mobilities are expected
to increase with increasing strain and saturate at Ge con-
centrations of 20% and 40%, respectively, in the buffer lay-
ers. The saturation of mobility enhancement is related to
the diminishing benefit of strain-induced energy splitting.
The suppression of the intervalley scattering by energy split-
ting increases the mobility, but other scattering mechanisms,
such as oxide roughness scattering and other phonon scat-
tering, begin to dominate the low field mobility. At low tem-
perature, there are fewer phonons, and the smaller energy
splitting is enough to suppress the intervalley phonon scat-
tering. Therefore, the mobility enhancement saturation is
expected at even lower Ge content. Please note that both
NMOSFET and PMOSFET can use the strained Si channel
to increase the device speed.
0.0 0.5 1.0 1.5
2.4.3. Mobility in Strained Ge
Figure 12 shows the in-plane electron and hole mobilities
at 300 K in strained Ge [41]. The electron mobility shows
a noticeably complicated behavior. For tensile strain, elec-
trons begin to populate the conduction states at the ' point
at strains larger than 1%. Because of the small in-plane
effective electron mass in the ' valley, there is a dramatic
enhancement of mobility for strains larger than 1%. For
compressive strain, the electrons mainly populate the L
valleys at small strain, but the energy separation between
2.5
Mobility Enhancement Factor
2.0
1.5
Electron[Takagi et al.]
Hole[Oberhuber et al.]
1.0
0 10 20 30 40 50
Substrate Ge content (%)
Figure 11. The calculated electron and hole mobility enhancement fac-
tor in MOS inversion layers of strained Si.
SiGe/Si Heterostructures 7

104 (500–800 "m) substrates. The thin epitaxial Si1−x Gex film
has to fight with thick substrate to become relaxed with the
pay-off of defects. It is unlikely that Si substrates can be
thinned down far below 50 "m with mechanical stability.
Electron mobility (cm2/Vs)

A smart way to effectively grow Si1−x Gex on thin Si is to use

the silicon-on-insulator (SOI) substrates [44], and the Si can
be as thin as 10 nm on the buried oxide (BOX, commonly
103
in-plane
used insulator). The SOI devices have the extra advantages
of high speed, latch-up resistance, and radiation hardening.
If the bonding force between Si and BOX can be small com-

Proof's Only pared with Si and Si1−x Gex , a Si1−x Gex thicker than SOI can
easily be relaxed without any defect generation, and the thin
SOI becomes strained. Several variations have been invented
based on the basic idea.
102
–5 –4 –3 –2 –1 0 1 2 3 The BOX layer can be created by separation-by-
Strain ε (%) implanted-oxygen (SIMOX) technology after the Si1−x Gex
105 layer is grown on conventional bulk Si wafers [45]. The
implantation depth can reach Si or Si1−x Gex . The relaxed
in-plane films and BOX can be formed after high-temperature
(>1100 $ C) annealing. To obtain a relaxed Si1−x Gex layer
Hole Mobility (cm2/Vs)

with a large Ge fraction, the relaxed films can be further oxi-

104
103
–5 –4 –3 –2 –1 0 1
Strain ε (%)
Figure 12. Electron and hole mobility in strained Ge.
L valleys and the four-fold & valleys perpendicular to the
growth direction shrinks. The resulting larger intervalley
scattering causes a lower mobility. At large compressive
strain, all electrons stay in the & valleys. The mobility now
approximates a constant value, nearly equivalent to the &
valleys’ electron mobility in relaxed Ge. In practice, only the
compressively strained Ge can be grown. Therefore, there
is no advantage to using the Ge channel in the NMOSFET,
but it is interesting to note that the Ge with tensile strain
can have a direct bandgap.
For in-plane hole mobility, the situation is qualitatively
similar to that of strained Si. The compressive Ge has an
in-plane hole mobility greater than 2000 cm2 /Vs and is ben-
eficial for the PMOSFET application.
2.5. Relaxed SiGe on an Insulator
To have fully relaxed Si1−x Gex grown on Si, the Si1−x Gex
thickness has to be much larger (>10x) than the critical
thickness. The growth rate has to be high enough to ensure
a reasonable growth time. The growth of films at low tem-
perature takes a long time, but they might also have to be
annealed at high temperature after growth to obtain suffi-
cient relaxation.
The misfit and threading dislocations are generated in the
relaxed films. All of the problems arise from the thick Si
dized. The oxidation of Si1−x Gex can inject Ge into under-
lying Si1−x Gex films, and the underlying films can have a
higher Ge fraction.
Bond-and-etch-back SOI (BESOI) wafers have the advan-
tage of a cleaner silicon/oxide interface at the BOX than
SIMOX. Oxidation of the seed and handle wafer, followed
by bonding of the two wafers, generates the BESOI. The Si
can be thinned down by the combination of CMP (chemical-
mechanical polish) and etching to the desired film thickness.
2 3 4 5 The relaxed Si1−x Gex can be grown on the BESOI wafers
with thin Si (<100 nm) on the BOX.
The hydrogen ions implanted in Si at a sufficient dose
(1016 to 1017 cm−2 ) can break Si into two pieces after anneal-
ing at 400 $ C to 600 $ C because of the formation of hydrogen
molecules (bubbles) in the implanted region. The way to cut
Si by hydrogen implantation is called “smart cut.” The split-
ting depth depends on the ion energy, and the splitting tem-
perature depends on the ion dose. The combination of smart
cut and wafer bonding can also yield relaxed Si1−x Gex with
the use of one host wafer with oxide and the other handle
wafer with hydrogen-implanted Si1−x Gex [46, 47]. Figure 13
shows one of the procedures for the smart-cut and layer
transfer process to make strained Si on SiGe-on-insulator
(SGOI) material, and Figure 14 is a transmission electron
microscopy (TEM) picture of the resulting relaxed Si1−x Gex
films with strained Si on the top. The as-split SGOI has a
surface roughness of 5–12 nm (rms value); therefore a CMP
process is needed to smooth the surface of the transferred
layer. The relaxation of the Si1−x Gex layer is confirmed by
X-ray diffraction measurement.
3. DEVICE PERFORMANCES
Advanced BiCMOS technology has fully utilized graded-
base SiGe:C heterojunction bipolar transistors, which will
dominate the radiofrequency (up to 10 GHz) and optical
communication (up to 40 Gbit/s) markets. For mainstream
Si technology, to increase the MOSFET speed with the same
lithography feature, the strained Si MOSFET will be used in
the 90-nm technology node and beyond. Si1−x Gex is one of
8 SiGe/Si Heterostructures

H+ H+ H+ H+ H+ H+ H+ Wafer A 3.1. Si/SiGe:C Heterojunction

Bipolar Transistors
oxide Since the first Si/SiGe heterojunction bipolar transistor
Si1-xGex Si1-xGex (HBT) was reported in 1988 [48], tremendous progress of
oxide
Si/SiGe:C HBTs has been achieved, reaching a maximum
oscillation frequency of 210 GHz [1] and a cut-off frequency
Wafer A
of 285 GHz [2], with circuit applications in wireless and opti-
(a). Hydrogen implantation cal communication.
Wafer B
In the NPN bipolar transistor, the collector current is
(c). Splitting annealing
Wafer A controlled by application of a forward bias VBE to the
emitter-base junction [49]. In the forward active region, the
Si1-xGex base-collector junction is reverse biased by VCB , as shown
Si1-xGex in Figure 15. More electrons are injected into the base
oxide
oxide region in HBT than in bipolar junction transistor (BJT)
oxide because of the lowering of the potential barrier &Vn . Note
that the same base doping concentration is assumed in HBT
Wafer B and BJT, and therefore the separation between the Fermi
Wafer B
(d). Polishing level and the valence band edge is the same for HBT and
(b). Hydrophilic bonding at low
BJT. This results in an increase in collector current as com-
temperature
pared with Si BJT with the same base doping. In other
Figure 13. Smart-cut and layer transfer process flow for making words, to have the same barrier &Vn (same collector cur-
strained Si on SiGe-on-insulator material. rent), the HBT can have a heavy base doping, which moves
the conduction band edge in the base upward. The narrow
bandgap of the Si1−x Gex base can have a concentration of
the enabling technologies that can make Si prosperous for up to 2 × 1020 cm−3 [50], which significantly reduces the base
at least two more decades. resistance and hence leads to a high maximum oscillation
In addition to conventional Si devices, because of the frequency, high Early voltage, and a low noise figure, as
heterostructures of Si/Si1−x Gex , some III–V device struc- compared with Si bipolar junction transistors.
tures, such as modulation doped FET and resonant tunnel- A built-in electric field for electrons in the p-type base
ing diodes, can be made with Si. It is possible that these Si region can be obtained with graded Si1−x Gex (shown in
based quantum devices can outperform the original III–V Fig. 16). The electrical field accelerates the electron motion
devices. in the base and thus reduces the base transit time. The
The bandgap of Si (∼1.1 eV) almost makes it impossible cut-off frequency ft can be enhanced. Many studies [51–56]
to have Si-based devices operating at 1.3-"m, 1.5-"m wave- are focused on the optimal Ge profile of SiGe base HBT′
lengths and at the far-infrared region (∼10 "m) for opto- to minimize the base transit time. The narrow base also
electronic and defense applications. However, Si1−x Gex with reduces the base transit time. However, because of the
boron out-diffusion, especially by transient-enhanced diffu-
a small bandgap can absorb the light of 1.3 and 1.5 "m, and
sion (TED) in the fabrication process, the base width is
Ge/Si quantum structures with intraband transition can have
limited. An ultra-high-speed HBT requires a heavily doped
far-infrared absorption. For light emission devices, Si1−x Gex
and extremely narrow base. The carbon incorporation in
p-i-n light-emitting diodes are also demonstrated.

∆ Eg

∆ Vn
base
Strained Si EfE
VBE EfB

VCB
emitter ∆ Vp
Si1-x Gex

Proof's Only
EC

EfC
collector
Si
BOX
Ev
SiGe

Figure 15. Band diagram of typical SiGe HBT. In the forward active
region, the base-emitter junction is forward-biased (VBE ) and the base-
Figure 14. Cross-sectional TEM picture of relaxed SiGe on SOI from collector junction reverse-biased (VCB ). EfC , EfB , and EfC are the Fermi
the smart-cut method. levels in the emitter, the base, and the collector, respectively.
SiGe/Si Heterostructures 9

built-in Field layers grown on either a graded-Ge layer or SOI. The

surface channel device (Fig. 17a) has a single layer of thin
strained Si grown on top of a relaxed buffer layer. This
Ec layer is oxidized to form gate oxide. The buried strained Si-
channel device (Fig. 17b) has a layer of strained Si buried
beneath a thin layer of relaxed SiGe. An additional layer
of strained Si is necessary to form gate oxide on top of
the SiGe, and ideally this additional Si layer should be con-

Proof's Only
Ep
Ev
Figure 16. The compositionally graded Si1−x Gex can build an electrical
field in the base of Si/SiGe HBTs.
the Si1−x Gex base can reduce the boron out-diffusion to a
narrow base with small base resistance and without the par-
asitic barrier in the collector. A low concentration of carbon
atoms (∼< 0!2% = 1020 cm−3 ) is introduced into the base
region to effectively suppress the TED of boron [57]. The
suppressed boron diffusion found in carbon-doped Si and
SiGe is caused by an undersaturation of Si interstitials due to
carbon out-diffusion from the base. However, it is reported
that the addition of a carbon concentration higher than ∼1%
can degrade the electron mobility by a factor of 2 [58].
3.2. Field Effect Transistors
3.2.1. N Channel Metal-Oxide-Semiconductor
Field Effect Transistors
Very high electron mobilities in strained Si layers suggest
a great potential for this material in high-performance N
channel metal-oxide-semiconductor field effect transistors
NMOSFETs. The low defect density buffers and high 14
quality oxide at low temperature are key technologies for
ensuring a mobility advantage in device performance.
The enhancement of effective electron mobility has been
reported for long-channel MOSFETs with both surface and
buried channels [59]. Figure 17 shows schematic diagrams
of these two possible configurations of strained Si channel
NMOSFETs [60]. Both structures have relaxed SiGe buffer
sumed during oxidation. If it is not, the residual sacrificial Si
layer between the gate oxide and the SiGe barrier layer can
act as a parallel conducting channel and strongly affects the
device performance. Depending on the dopant type in the
layers, these structures can also be used for PMOSFETs or
NMOSFETs. The long channel (W = 10 "m ×168 "m) sur-
face and buried-channel NMOSFET devices fabricated on
relaxed Si0!7 Ge0!3 buffer layers showed well-behaved output
characteristics. The effective low-field mobilities for these
device structures [60] are shown in Figure 18. For the surface
channel strained Si device, the effective mobility is enhanced
with a similar dependence on the effective electric field as
compared with a bulk-Si control device. The peak mobility
value is 1000 cm2 /Vs, which shows 80% enhancement over
the Si control device (550 cm2 /Vs). The peak mobility value
of the buried channel device is over 1600 cm2 /Vs, which is
almost 3 times that of the Si control device, but drops rapidly
with increasing effective field. The enhancement of strained
Si NMOSFET mobility becomes less significant, if the low
Ge content buffer is used [60], since the strained Si mobil-
ity increases with increasing strain (more Ge content in the
relaxed buffer layer). Note that buried channel devices with
deep submicron length suffer from degraded threshold volt-
age roll-off and subthreshold characteristics.
Recently, IBM [6] has demonstrated current drive
enhancements in the strained-Si NMOSFET with sub-100-
nm physical gate lengths. Measured effective electron mobil-
ity characteristics are shown in Figure 19. For ∼1.2% strain
(i.e., 28% Ge content in buffer layer), effective electron
1600
VDS=40mV
Buried channel
1200
µeff(cm2/V.s)

Surface channel

(a) (b) Gate

800
Gate

Metal/Play Metal/Play
Source Drain Source Drain
SiO2
SiO2
400
n+ Strained-Si n+ Relaxed Si1-xGex
n+ n+ Control-Si

0.1 0.2 0.3 0.4 0.5

Strained-Si
Eeff(MV/cm)
Relaxed
Si1-xGex Figure 18. Effective low-field mobility as a function of effective field
Relaxed Si1-xGex
for different NMOSFETs at T = 290 K. The surface channel mobility
shows a fairly constant mobility enhancement compared with that of
Figure 17. Device structures for strained Si NMOSFETs with (a) a Si a control-Si device, whereas the buried channel mobility peaks at low
surface channel and (b) a Si buried channel. Adapted with permission fields but decreases rapidly at higher fields. Adapted with permission
from [59], J. Welser et al., IEEE Electron Device Lett. 15, 100 (1994). from [59], J. Welser et al., IEEE Electron Device Lett. 15, 100 (1994).
© 1994, IEEE. © 1994, IEEE.
10 SiGe/Si Heterostructures

mobility enhancement diminishes at high effective electric

800 field. For lower strain in Si (13% Ge content in buffer layer),
hole mobility is slightly degraded compared with the con-
Effective Electron mobility (cm2/Vs)

trol Si. Since the strained SiGe also has high hole mobil-
600 ity (Fig. 8), it is desirable to use a SiGe channel in the
PMOSFETs. With a strained SiGe buried channel below the
strained Si in the buried channel device (Fig. 21), the hole
400 mobility has an enhancement comparable to that of the Si
110% surface channel structure with high strain (28% Ge content
in the buffer layer). The same strained Si structure suitable
Control
200 for NMOSFETs and PMOSFETs makes it possible to apply
Universal mobility
strained Si technology in CMOS circuits.
Strained Si/ Relaxed SiGe 13%
Strained Si/ Relaxed SiGe 28%
Since the compressively strained Ge has a large hole
0
0 500 1000 1500
mobility (Fig. 12), Ge channel PMOSFETs with an effective
Effective Filed (KV/cm)
mobility of 2700 cm2 /Vs have also been reported [5].

Figure 19. NMOSFET effective mobility versus vertical effective field. 3.2.3. Modulation Doped Field
Adapted with permission from [6], K. Rim et al., “IEEE Symposium on Effect Transistors
VLSI Technology Digest, 98,” 2002. © 2002, IEEE.
Carriers can be separated from their parent donor or accep-
tor atoms for suitable band discontinuity. The impurity scat-
mobility at high field was enhanced by 110% over that of tering can be further reduced if a spacer is inserted between
the control Si. Note that to obtain a high current drive in the doped carrier-supply layers and undoped conduction
extremely small devices (∼30 nm), the saturation velocity, in channels. In principle, the modulation doped field effect
addition to the mobility, is also important. transistors (MODFET) can have a much higher mobility than
the MOSFET because of the lack of impurity scattering.
3.2.2. P Channel Metal-Oxide-Semiconductor With the band alignment requirement, NMODFETs have to
Field Effect Transistors use a strained Si channel on relaxed Si1−x Gex [68], whereas
Strained-Si P channel metal-oxide-semiconductor field effect PMODFETs have to use strained Si1−x Gex on relaxed Si or
transistors (PMOSFETs) have been studied [61–67] through strained Ge on relaxed Si1−x Gex [5, 69]. Figure 22 shows
the use of high hole mobility. The tensile strain in silicon
grown on relaxed SiGe buffer raises the light-hole band
and lowers the heavy-hole band. This reduces an intervalley
scattering and increases the low field hole mobility signif- Gate Oxide
icantly. Recently, IBM [6] has demonstrated current drive
enhancements in the strained-Si PMOSFET with sub-100-
Strained Si
nm physical gate lengths. Measured hole mobility charac-

Proof's Only
teristics are shown in Figure 20. For ∼1.2% strain (i.e.,
28% Ge content in the buffer layer), peak hole mobility
Strained Si1-yGey y>x
was enhanced by 45% over that of the control Si. The hole

120 Relaxed Si1-xGex

100 Buffer
Effective Hole mobility (cm2/Vs)

80
strained Si

60
strained Si1-yGey

40 Strained Si/Strained SiGe 13%

oxide
Strained Si/Strained SiGe 28%
Strained Si/Strained SiGe 30%/ Relaxed SiGe 13%
20
Control
relaxed Si1-xGex
Universal mobility
0 y>x
200 400 600 800 1000 2000
Effective Filed (KV/cm)
Figure 21. Schematic diagram of a buried strained-SiGe PMOSFET.
Figure 20. PMOSFET effective mobility versus vertical effective field. Most current flow is in the strained SiGe channel. Adapted with per-
Adapted with permission from [6], K. Rim et al., “IEEE Symposium on mission from [6], K. Rim et al., “IEEE Symposium on VLSI Technology
VLSI Technology Digest, 98,” 2002. © 2002, IEEE. Digest, 98,” 2002. © 2002, IEEE.
SiGe/Si Heterostructures 11

Si-cap
Si1-xGex
n +doping
Si1-xGex
spacer
Si-channel
relaxed
Si1-xGex buffer
Si-substrate Si-substrate
(a)
Figure 22. Typical MODFET structures. (a) NMODFETs with Si-
channel on relaxed-SiGe buffer. (b) PMODFET with SiGe channel and
(c) PMODFET with Ge channel on relaxed-SiGe buffer. Note that the
doping layers and spacers can be located below the bottom of the chan-
nels (after [70]).
these three possible MODFET structures [70]. As in MOS-
FETs, the large defect density of these structures can seri-
ously degrade the device performance.
An electron mobility up to 2700 cm2 /Vs at 300 K for a
sheet carrier density of 7 × 1012 cm−2 in a strained Si chan-
nel NMODFET is reported [71], and a hole mobility of
1880 cm2 /Vs at 300 K for a sheet carrier density of 2!1 ×
1012 cm−2 has been obtained with a pure Ge channel layer
on a relaxed Si0!4 Ge0!6 buffer [71]. All of the available data
on effective electron and hole mobilities for MODFET are
shown in Figure 23 [71–75]. From a comparison of Figure 19
and 23, it is evident the MODFETs have larger enhance-
ment than MOSFETs.
Si-cap
3.3. Optoelectronic Devices
Si-cap
In the last decade, interest in silicon-based optoelectronic
Si1-xGex devices has grown rapidly [76]. The trend of optoelectron-
ics is to integrate both high-performance optoelectronic
p +doping p +doping and electrical devices on the same chips with silicon pro-
Si1-xGex cessing technology. Among silicon-integrable materials, Ge
Si spacer spacer and SiGe are of great importance to the fabrication of
optoelectronic devices because of their optical absorption
Si1-xGex wavelengths.
Ge-channel
channel Many SiGe/Si devices operated in the 1.3–1.5 "m wave-
Si buffer relaxed length range have been reported and demonstrated [77–78].
Si1-xGex buffer In this section, we discuss Si/SiGe photodetectors, light-
emitting diodes, and heterojunction phototransistors.
Si-substrate
3.3.1. Absorption of SiGe
(b) (c) Because of the large absorption length (∼16"m) of Si at
820 nm [79] and the forbidden absorption at 1300 and
1550 nm, Si-based photodetectors have limited detection
efficiency and wavelength range. Not only can the incorpora-
tion of Ge into Si increase the cutoff wavelength (Fig. 6); it
can also enhance the absorption efficiency (small absorption
length). The strained Ge could have an absorption length
of 0.1 "m or less at a wavelength of 820 nm. Figure 24
shows the absorption length at 820, 1300, and 1550 nm ver-
sus Ge mole fraction. The absorption length decreases as the
Ge mole fraction increases. For the large Ge fraction, the
shadowed areas indicate the uncertainty of the estimation.
The incorporation of strained Ge/SiGe into optoelectronic
devices makes devices particularly useful over the important
fiber optic communications wavelengths.
3.3.2. Photodetectors
The figures of merit for light detection are high effi-
ciency, high responsivity, low noise, low dark currents,
and fast response. Previous studies have focused on
metal-semiconductor-metal (MSM) diodes and p-i-n diodes.

103
IBM (A)
y=0.3 DC
x=1 y=0.7 1550 nm
102
Effective Mobolity (cm2/Vs)

Absorption length(µm)

IBM (B) 1300 nm

CNET
y=0.3 x=1 y=0.7
DC 1
103 10
x=1 y=0.7

Proof's Only
820 nm
IBM (B)
x=0.8 y=0.3 100

IBM (A)
x=0.8 y=0.3
10–1
Hole mobility
strained SiGe
Electron mobility
2
10 10–2
0.1 1 0.0 0.2 0.4 0.6 0.8 1.0
Eeff (MV/cm) Ge mole fraction

Figure 23. Available experimental data [71–75] at 300 K for effective
electron and hole mobility in MODFET. A denotes modulation doping
above a strained Si channel, B denotes a doping supply layer below a
strained silicon channel, x is the Ge fraction in the channel, and y is the
Ge fraction in the buffer layers. DC, DaimlerChrysler Research Center;
CNET; France Telecom.
Figure 24. The absorption length at 820, 1300, and 1550 nm versus
Ge mole fraction. The absorption length decreases as the Ge mole
fraction increases. For the large Ge fraction, the shadowed areas indi-
cate the uncertainty of the estimation. Reprinted with permission from
[16], B.-C. Hsu et al., “International Electron Device Meeting,” 2002,
pp. 91–94. © 2002, IEEE.
12
In 1992, a metal-semiconductor-metal (MSM) diodes was
reported by Splett et al. [80]. The 17 measured respon-
sivity at 1.3 "m is 0.2 A/W over a 1-mm detector length
with 500 pA/"m2 dark current at 5-V bias. In 1996, Huang
et al. reported an epitaxial SiGeC/Si photodetector with a
response in the 1.3–1.55-"m wavelength range [77]. The
active absorption layer of the p-i-n photodiode consists of
a pseudomorphic SiGeC alloy grown on a Si substrate with
a Ge content of 55% and a thickness of 80 nm. In 2001, a
p-i-n Ge on Si photodetector was reported by Masini et al.
[78]. The photodiodes exhibit short-circuit responsivities of
0.3 and 0.2 A/W at 1.3 and 1.55 "m, respectively, reverse
dark currents of 20 mA/cm2 , and response times of 800 ps.
In 1999, photodetectors and light-emitting diodes for
1.1-"m wavelength have been demonstrated with metal-
oxide-silicon (MOS) tunneling structures on both n-type
and p-type silicon substrates [81–84]. The ultrathin thickness
(<3 nm) of thermal oxide is required in these novel pho-
todetectors to provide sufficiently large tunneling probabil-
ity. As biased in inversion region, the tunneling diode works
in the deep depletion region with the soft pinning of oxide
voltage, instead of pinning of surface potential, which is very
different from the conventional MOS diode with thick oxide.
The Ge MOS detector can operate at 1.3 and 1.55 "m with
high responsivity [85]. To avoid material degradation such
as strain relaxation and Ge out-diffusion, low-temperature
liquid phase deposition (LPD) oxide is introduced [86].
A MOS Ge quantum dot photodetector is demonstrated
[16]. The photodetector has responsivities of 130, 0.16, and
0.08 mA/W at detection wavelengths of 820 nm, 1300 nm,
and 1550 nm, respectively. The dark current is extremely
low (0.06 mA/cm2 ). Si/Ge quantum dots are prepared by
ultra-high-vacuum chemical vapor deposition (UHVCVD)
on p-type Si (001) substrates. The structure is shown in
Figure 25. With the careful design of intraband transition,
the long-wavelength infrared (6–10 "m) can also be detected
with the same devices.
3.3.3. Light-Emitting Diodes
Two different Si light emitters have been reported. A narrow-
band infrared emitter at 1160 nm was implemented with a
pn junction under forward bias with an external quantum
Proof's Only
Figure 25. The MOS detector structure with five layers of Ge quantum
dots.
SiGe/Si Heterostructures
efficiency of ∼10−4 [87]. A broad-band (450–850 nm) visible-
light emitter was also realized with an avalanche pn diode
with an external quantum efficiency of ∼10−8 [87] and ∼10−6
[88]. Recently, the band-edge (1.1 "m) electroluminescence
(EL) of a MOS tunneling light-emitting diode has also been
reported [83]. Because of the indirect bandgap of Si, addi-
tional momentum is required for the light emission pro-
cess. The phonon provides the additional momentum in
bulk Si and bulk SiGe [89]. In the MOS structure, the
interface/surface roughness can seriously affect the carrier
transport in the inversion layer [90]. This indicates that the
interface/surface roughness can scatter the carrier and can
change the carrier momentum. Therefore, the rough oxide
can enhance the emission efficiency of MOS light emitting
diodes [91].
The addition of Si1−x Gex to p-i-n diodes can increase
the emission wavelength. Both 1.3-"m [18] and 1.5-"m [19]
emissions with Si1−x Gex /Si quantum wells and Ge/Si quan-
tum dots, respectively, are demonstrated at room temper-
ature, and erbium-doped Si1−x Gex can also have 1.5-"m
emission [92]. However, MOS diodes with Si1−x Gex or Ge
quantum dots are not reported to have long-wavelength
emission so far.
3.3.4. Heterojunction Phototransistors
With high gain and low noise, the phototransistor can be
used in the front end of an optical receiver. The Si1−x Gex /Si
multiple quantum well heterojunction phototransistor with
an ultrahigh responsivity of 1.47 A/W and a bandwidth of
>1.25 GHz at a wavelength of 850 nm has been reported at
an operation voltage as low as ≤1.5 V [13]. The responsivity
at 1310 nm is 0.15 A/W. The multiple quantum wells in the
collectors can enhance the photon absorption and increase
the cutoff wavelength. The current gain of the transistors
can further amplify the optical current. Si/Si1−x Gex quantum
well phototransistors with far-infrared (6–20 "m) response
with low leakage current and high gain were also proposed
[93].
4. FABRICATION TECHNOLOGIES
4.1. Growth of Si1−x Gex Films
Si1−x Gex can be epitaxially grown by chemical vapor deposi-
tion (CVD) and molecular beam epitaxy (MBE). Depending
on the growth pressures, CVD has some variations: APCVD
(atmospheric pressure), rapid thermal CVD (RTCVD, sev-
eral torr with lamp heating), low-pressure CVD (LPCVD,
several tenths of a torr), and ultrahigh vacuum pressure
CVD (UHV/CVD). UHV/CVD [94] has a growth pressure
of 10−2 to 10−3 torr and a base pressure of UHV (∼10−9
torr). The designation UHV is sometimes confusing and
only indicates the base pressure of the reactor chamber, not
the growth pressure. The wafer temperature can be obtained
by lamp heating or thermal equilibrium furnaces. For lamp
heating, the wafer temperature can rise and fall very rapidly
(on the order of 10 s), and is often called “rapid thermal
CVD” [95]. The chamber used for RTCVD is often made
of quartz to avoid contamination during growth. The quartz
chamber does not absorb as much emission from the lamps
SiGe/Si Heterostructures
as Si wafers. A cold-wall RTCVD can be obtained, whereas
a quartz tube with hot walls is used in the furnace-type reac-
tor, such as that used for UHV/CVD. Because of the config-
uration of heating lamps, RTCVD can process only a single
wafer at a time, whereas a furnace-type reactor such as that
used for UHV/CVD can process a batch of wafers (more
than 20 wafers). Silane (SiH4 ) and dichlorosilane (DCS) are
the common precursors of Si, and germane (GeH4 ) is the
precursor of Ge. Phosphine (PH3 ) is used for n-type dop-
ing, and diborane (B2 H6 ) is for p-type doping. Both RTCVD
and UHV/CVD are used in semiconductor manufacturing
laboratories as well as research laboratories.
MBE is a physical deposition system with a stainless
chamber. The base pressure and growth pressure are about
10−11 and 10−9 torr, respectively. The electron beams are
used to heat source materials such as Si and Ge, and the Si
and Ge atoms are evaporated on Si substrates. The chamber
is cold and substrates are heated by a local heater. Because
of the difficulty of using large-diameter wafers and some
process issues, MBE is used in research laboratories, and
HBTs with ideal base currents are grown by MBE [96] after
CVD.
4.2. Metal Contacts
As the microelectronics industry moves into the era of
deep submicron devices, metallization has become the
main performance-limiting factor. Metal silicides have
been widely used to reduce the contact resistance of the
source/drain of microelectronic devices. The self-aligned sili-
cidation technique has become a crucial part of recent ultra-
high-speed silicon device technologies [97]. TiSi2 is currently
the most commonly used silicide in the IC industry. In the
deep submicron regime, a linewidth dependence of sheet
resistance was observed for TiSi2 [98, 99]. CoSi2 has been
introduced to replace TiSi2 in sub-quarter-micron technol-
ogy. However, its use in sub-0.1-micron devices is in doubt
unless a raised source/drain scheme becomes feasible. NiSi
is the only silicide left with resistivity comparable to that
of TiSi2 and CoSi2 . On the other hand, intensive efforts
have been made to extend IC devices to other substrate
frames, such as Si-Ge. Metal germanosilicide/Si1−x Gex /Si
heterostructures are promising for use in devices such as the
heterojunction bipolar transistor and infrared detectors with
high cutoff wavelengths [100, 101].
Metal germanosilicides may be used for making metal-
lic contacts with Si1−x Gex alloys, and knowledge about the
formation and stability of thin metal germanosilicide films
is essential for such applications. The thermally induced
metal/Si1−x Gex reaction has previously been studied for
many metals. Various degrees of germanium segregation
and/or the formation of segregated layered structures were
observed in the reactions of these metal/Si1−x Gex systems.
The difference in heats of formation of silicide and ger-
manide offers the driving force for the segregation of
Ge-rich Si-Ge alloy [102]. The phase formation paths were
found to depend strongly on the composition of substrates.
By extension from silicon to Si-Ge devices, the contact mate-
rials considered for Si-Ge devices have been focused on Ti,
Co, and Ni contacts.
13
4.2.1. Co/Si-Ge System
Direct deposition of metal thin films on Si1−x Gex in a self-
aligned silicide process would be an efficient technique and
would take advantage of established technologies. However,
the major difficulties in using Co as a contact material for
Si1−x Gex appear to be the preferential reaction of Co with
Si and the high consumption ratio of the Si to Co to form
CoSi2 . The undesirable characteristics lead to Ge segre-
gation, deterioration of the Si1−x Gex layer, degradation of
junction integrity, and film agglomeration at low tempera-
tures, resulting in poor thermal stability and high-resistivity
contacts [103–105]. In addition, it has been demonstrated
that CoSi2 is formed at much higher temperatures on a
Si1−x Gex layer than that on Si, owing to Ge expelled from
the Co-Si-Ge compound, which blocks the Co diffusion
paths, slowing down the reaction [106–108]. Successful for-
mation of good quality CoSi2 on epitaxial Si0!7 Ge0!3 in the
presence of a sacrificial a-Si layer has been achieved. CoSi2
was previously found to form at a lower temperature on a-Si
with a smoother interface than that on single-crystal Si [109].
For convenience, the two sets of samples Co(15 nm)/
Si0!7 Ge0!3 and Co(15 nm)/a-Si(50 nm)/Si0!7 Ge0!3 are desig-
nated as samples A and B, respectively. Five hundred-
nanometer-thick Si0!7 Ge0!3 and 1-m"m-thick strained layers
of Siy Ge1−y (y varies from 1 to 0.7) were grown on (001)Si
wafers at 550 $ C by MBE. A 50-nm-thick sacrificial a-Si
layer was deposited on a Si0!7 Ge0!3 substrate followed by
the deposition of a 15-nm-thick Co thin film without break-
ing the vacuum at room temperature. Figure 26 shows the
sheet resistance data of the two sets of samples after dif-
ferent heat treatments. For samples annealed at 600 $ C,
the sheet resistance of samples B is much lower than
that of samples A. The low resistance is attributed to the
early formation of low-resistivity CoSi2 , which is consistent
with the X-ray diffraction data. In contrast, CoSi2 was not
detected in samples A annealed at a temperature as high as
800 $ C. The further substantial increase in sheet resistance
for Co(15 nm)/Si0!7 Ge0!3 samples after 800 $ C annealing,
Proof's Only
Figure 26. Sheet resistance versus annealing temperature curves for
samples A and B after annealing at 500–1000 $ C for 30 s by RTA.
Reprinted with permission from [109], W. W. Wu et al., Appl. Phys. Lett.
81, 820 (2002). © 2002, American Institute of Physics.
14 SiGe/Si Heterostructures

as shown in Figure 26, is correlated to the agglomeration

of Co(Si1−x Gex ). Figure 27 is a plane-view TEM micro-
graph showing the formation of Co(Si1−x Gex ) islands in a
Co(15 nm)/Si0!7 Ge0!3 sample annealed at 800 $ C. On the
other hand, for the Co(15 nm)/a-Si(50 nm)/Si0!7 Ge0!3 sam-
ples, the formation of CoSi2 was completed after 700 $ C
annealing. The sheet resistance maintained the same low
level for samples B after annealing at 700–900 $ C. In 900 $ C
annealed samples, the silicide films were found to be contin-
uous with the smooth interface with Si0!7 Ge0!3 , as revealed
Proof's Only
by plane-view TEM and XTEM images shown in Figure 28.
No Ge segregation was detected from the analysis of TEM
direct images and electron diffraction patterns. In contrast
with samples B, rough interface and Ge segregation in sam-
ples A are evident. An example is shown in Figure 29.
Previous study showed that the retardation of the silici-
dation process on Si1−x Gex is related to a higher effective
Ge concentration at the reaction front, therefore causing
an increase in the interface energy. The expelled and seg-
regated Ge tends to diffuse to the surface and interface
of the silicide layer [104, 105]. These Ge atoms can dec-
orate the grain boundaries, resulting in an increase in the
grain boundary energy, which makes the silicide film more
prone to agglomeration. On the other hand, the sacrificial
a-Si layer is shown to improve the interfacial roughness
and thermal stability of a CoSi2 film grown on Si0!7 Ge0!3 .
The increased uniformity of the silicide/Si0!7 Ge0!3 interface
is speculated to result from small-grained CoSi2 . The aver-
age grain size is smaller for silicides formed on a-Si than
that on single-crystal Si and poly-Si in samples subjected to
Figure 28. (a) Plane-view and (b) cross-sectional TEM images of
the same heat treatment [110]. The results indicated that the
Co(15 nm)/a-Si(50 nm)/Si0!7 Ge0!3 samples after annealing at 900 $ C for
reaction between Co thin films and a-Si incurs the formation 30 s by RTA. Reprinted with permission from [109], W. W. Wu et al.,
of small-grained CoSi2 , which in turn enhances the mor- Appl. Phys. Lett. 81, 820 (2002). © 2002, American Institute of Physics.
phological stability of CoSi2 . In addition, the formation of
thermally stable CoSi2 leads to a low sheet resistance value.
forms first on heating of Ti on Si above 500 $ C, and addi-
4.2.2. Ti/Si-Ge System tional heating above 700 $ C is needed to transform C49 into
the low-resistivity C54-TiSi2 . However, in the Ti/Si1−x Gex
Titanium disilicide has been widely used for contacts to Si in
system, Ge segregation was observed near the C54 phase
microelectronics devices. Its use is complicated by the exis-
formation temperature [111]. In addition, the resistivity
tence of two crystalline phases. The high-resistivity C49-TiSi2
of C54-Ti(Si1−z Gez )2 forms on Si1−x Gex layer is higher
than that of C54-TiSi2 . The appearance and agglomeration
temperature of low-resistivity C54-Ti(Si1−z Gez %2 were both
found to decrease with the Ge concentration [111].

Figure 27. Plane-view TEM image of a Co(15 nm)/Si0!7 Ge0!3 sample

after annealing at 800 $ C for 30 s by RTA. Reprinted with permission
from [109], W. W. Wu et al., Appl. Phys. Lett. 81, 820 (2002). © 2002, Figure 29. Cross-sectional TEM image of Co(15 nm)/Si0!7 Ge0!3 samples
American Institute of Physics. after annealing at 900 $ C for 30 s by RTA.
SiGe/Si Heterostructures 15

An amorphous Si was also successfully used to decrease

the formation temperature of low-resistivity C54-TiSi2 and
alleviate the formation of islands as well as the segregation
of Ge. For the Ti/a-Si/Si1−x Gex system, the thicknesses of Ti
and amorphous Si were selected to be 15 and 30 nm, respec-
tively. Figure 30 shows an XTEM image of a Ti/Si0!7 Ge0!3
sample annealed at 900 $ C, revealing the formation of C54-
Ti(Si1−z Gez )2 islands and Ge segregation. An amorphous Si
was used to alleviate the formation of islands as well as the
segregation of Ge. The selection of the thickness ratio of Ti
and a-Si was such that the a-Si was completely consumed in
forming C54-TiSi2 . If the a-Si was too thin, Ti would start
to react with the Si1−x Gex layer and accompanying prob-
lems in forming higher-resistivity Ti(Si1−x Gex ) compound
became troublesome [102]. Ge segregation [111], a rough
interface [112], and strain relaxation of the Si1−x Gex layer
are expected to occur [113].
GIXRD spectra of Ti(15 nm)/a-Si(30 nm)/Si0!7 Ge0!3 Figure 31. Resistivity versus annealing temperature curves for samples
samples revealed that low-resistivity C54-TiSi2 was the A and B after annealing at 500–1000 $ C for 30 s by RTA.
dominant silicide phase above 650 $ C. The formation tem-
perature of C54-TiSi2 was lowered by about 100 $ C in
samples with a sacrificial a-Si interlayer compared with films were also found to be continuous with the smooth
that of the Ti/Si0!7 Ge0!3 system [111]. Figure 31 shows the interface with Si0!7 Ge0!3 , as shown in Figure 32. As a result,
resistivity curves of the Ti(30)nm/Si0!7 Ge0!3 and Ti(15 nm)/a- a sacrificial a-Si layer was found to decrease the formation
Si(30 nm)/Si0!7 Ge0!3 samples (samples A and B) after anneal- temperature of C54-TiSi2 , prevent Ge segregation, lower the
ing at different temperatures. For samples annealed at resistivity of silicide, and improve the morphological stabil-
700 $ C, the resistivity of samples B is 23 much lower than ity of C54-TiSi2 on the Si0!7 Ge0!3 layer. If the a-Si was too
that of samples A. It resulted from the formation of low- thin, Ti would react with the Si0!7 Ge0!3 layer significantly and
resistivity C54-TiSi2 at low temperature. On the other hand, result in a rough interface.
for samples A, as the annealing temperature was increased
to 800 $ C, a sharp drop in resistivity occurred. In samples 4.2.3. Ni/Si-Ge System
B, the temperature range of low-resistivity C54-TiSi2 was Low-resistivity NiSi is currently one of the most promising
extended to 700–900 $ C. From both resistivity and TEM silicides to replace TiSi2 for the self-aligned technology of
data, it was concluded that the resistivity of C54-TiSi2 in ULSI, owing to its favorable properties low resistivity, low
samples B is lower than that of C54-Ti(Si1−z Gez )2 in sam- silicon consumption, low processing temperature, and rela-
ples A. The magnitude of such differences will be affected tive insensitivity to the linewidth of the silicide.
by the homogeneity of the microstructures and will depend For the Ni/Si0!7 Ge0!3 system, Ge tended to be less reactive
specifically upon the grain size [110]. On the other hand, with Ni than with of Si. Moreover, Ge was found to segre-
with higher solute concentration, the electronic structure or gate to grain boundaries in 600 $ C annealed samples, and
phonon spectrum of the alloy will start to suffer from pertur- Ni(Si0!9 Ge0!1 ) islands were found to form in 700 $ C annealed
bation, and then the resistivity is expected to increase. For samples. In the XTEM image observation, the Ge segrega-
Ti(15 nm)/a-Si(30 nm)/Si0!7 Ge0!3 samples, the a-Si was com- tion toward the grain boundary was evident. An example is
pletely consumed in forming C54-TiSi2 , and the phase pos- shown in Figure 33. Ni(Si0!9 Ge0!1 ) islands were observed to
sesses lower resistivity than ternary C54-Ti(Si1−z Gez )2 phase. form in 700 $ C annealed samples [114].
In addition, no Ge segregation was detected. The silicide

Proof's Only
Figure 30. Cross-sectional TEM image of Ti(30 nm)/Si0!7 Ge0!3 samples Figure 32. Cross-sectional TEM image of Ti(15 nm)/a-Si(30
after annealing at 900 $ C for 30 s by RTA. nm)/Si0!7 Ge0!3 samples after annealing at 900 $ C for 30 s by RTA.
16
Figure 33. Cross-sectional TEM image of a Ni(30 nm)/Si0!7 Ge0!3 sample
after annealing at 700 $ C for 30 s by RTA.
The scheme of an interposing a-Si layer was also
attempted to overcome the detrimental effects of Ge seg-
regation as well as island formation in Ni/Si-Ge systems.
The thicknesses of Ni and amorphous Si were selected to be
15 and 27 nm, respectively. GIXRD spectra for Ni(15 nm)/
a-Si(27 nm)/Si0!7 Ge0!3 samples annealed at 300–700 $ C indi-
cated that low-resistivity NiSi was the only phase present in
all samples annealed above 500 $ C.
Figure 34 shows the sheet resistance data for Ni(30 nm)/
Si0!7 Ge0!3 and Ni(15 nm)/a-Si(27 nm)/Si0!7 Ge0!3 samples
(samples C and D). After annealing at 400 $ C, low-resistivity
NiSi phase was formed in both sets of samples. The apparent
increase in sheet resistance for Ni(30 nm)/Si0!7 Ge0!3 samples
after annealing at 700 $ C results from the formation of the
island structure of Ni(Si0!9 Ge0!1 ). On the other hand, even
after annealing at 800 $ C, the sheet resistance remained at
the same low level for the Ni(15 nm)/a-Si(27 nm)/Si0!7 Ge0!3
samples. Furthermore, the sacrificial a-Si layer was also seen
to improve the interface roughness and thermal stability of
NiSi film grown on Si0!7 Ge0!3 from XTEM micrographs. In
addition, no Ge segregation was observed. An example is
shown in Figure 35. In the Ni thin films on the Si system,
Figure 34. Sheet resistance versus annealing temperature curves for
Ni(30 nm)/Si0!7 Ge0!3 and Ni(15 nm)/a-Si(27 nm)/Si0!7 Ge0!3 samples after
annealing at 300–800 $ C for 30 s by RTA.
SiGe/Si Heterostructures
Proof's Only
Figure 35. Cross-sectional TEM image of Ni(15 nm)/a-Si(27 nm)/
Si0!7 Ge0!3 samples after annealing at 800 $ C for 30 s by RTA.
NiSi2 is normally formed at 750 $ C. The extraordinary sta-
bility of NiSi on Si0!7 Ge0!3 with a sacrificial a-Si layer is likely
due to the high consumption ratio of the Si to Ni to form
NiSi2 , which requires the excess Ni atoms to react directly
with the Si1−x Gex layer. Ge was then expelled from the Ni-
Si-Ge compound and slowed down the reaction. The block-
ing of Ni diffusion paths by Ge atoms may also slow down
the reaction and result in a delay of the formation of NiSi2 .
The mechanism is similar to that of the formation of CoSi2
on a Si1−x Gex layer. In contrast, if the a-Si is too thin, as in
Ni(15 nm)/a-Si(22 nm)/Si0!7 Ge0!3 samples, a rough interface
is formed. The results indicate that a sacrificial a-Si layer
with appropriate thickness works beneficially for Ni contacts
on Si-Ge.
GLOSSARY
CMP Chemical-mechanical polish. A chemical-mechanical
method utilized to eliminate the surface roughness of a sam-
ple. This method is commonly used in ULSI processes.
CVD Chemical vapor deposition. A method utilizing
chemical gas to deposit film on substrates.
Dislocation A kind of line defect due to the lattice misfit
between SiGe and Si. There are two segments. The segment
parallel to the Si/SiGe interface is called “misfit disloca-
tion,” and the segment propagating to the surface is called
“threading dislocation.”
HBT Heterojunction bipolar transistors. The narrow
bandgap base in the bipolar transistor to enhance the device
performance.
Metal germanosilicide A compound of metal, Si and Ge.
SGOI Strained Si-on-SiGe-on-insulator. Introducing
strained Si to the silicon-on-insulator (SOI) technology,
which provides high-performance CMOS circuits due to
combination of carrier mobility enhancement in strained Si
with the advantage of SOI device/circuit.
Silicidation process The process used to form silicide.
Strained Si FET Strained Si field effect transistors. The
tensile strained Si has higher carrier mobility than conven-
tional Si. The new type of device can give larger current
drive in VLSI circuits.
SiGe/Si Heterostructures
Universal mobility The carrier mobility in the field effect
transistor depending only on effective transverse electrical
field regardless of the doping concentration of the channel.
ACKNOWLEDGMENTS
The help of S. T. Chang (Department of Electrical Engi-
neering, National Taiwan University, Taiwan) and W. W.
Wu (Department of Materials Science and Engineering,
National Tsing Hua University, Taiwan) in manuscript
preparation are gratefully appreciated. The work on the
composite quantum dots by Dr. P. S. Chen, ERSO/ITRI,
Taiwan, is highly appreciated.
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