Item Text Option Text 1

In enhancement mode, device is in which conducting

condition
In CMOS Static power dissipation is low
In CMOS noise margin is zero
In MOS transistors what is used for their gate. metal

Inversion layer in enhancement mode consists of positive charge

Depletion mode MOSFETs are more commonly switches

used as
In Nchannel MOSFET,what is constant channel length
When clock signal will zero then parasitic charge
capacitance will
In CMOS Wp is 2Wn
Complementary CMOS of inverter source is source
connected to its
in Inverter VTC largest slope in transition region is zero

VLSI technology use what to form integrated transistor

circuit
Which has high input resistance NMOS
CMOS inverter has how many regions of three
operation
CMOS is what type of switching device bad
Drain current depends on Vg
CMOS inverter the output impedance is low
Medium scale integration has how many gates 10

What is used in logic design of VLSI LIFO

For depletion mode transistor gate is connected source
to
The most basic form of behavioral modeling in IF
VHDL is
SIGNAL x : STD_LOGIC; In this statement x is variable
Which of the following is equivalent division by 2 SRL
operator?
The main problem with behavioral modeling is Asncronous delay

Which of the following is default delay in VHDL Inertial

Transport delay is a kind of delay Synthesis
In which part of the VHDL code, generics are Package
declared?
In most synthesis tools, only generics of which Integer
type are supported
Which function is used to map a generic on Portmap()
design?
Generics in VHDL can be treated as global variable
Guarded block has an extra expression of what Conditional
type
Which of the following statement is used to block
describe regular structures?
Which of the following is not a way of partitioning Component
a design
In which part of the VHDL code, components Library
must be declared?
How many ways are there in VHDL to map the 1
components?
Which of the following is not a type of VHDL behavioral
modeling?
Which of the following statement is used in portmap()
structural modeling?
What is the basic unit of behavioral description? Structure

Delays are generally ignored in which assignments Concurrent

statements.
Which of the following is a keyword used for IF
conditional assignment?
Why is SRAM more preferably than DRAM low-cost

What is approximate data access time of SRAM? 4ns

How many MOSFETs are required for typical SRAM 2
Which of the following is an SRAM? 1T-RAM
Which of the following can access data even when Non-volatile SRAM
the power supply is lost?
Which of the following can easily convert to a non- SRAM
volatile memory?
Which of the following memory technology is SRAM
highly denser
The time taken to transfer a word of data to or Access time
from the memory is called as
Which is the storage element in DRAM inductor
The reason for the cells to lose their state over tim The lower voltage levels
o reduce the number of external connections De-multipexer
reqiured, we make use of
Which one of the following is a storage element in capacitor
SRAM
Which is the very basic technique of refreshing DRAburst refresh
How is the refresh rate calculated? by refresh time

Which is the commonly used refresh rate 125 microseconds

What is the purpose of the address bus? to provide data to and
from the chip

The cells in a row are connected to a common line Work line

called
The cells in each column are connected to …………. Sense line

The word line is driven by……… Chip Select

The time required to store and /or retrieve a Cycle time
particular data bit in the memory array is called….

What is the Process for Refreshing the cell after reading every cell

What is the meaning of term dynamic stores data when power is

removed
A _______ is used to restore the contents of the Sense amplifier
cells
Floating output is observed in which type of fault stuck-at

Single stuck at fault is Technology dependent

In a VLSI design which of the following is correct error-fault-failure

sequence of occurance
The ease with which the controller establishes Observability
specific signal value at each node by setting input
values is known as
Which is easier mathod to test Random sequence
generators
what is long form of JTAG Joint Test Acess Group

Built in self test technique used for self testing

out of the following is not the TAP signal TRST
Which is correct TAP controller sequence Capture-Pause-Shift-
Update
TAP controller stands for Test Access Port controller
Observability is the process of  checking all possible inputs

what is the easiest way to reduce test time by using the whole circuit
as a single system

Scan Path approch is also known as Clock scan

Gated clocks should be avoided while design VLSI It affects Controllabiltity
based system because
Design for testability is an essential process for 30%
good design. ______ of the area is dedicated for
testability
Test vectors in sensitized path-based testing is after designing
generated
 Asynchronous logic is driven by clock
Which circuits are faster? synchronous circuits

Automatic test pattern generators depend on map design

The fast rise and fall times give cross-talk they are in close proximity
problems if

The depletion N channel MOSFET has how many 4

terminals
In CMOS Static power dissipation is low
In CMOS noise margin is zero
Source and drain in nMOS device are isolatedby one doide

Inversion layer in enhancement mode consists of positive charge

Depletion mode MOSFETs are more commonly switches

used as
In Nchannel MOSFET,what is constant length
When clock signal will zero then parasitic charge
capacitance
In CMOS Width of channel of pmos is 2Wn
Complementary CMOS of inverter source is source
connected to its
in Inverter VTC largest slope in transition region is zero

VLSI technology use what to form integrated transistor

circuit
Which has high input resistance NMOS
CMOS inverter has how many regions of three
operation
CMOS is what type of switching device bad
Mobility depends on supply voltage
CMOS inverter the output impedance is low
Medium scale integration has how many gates 10

What is used in logic design of VLSI LIFO

For depletion mode transistor gate is connected source
to
In N channel MOSFET what is constant Length
CMOS inverter has how many regions of Three
operation
Medium scale integration has how many gates 10
In CMOS inverter source is connected to its Source
In CMOS Width of channel of pmos is 2Wn
CMOS is what type of switching device Bad
In CMOS noise margin is One
VLSI technology use what component or device to Transistors
form integrated circuit
The process used for implementation of Sequential process
sequential logic in VHDL is called
How many types of resets are there in hardware One
design
What is the state value of CLEAR input Reset
What is stimuli in test bench waveform Input values
In FSM diagram what does circle represent? Change of state
What kind of output does mealy machine produce Asynchronous

Which among the following are identical in Mealy Combinational output

& Moore machines signal
Which among the following constraints are State variable and clock
involved in a state-machine description

Why is SRAM more preferably than DRAM Low-cost

Which of the following is an SRAM? 2T

Which of the following can easily convert to a non- SRAM
volatile memory?
Which one of the following is a storage element in Capacitor
SRAM
Which is the very basic technique of refreshing Burst refresh
DRAM?
Which is the storage element in DRAM Inductor
The time required to store and retrieve a Cycle time
particular data bit in the memory array is called as
What is the meaning of term dynamic Stores data when power is
removed
Which is the type of clock distribution H tree
Why do we use buffers in a clock distribution To reduce the delay

The propagation delay of a long interconnection Making the line thinner

line can be reduced by

One of the main approaches to handle the clock Balance the delays of the
skew problem is critical paths in the circuit

Which of the following statements is true for Global skew is less

clock networks important than local skew

Which clock topology is better for distributing A pure H-tree topology

clock signals to a large number of arbitrary points
in a chip?
In floorplanning, placement and routing are called Front end tool
as
In floorplanning, which phase/s play/s a crucial Placement
role in minimizing the ASIC area and the
interconnection density?
Maze routing is also known as Viterbi’s algorithm

Increase in the physical distance of H-tree the Decreases

skew rate also
In signal integrity, which noise occur due to Power Noise
impedance mismatch
Maze routing is used to determine Shortest Path
What is long form of JTAG Joint Text Apply Group

Built in self test technique used for Self testing

TAP controller stands for Test Action Port controller

Multiplexer can be used to make Logic gates

Out of the following which is not the TAP signal TRST

The ripple carry adder is a Serial Adder

High-speed Carry Look-ahead Adders are used in Capacitor
FPGA uses program technology called as EEPROM
What distinguishes the look-ahead-carry adder It is slower than the ripple-
carry adder
What are the two types of basic adder circuits Sum and carry

How many shift registers are used in a 4 bit serial 4

adder
 What are carry generate combinations If all the input are same
then a carry is generated

Stick diagrams are those which convey layer Thickness

information through
Which color is used for polysilicon Blue
Design rules does not specify Linewidths
Which gives scalable design rules Lambda rules
Which model is used for scaling Cconstant electric scaling

As the channel length is reduced in a MOS Increased

transistor, depletion region width must be
The size of a transistor is usually defined in terms Feature size
of its
Physical verification tools in design process Circuit extractors
include
Simulators are available for Transistor level logic
Which is not a layout EDA tool Xilinx
Which layer is used for power and signal lines Metal
Which is important during the design phase Circuit simulator
Speed power product is measured as the product gate switching delay and
of gate power dissipation

nMOS devices are formed in p-type substrate of high

doping level

Source and drain in nMOS device are isolated by a single diode

In depletion mode, source and drain are insulating channel

connected by
In enhancement mode, device is in which conducting
condition
MOS transistor structure is symmetrical
Inversion layer in enhancement mode consists of positive carriers
excess of
As source drain voltage increases, channel depth increases

In MOS transistor which material is used in the metal

gate
Gate region consists of conducting layer
Electrical charge flow from source to drain
If the gate is given sufficiently large charge, drain region
electrons will be attracted to
In VLSI design what is used to form intrgrated transistors
circuit
Medium scale intrgration has ten logic gates
The difficulty in achieving high doping error in concentration
concentration leads to
What is used in VLSI Design LIFO
Which provides higher integration density? transistor-transistor logic

Switch logic is based on pass transistors

Power dissipation in Switch logic is less

Pass transistor can be driven through --------------- one
pass transistors
Switch logic is designed using complementary switches
Gate logic is also called as transistor logic
As the number of inputs increases, the NAND gate increases
delay
In CMOS NAND gate, p transistors are connected series
in
Which Gate is faster AND
The Channel width of PMOS is how many times 2 to 3
that of NMOS
CMOS inverter has how many regions of two
operation
In the region where CMOS inverter exhibits gain, linear
the two transistors are in ------------------- region

If both the transistors are in saturation, in CMOS current source

inverter then they act as
In CMOS inverter, transistor is a switch having infinite on resistance

CMOS inverter has ______ output impedance. low

What is the input impedance of CMOS inverter high

In inverter during logic 1 to 0 transition, pull up transistor

capacitance discharges at
The area of CMOS inverter is proportional to area of n device

Dynamic power dissipation can be given as C x Vdd x f

Which has better noise margins NMOS
A latch is SET if  the output Q is ACTIVE

A VHDL construct that maps the name of a port in port entity

a component to the name of a port, variable, or
signal in a design entity that uses the component
is called ____
Output values of Moore type FSM are determined  Input values
by its ________
In FSM diagram what does circle represent Change of state
State transition happens _______ in every clock Once
cycle.
Statements inside of a VHDL PROCESS are ____ sequential

The amount of time required from an active level setup time

on one input (such as CLR) until the active edge of
the clock pulse is ____
Which among the following constraint/s is/are State variable & clock
involved in a state-machine description

How many flip flops are necessary to design a 2

state machine with 25 states
If the output of a JK flip flop becomes a 1 after a the output was previously
clock pulse, which statement below was possible 0, J = 0 and K = 0

The time that an input to a flip flop must remain setup time
stable after the edge of the clock pulse is called
____
What happens if the input is high in FSM? Change of state

Moore machine has _________ states than a Fewer

mealy machine.
A finite state machine has an output determined Moore machine
only by the present state of the system is ____

A data type in VHDL which has been defined by an entity

the user is called ____
Which among the following is/are identical in Combinational output
Mealy & Moore machiness signal
Which of the following is not a type of VHDL Behavioral modeling
modeling
In behavioral modeling, what do descriptive How the system performs
statements describe on given input values

Which of the following modeling style follows the Dataflow modeling

sequential processing of instructions

Component instantiation is the part of Behavior

__________ modeling
 In Net-list language, the net-list is generated Before
_______synthesizing VHDL code
Which function is used to map a generic on design Port map()

Register transfer level description specifies all of Sequential

the registers in a design & ______ logic between
them
Sequential circuit includes delays

Outputs are functions of present state

In most synthesis tools, only generics of type INTEGER

________ are supported
Generics in VHDL can be treated as _______ Global variable
Which data type in VHDL is non synthesizable & Scalar
allows the designer to model the objects of
dynamic nature
States in FSM are represented by ________ Bits
What is the first state of FSM? Wait loop state
In mealy type FSM, the path is labelled by which Inputs
of the following?
What are the two constructs used in most of the Assign
behavioural modelling?
Timing performance of design is checked by which Gate-level
of the following simulation mode?
Which of the following can’t be declared in an Signal
architecture?
Which of the following attribute is generally used ‘STABLE
in implementation of sequential circuits?

To obtain 16-bit data bus width, the two 4K*8 parallel

chips of RAM and ROM are arranged in
The semiconductor memories are organised as 1D
__________ dimension(s) of array of memory
locations.
The advantage of dynamic RAM is high packing density

If a typical static RAM cell requires 6 transistors 1 transistor along with

then corresponding dynamic RAM requires capacitance

Which components play a significant role in the Two MOSFETs

formation of a dynamic RAM?
With the availability of 16 x 4 memory size, how 4
many ICs ( memory chips) will be required for the
expansion of its word size in order to obtain 16 x
8 memory?
A technique of addressing storage cells on a flash conversion
dynamic RAM that sequentially uses the same
inputs for the row and column addresses of the
cell is called________.
Refreshing DRAM typically must occur every 2 µs
________.
The time interval between the memory receiving access time
a new address input and the data being available
is called
In general, _________ are used when a small EEPROMs
amount of read/write is required
The periodic recharging of DRAM memory cells is Multiplexing
called
In modern chips, VDD is 1V
Only one bit line is used in SRAM
Which of the following memory technology is DRAM
highly denser?
Which of the following capacitor can store more planar capacitor
data in DRAM
Which of the following is the main factor which number of transistors
determines the memory capacity
Which of the following is correct refreshed rate 10-1000ms
for DRAM?
Signal at the output of sense amplifier of selected Bus-output line
column is fed to
Why is SRAM more preferably in non-volatile low-cost
memory?
Which type of storage element of SRAM is very TTL
fast in accessing data but consumes lots of
power?
What is approximate data access time of SRAM? 10 ns
Which of the following can easily convert to non- DRAM
volatile memory
Which memory storage is widely used in PCs and SRAM
embedded system?
Which of the following is more volatile ROM
what is the size of trench capacitor in DRAM? 1MB
What two functions does a DRAM controller address multiplexing and
perform data selection

Which storage element is used by MAC and IBM CMOS

PC
Who proposed the miniature card format INTEL
Refresh operation is always carried out in burst mode
If operation is read, bit line is precharged to VDD
Memory Chip is available for normal operation 98% of time
more than
When word line is selected and circuit voltage Breakdown
raised to supply voltage, access transistor will

when DRAM cell is storing 0, capacitor voltage supply voltage

goes to
SRAM
To hold saved data even if the power is turned off
USB-type storage device is - Secondary
Which is the type of clock distribution H tree
To reduce the delay
Why do we use buffers in a clock distribution
Making the line thinner
The propagation delay of a long interconnection
line can be reduced by
Balance the delays of the
One of the main approaches to handle the clock critical paths in the circuit
skew problem is
Global skew is less
Which of the following statements is true for important than local skew
clock networks
Which clock topology is better for distributing A pure H-tree topology
clock signals to a large number of arbitrary points
in a chip?
In floorplanning, placement and routing are called Front end tool
as
In floorplanning, which phase/s play/s a crucial Placement
role in minimizing the ASIC area and the
interconnection density?
 Viterbi’s algorithm
Maze routing is also known as
Increase in the physical distance of H-tree the Decreases
skew rate also
In signal integrity, which noise occur due to Power Noise
impedance mismatch
Maze routing is used to determine Shortest Path
The parasitic capacitances found in MOSFET are Oxide related capacitances

Interconnect capacitance contributes to the Coupling Capacitance

Interconnect capacitance is formed due to Junction capacitance
between gate and
substrate

The term Signal Integrity (SI) addresses two the timing and the quality
concerns in the electrical design aspects of the signal
Which process deals with the determination of Testing
resistance & capacitance of interconnections in
VLSI design?
Variation in voltage at the VDD or VSS node with Ground Bounce
respect to an external ground is called
In floor planning, placement and routing are Front end tool
In signal integrity, which noise/s occur/s due to Power/Ground Noise
impedance mismatch,In signal integrity, which
noise/s occur/s due to impedance mismatch,
stubs, vias and other interconnecct

Skew describes a -----------------------------in time relative delay or offset

between two signals.
The jitter affects ---------------of the circuit power delay
Parasitic components are Capacitance and
inductance
Wire resistance are computed by measuring capacitance

___________________caused by EM coupling Crosstalk

between multiple transmission lines running
parallel.
Each pad must be large enough to have a metal soldered
Each pad has large Power lines
High temperatures can also cause chips to Pass
permanently
To design VLSI____________architecture is used system on a circuit

Diffusion capacitance is equal to area capacitance

Which layer has high resistance value polysilicon

In which design all circuitry and all semi-custom design
interconnections are designed
Which file is required as an input for floor UCF
plaaning
Which one is Outputs of Floor Planning Stage cost of die
Two types of Routing Global and detailed
Many companies are transitioning to using FPGAs FPGAs always outperform
for their processor designs instead of an ASIC .
ASICs. Why?
Which among the following statement/s is/are Short design cycle
not an/the advantage/s of Programmable
Logic Devices (PLDs)?

Most FPGA logic modules utilize a(n) ________ AND array

approach to create the desired logic
functions.

Given a gate-level netlist represented by a graph, The 4-input LUT is typically

which of the following is not true for 4- realized using a 16x1 SRAM
input LUT mapping in a typical FPGA? unit.

Which of the following statements is true for a 4- It can be implemented

input LUT in a typical FPGA? using a 16x1 static memory
block.
Which of the following represents the correct FPGA, Gate array, Standard
ordering with respect to speed of circuits cell, Full custom
(slowest to fastest)?
_________ is the fundamental architecture block system Partitioning
or element of a target PLD.
In testability, which terminology is used to Validation
represent or indicate the formal evidences of
correctness?
Which among the following is regarded as an Excessive steady-state
electrical fault? currents
Which among the following faults occur/s due to Process variations &
physical defects? abnormalities 
In logic synthesis, ________ is an EDIF that gives Netlist
the description of logic cells & their
interconnections.
Simple Programmable Logic Devices (SPLDs) are Programmable Array Logic
also regarded as _____________. (PAL)
stuck open (off) fault occur/s due to _______ An incomplete contact
(open) of source to drain
node

Which type/s of stuck at fault model exhibit/s the Single

reduced complexity level of test generation?

Why is multiple stuck-at fault model preferred for Because single stuck-at
DUT? fault model is independent
of design style &
technology

In spartan-3 family architecture, which Configurable Logic Blocks 

programmable functional element accepts two 18
bit binary numbers as inputs and computes the
product?
Due to the limitations of the testers, the Lower than
functional test is usually performed at speed
_______the target speed.
High observability indicates that________ More
number of cycles are required to measure the
output node value.
Basically, an observability of an internal circuit Inputs
node is a degree to which one can observe that
node at the _______ of an integrated circuit.

Primary objective of testing is to guarantee Fault-free products

Input to a testing process Test stimuli only

Output of a testing process Test response

Verification targets Design Errors
Testing targets Design Errors

Applying all possible test patterns to a CUT is Exhaustive testing

called
JTAG stands for_________________ Joint Test Action Group

In a CMOS logic gate, stuck-short fault of a PMOS SA1

transistor is represented as a
__________ fault at input.
The configurable logic block (CLB) constitutes the FPGA
basic ____ cell
JTAG Boundary Scan Standard is IEEE 1149
JTAG can operate at chip only

TAP Controller FSM goes through _____ nimber 13

of states
TAP stands for Test Access Port
How many are the signals to TAP controller 2
Hierarchy of the Logic Block in FPGA is LC-Slice-CLB
FPGA does not include______ Embedded Multipliers
Stick diagrams are those which convey layer color
information through?
Which color is used for polysilicon? Red
Which color is used for buried contact? Red
_______ layer should be over ______ layer.  polysilicon, ntype
When two or more cuts of same type cross or  like contact
touch each other, that represents __________

Design rules does not specify ________  separations

The width of n-diffusion and p-diffusion layer λ
should be?
What should be the width of metal 1 and metal 2 3λ, 4λ
layers?
Which gives scalable design rules? micron rules
The oxide layer below the first metal layer is chemical vapour deposition
deposited using __________
 Minimum n-well width should be ____________ 2
micro meter.
What are the advantages of design rules?  scalable
The scaling factor for the supply voltage VDD is:  1/β

The scaling factor of length and width of the 1/α, 1/β

channel are:
 The scaling factor of Gate Capacitance per unit  1/α
area is:
Which type of simulation mode is used to check Switch-level
the timing performance of a design?
In which design all circuitry and all semi-custom design
interconnections are designed?
Which method is used for verification along with computer assisted textual
generation? entry
Simulators are available for switch level logic
Which gives the main electrical behaviour of timing simulator
various parts of the circuit?
buried contact
Which is a more complex process
polysilicon
Which layer is used for power and signal lines
What is the basic use of EDA tools Communication of
Electronic devices

Which of the following is not an EDA tool? Quartus II

 VLSI QUESTION BANK -MCQS -2021

Option Text 2 Option Text 3 Option Text 4 Correct Option

nonconducting partially conducting insulating 2

high zero minimum 1

high low high 4
SiO2 polysilicon gallium 3

negative charge neutral no charge 2

resistors buffers capacitors 2

channel width depth concentration 1

discharge no change random 2

2.5Wn 3Wn 3.5Wn 2

drain gate body 4

finite infinite default 2

switches buffers doides 1

PMOS CMOS BiCMOS 3

four five two 3

good worst ideal 4

Vds Vdd Vss 2
high simple good 1
50 100 1000 3

FIFO FILO LILO 2

drain ground Vdd 1

Assignment loop wait 2

Identifier Name Literal 2

SLL SLA SRA 1

Simulation No delay single driver 1

Transport delta Wire 1

Simulation inertial Wire 4
Entity Architecture configuration 2

real bit-vector std_logic 1

Generic Genericmap() port 3

local variable variable signal 1

declarative block Guard 4

generate use guarded block 2

block statement Process Generics 3

Entity Architecture Configuration 3

2 3 4 2

Component dataflow structural 2

process() if-else case 1

Sequence Process Dataflow 3

conditional Sequential Selected 3

WHEN FOR END 2

high-cost low power transistor as a storage 3

consumption element
10ns 2ns 60ns 1
4 6 8 3
PROM EEPROM EPROM 1
DRAM SRAM RAM 1

DRAM DDR SRAM DDR SRAM 1

EPROM DRAM Flash memory 3

Cycle time Memory latency 4

capacitor resistor mosfet 2

Usage of capacitors to Use of Shift registers The defect of the 2
store the charge capacitor
Decoder Encoder Multiplexer 4

inductor transistor resistor 3

distributive refresh software refresh refresh cycle 4

by the refresh cycle by refresh cycle and refresh frequency and 3
refresh time refresh cycle
120 microseconds 130 microseconds 135 microseconds 1
to select a specified to select a location to select a read/write 3
chip within the memory cycle
chip
Word line Length line Principle diagonal 2

Data line word line Read line 1

Data Line Address Decoder Control Line 3

Latency Delay Access time 4

after reading every after reading all cell after reading all 1
column column
Must be refreshed Loses data when Must be refreshed 2
periodically power is removed after Writing
Restorer Refresh counter Shift register 3

stuck-on stuck-short stuck-open 4

Design style Design style delay dependent 3

dependant independent
fault-error-failure failure-error- fault error-failure-fault 2

 Controllability Testability Manufacturability 2

Counters LFSR  Weighted LFSR 3

Joint Text Acess Group Joint Test Action Joint Text Apply Group 3
Group
fabrication logic design debugging 1
TCLK TDI TS 4
Capture-Shift-Update- Capture-Shift-Pause- Shift-Update-Capture- 2
Pause Update Pause
Test Action Port Text Access Text Action Port 1
controller Port controller controller
checking errors and checking all outputs checking all inputs 2
performance
by reducing adders by reducing by dividing circuit into 4
multiplexers subcircuits

Input scan output scan fault scan 1

It affects Observability It affects Testability It affects 1
Manufacturability
20% 10% 25% 1

after enumerating  before enumerating before designing 2

faults faults
gating circuit self-clock self timing 4
asynchronous circuits sequential circuits  clocked circuits 2

layout design  logic domain testing domain 3

if they are far away  it always gives rise to does not allow croo- 1
croo-talk problems talk problems

2 1 3 1

high zero minimum 1

high low high 4
two diode three diode four diode 2

negative charge neutral no charge 2

resistors buffers capacitors 2

width depth concentration 1

discharge no change random 2

2.5Wn 3Wn 3.5Wn 2

drain gate body 4

finite infinite default 2

switches buffers doides 1

PMOS CMOS BiCMOS 3

four five two 3

good worst ideal 4

Vgs electric field source 2
high simple good 1
50 100 1000 3

FIFO FILO LILO 2

drain ground Vdd 1

Width Depth Concentration 1

Four Five Two
3
50 100 1000 3
Drain Gate Body 4
2.5Wn 3Wn 3.5Wn 2
Good Worst Ideal 4
High Zero Low 2
Switches Buffers Diodes
1
Combinational process Clocked process Unclocked process
3
Two Three Four
2
Set Invalid Unknown 1
Output values Clock input Current state 1
 State Output value Initial state 2
Synchronous Level Pulsed clock
1
Clocked Process Both a and b Sequential clock 2

State transitions and Reset condition Reset condition

output specifications
4
Ligh-cost Low power Transistor as a storage
consumption element 3
6T 3T 4T 2
DRAM DDR SRAM DDR RAM
1
Inductor Transistor Resistor
3
Distributive refresh Software refresh Refresh cycle
4
Capacitor Resistor Mosfet 2
Latency Delay Access time

4
Must be refreshed Loses data when Must be refreshed
periodically power is removed after Writing 2
B tree Clock tree S tree 1
To reduce area To generate multiple To reduce speed
clock phases 1
Making the line wider. Inserting one or more Clock delay
buffers along the line.
3
Increase the time Equalize the worst- Sequential clock block
period of the clock. case delays of every
combinational block 2
Global skew is more Both global and local Inside the chip, both
important than local skews are equally global and local skews
skew. important. are equal. 1
A MMM Algorithm A clock mesh driven in A Spine tree
parallel by a regular H-
tree 3
Back end tool End to End tool Both 1 and 2
2
Global Routing Detailed Routing All 1, 2 and 3

4
Prim’s algorithm Quine-McCluskey Lee-Moore algorithm
algorithm 4
Increases Constant Changes
2
Crosstalk Noise Reflection Noise Ground Noise
3
Average Path Longest Path Medium Path 1
Joint Text Acess Group Joint Test Access Joint Test Action Group
Group 4
Fabrication Logic design Debugging 1
Test Access Text Access Text Action Port
Port controller Port controller controller 2
Flipflops Counter Register 1
TCLK TDI TS
4
Parallel Adder Multi Adder Single Adder 2
Resistor IC Component 3
SRAM ROM RAM 2
It is easier to It is faster than a It requires advance
implement logically ripple-carry adder knowledge of the final
than a full adder answer 3
Half-adder and full- Asynchronous and One and two’s-
adder synchronous complement 2
3 2 5
3
If all of the output are  If all of the input are If all of the output are
independent of the dependent on the dependent on the
inputs output input 2
Color Thinness Shapes
2
Green Black Red 4
Separations Extensions Colors 4
Micron rules Layer rules Thickness rules 1
Constant voltage Costant electric and Costant current model
scaling voltage scaling 3
Decreased Must not vary Exponentially
decreased 2
Channel length  Width Thickness d
2
Textual entry Graphical entry Simulation
1
 Switch level logic Gate level logic Design level logic 2
Microwind Pyxis Callibre 1
Polysilicon n diffusion p diffusion 1
Timing simulator Logic level simulator Functional simulator 2
gate switching delay gate switching delay gate power dissipation A
and gate power and net gate power and absorption
absorption

n-type substrate of p-type substrate of n-type substrate of C

low doping level moderate doping level high doping level

two diodes three diodes four diodes B

conducting channel Vdd Vss B

nonconducting insulating partially conducting B

non symmetrical semi symmetrical pseudo symmetrical A

negative carriers both in equal numbers neutral B

decreases increases increases exponentially B

logarithmically
silicon dioxide poly silicon gallium C
insulating layer lower metal layer p type layer A
drain to source source to ground source to gate A
channel region switch region bulk region B

switches buffers doides A

fifty logic gates hundred logic gates thousand logic gates C

error in variation error in doping distribution error B

FIFO FILO LILO B

switch-transistor logic transistor-buffer logic circuit level logic A

transmission gates pass transistors and design rules C

transmission gates
more high very less A
no more two B

silicon plates conductors resistors A

switch logic complementary logic restoring logic D
decreases does not vary exponentially A
decreases
parallel cascade random B

NAND NOR OR C
3 to 4 4 to 5 5 to 6
A
three four five
D
cut off non saturation saturation
D

voltage source divider buffer

A
finite off resistance buffers infinite off resistance
D
high very high Z
A
low very low medium
A
pull down transistor both pull up and pull at gate
B
down
area of p device total area of n and p square of minimum
C
device feature size
Vdd2 x f C x Vdd2 C x Vdd2 x f D
PMOS CMOS BiCMOS C
the output Q is both Q and notQ both Q and notQ
A
INACTIVE outputs are ACTIVE outputs are INACTIVE
port enable port map port assignment
C

Output values Clock input Current state

D
State Output value Initial state B
Twice Thrice Four times
A
concurrent sequential or primitive
concurrent depending
on the order of the A
statements

hold time propagation time recovery time

D

State transitions & Reset condition  All of the above

output specifications D

5 25 2 25 B
the output was the output was the output was
previously 1, and K = 1 previously 1, and J = 1 previously 0, J = 0 and C
K=1
hold time propagation time recovery time
B

 No transition in state Remains in a single Invalid state

A
state
More Equal Negligible
B
Mealy machine Max machine Minimum machine
A

user library std_logic enumerated type

D
Clocked Process Both a and b None of the above
B
Dataflow modeling Structural modeling Component modeling
D
How the design is to Netlist Concurrent execution
be implemented A

Behavior modeling Structural modeling Component modeling

B

Component Dataflow Structural

D
At the time of (during) After None of the above
C
Generic() Generic map() Port
C
Combinational Both a and b None of the above
B

feedback delays and feedback delays and feedback

D
from input to output from output to input
previous state next state present and next state
A
REAL BIT_VECTOR STD_LOGIC
A
Local variable Variable Signal A
Access Composite File
B

Bytes Word Character A

Initial state Output state Activate pulse state B
Outputs Both inputs and Current state
C
outputs
Begin and end Initial and always Always and end
C
Behavioural Transistor-level Switch-level
A
Constant Variable BIT_VECTOR
C
‘LENGTH ‘LAST_EVENT ‘EVENT
D

) serial both serial and parallel neither serial nor

A
parallel
2D 3D none
B
low cost less power all of the mentioned
D
consumption
2 transistors along 3 transistors along 2 transistors along
with resistance with diode with capacitance A

Two capacitors One MOSFET and one One MOSFET and two
C
capacitor capacitors
8 16 2
D

dynamic refresh address multiplexing address strobe C

2 ms 8 µs 8ms
B
bus speed read/write speed write/data speed
A

PROMs SRAMs DRAMs

C
Bootstrapping Refreshing Flashing
C
3.3V 2.2V 5V B
DRAM ROM PROM B
SRAM EPROM Flash
A
trench capacitor stacked-cell non-polar capacitor
C
number of capacitors size of the transistor size of the capacitor
A
10-50ms 10-100ms 10-500ms
C
Data-output line input-output line register-output line
B
high-cost low power transistor as a storage
C
consumption element
CMOS NAND NOR
A

8ns 6ns 4 ns
D
EPROM ROM SRAM
D
DRAM PROM ROM
B
PROM SRAM DRAM D
4-256 MB 8-128 MB 64-128 MB B
address multiplexing data selection and the data selection and CPU
and the refresh refresh operation accessing B
operation
transistor capacitor inductor
A
IBM MIPS APPLE A
boot mode auto mode manual mode A
VDD/2 VDD+1 2VDD B
89% of time . 49% of time 39% of time
A
mild voltage ON OFF
C

input voltage output voltage zero voltage

D
NVM DRAM ROM
B
Axillary Tertiary Primary A
B tree Clock tree S tree A
To reduce area To generate multiple To reduce speed
clock phases A
Making the line wider. Inserting one or more Clock delay
buffers along the line.
C
Increase the time Equalize the worst- Sequential clock block
period of the clock. case delays of every
combinational block B
Global skew is more Both global and local Inside the chip, both
important than local skews are equally global and local skews
skew. important. are equal. A
A MMM Algorithm A clock mesh driven in A Spine tree
parallel by a regular H-
tree C
Back end tool End to End tool Both 1 and 2
B
Global Routing Detailed Routing All 1, 2 and 3

D
Prim’s algorithm Quine-McCluskey Lee-Moore algorithm
algorithm D
Increases Constant Changes
B
Crosstalk Noise Reflection Noise Ground Noise
C
Average Path Longest Path Medium Path A
Inter electrode Electrolytic capacitance All
D
capacitance
Load Capacitance Junction capacitance Bulk capacitance B
Wire connecting the Parasitic capacitance parasitic and junction
gates of 2 different existing between capacitance
inverters metal and C
polysiliconconnection

time and signal input period and signal Clock delay

A
output
Extraction Floorplanning Placement & Routing
B

Power limit VDD Supply Voltage

A
Back end tool both none B
Crosstalk Noise Reflection Noise All of the above

clock delay time dealy relative delay

A
time delay set-up delay the clock delay D
Resistance and resistance and inductance
B
capacitance inductance
thickness of metal measuring size of the Plate resistance
C
wire
Reflection Jitters skews
A

thickness of metal wire soldered minimum C

VDD and VSS lines supply lines ground lines B
VDD VSS Fail
D
system on chip system on a device system on gates
B
peripheral capacitance fringing field area capacitance +
capacitance peripheral capacitance D

silicide diffusion metal A

gate array design full custom design transistor design
C
Netlist (.v) VHD VTBW
B
Wafer SOC I/O pad/placed D
Supply and ground VDD and VSS BOX and Line A
The development FPGAs are more FPGAs are Flexibile
cycle for FPGA is much space‐efficient. B
shorter.
Increased space Increased flexibility Decreased space
requirement requirement
B

Look‐up table OR array AND and OR array

B

Any subgraph with up In SRAM-based LUTs, 2-input lookup tables

to 4 input edges and 1 the function of the are always used to
output edge can be LUT can be changed by imlement
mapped to a LUT downloading
irrespective of the appropriate D
number of vertices bit patterns in the
included therein. associated RAM
locations.

It can implement any It can implement any It can also implement a

function of 2-, 3- or 4-
function of 4 variables few functions of 5 and A
variables only. 6 variables
FPGA, Gate array, Full Gate array, FPGA, Gate array, FPGA, Full
custom, Standard cell Standard cell, Full custom, Standard cell A
custom
 Pre-layout Simulation Logic cell Post-layout Simulation
C
Verification Simulation Integration
B
Delay faults Bridging faults Logical stuck-at-0 or
A
stuck-at-1
Defects in silicon Photolithographic Mentioned all faults
D
substrate defects
Checklist Shitlist Dualist
A

Generic Array Logic Programmable Logic PAL,GAL and PLA

D
(GAL) Array (PLA)
Large separation of Open Contact and Contacts Short
drain or source Seperation
C
diffusion from the
gate
Dual Mutliple no fault
C

Because single stuck- Because complexity of Because of the three

at tests cover major % test generation is reasons mentioned
of multiple stuck-at reduced to greater above
D
faults & unmodeled extent in multiple
physical defects stuck-at
fault models
Input Output Blocks Block RAM Multiplier Blocks
D

Equal to Greater than infinite

A

Equal  Less Not Equal

C

Outputs Inout Buffer

B

Detection of design Reduction of product Increase in test cost

A
error cost
Circuit under test only Test patterns only Test Stimuli and Circuit
D
under test
Circuit under test DUT HDL Code A
Manufacturing Errors Contact Errors Product errors
A
Manufacturing Errors Contact Errors Product errors
B
Complete testing Functional testing simple testing
A
Joint Technical Joint Technical Joint Technical
A
Advisory Group Assessment Group Activities Group
SA0 1 0
B

CPLD PLD RAM

A
IEEE 1149.1 IEEE 1149.2 IEEE 1149.3 B
PCB only system levels only chip, PCB, & system
D
levels
14 15 16
D
The Access Port Test Access Pin The Access Pin A
3 4 5 D
LC-CLB-Slice Slice-LC-CLB Slice-CLB-LC A
Adders MACs CPLD D
Shapes layers thickness B

Green White Brown B

Green White Brown A
ptype, ntype ntype, ptype ntype, polysilicon B
electrical contact cross contact contact cut C

extensions colours linewidths D

4λ 2λ 3λ D

3λ, λ 2λ, λ 3λ, 3λ B

layer rules thickness rules lambda rules A

layer rules scattering method diffusion method B

1 4 3 A

portable all of the mentioned durable D

0 1 1/α B

 1/α, 1/α 1/β, 1/β 1, 1 C

 β α 1/β C

 Transistor-level Gate-level Behavioural D

gate array design transistor design full custom design A

computer assisted silicon compiler-based hand-crafted designs C

graphical entry design
gate level logic design level logic  transistor level logic B
 logic level simulator  functional simulator  circuit simulator A

butting contact buried & butting only butt

A
contact
silicon metal red
C
Fabrication of Electronic circuits Industrial automation
Electronics hardware simulation and C
synthesis
Xilinx ISE Visual C++ MaxPlus II A