Multiplexer,

Encoder and
Decoder

Lab 05
Prepared By: Rakesh Mahto
Objective
  Basic of Multiplexer

  Basic of Decoder

  Basic of Encoder

  VHDL Code for Decoder

  VHDL Code for Encoder

  Using Components in VHDL

 Multiplexer
Input S1 S0 B
0 0 A0
A3
Output 0 1 A1
A2 B 1 0 A2
A1 1 1 A3
A0
case S is
S1 S0 when “00” => B <=A(0);
VHDL when “01” => B <=A(1);
Code when “10” => B <=A(2);
when others => B <=A(3);
end case;
Decoder
Decoder
Encoder
  An encoder performs the inverse function of a
decoder. If input yi is 1 and the other inputs are 0,
then abc outputs represent a binary number
equal to i.
  For example, if y3 = 1, then abc = 011.
  If more than one input is 1, the highest numbered
input determines the output.
  An extra output, d, is 1 if any input is 1, otherwise d is
0. This signal is needed to distinguish the case of all 0
inputs from the case where only y0 is 1.
8-to-3 Priority Coder

y0 y1 y2 y3 y4 y5 y6 y7 a b c d
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
X 1 0 0 0 0 0 0 0 0 1 1
X X 1 0 0 0 0 0 0 1 0 1
X X X 1 0 0 0 0 0 1 1 1
X X X X 1 0 0 0 1 0 0 1
X X X X X 1 0 0 1 0 1 1
X X X X X X 1 0 1 1 0 1
X X X X X X X 1 1 1 1 1
VHDL code for decoder
process (I)
begin

case I is Note: Input and

when "00" => O <= "0001"; output are
considered as
when "01" => O <= "0010"; Std_Logic_Vector
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;

end process;
VHDL code for encoder
entity prio_encoder42 is port(
r: in std_logic_vector(3 downto 0);
code: out std_logic_vector(1 downto 0); input Output
active: out std_logic
r code active
); end prio_encoder42;
1XXX 11 1
architecture cond_arch of prio_encoder42 is
begin 01XX 10 1
code <= "11" when (r(3)=’1’) else
"10" when (r(2)=’1’) else 001X 01 1
"01" when (r(1)=’1’) else
"00"; 0001 00 1
active <= r(3) or r(2) or r(1) or r(0);
end cond_arch; 0000 00 0
Component Declaration
component component_name
generic(
generic_declaration;
generic_declaration;
…………
);
Port(
port_declaration;
port_declaration;
……….
);
Components in VHDL
architecture xor_arch of even_detector is
signal odd: std_logic;
begin
even <= not
odd <= a(2) xor a(1) xor a(0);
end xor_arch;

Courtesy: Dr. James Plusquellic

Continue…

Courtesy: Dr. James Plusquellic

architecture str_arch of even_detector is component xor2
-- declaration for xor gate
port( i1, i2: in std_logic; o1:
out std_logic
); end component;
component not1 -- declaration for
inverter port(
i1: in std_logic;
o1: out std_logic
); end component;
signal sig1,sig2: std_logic;

begin

-- instantiation of the 1st xor instance unit1: xor2

port map (i1 => a(0), i2 => a(1), o1 => sig1);

-- instantiation of the 2nd xor instance unit2: xor2

port map (i1 => a(2), i2 => sig1, o1 => sig2);

---instantiation of inverter unit3: not1

port map (i1 => sig2, o1 => even);

end str_arch;
Reference
  Pong P. Chu, “ RTL Hardware Design Using VHDL”.

  Charles H. Roth Jr., Larry L. Kinney, “Fundamentals of

Logic Design”.