1

CHAPTER 1

INTRODUCTION

1.1 GENERAL

The impact of power electronics is felt in several fields of electrical

engineering, such as electric drives, flexible AC transmission systems, and
uninterrupted power supplies. Power electronics plays a major role in energy
conservation and development of the power industry. The need for power
electronics has increased over the years due to its advantages in the control of
electrical energy. This surge is due to several factors; the most important
being the technological advancements in the semiconductor devices industry,
which has led to the introduction of high-speed and high-power integrated
devices. Other factors include: (i) the advances made in the area of
microelectronics that have paved the way for the development of efficient
integrated circuits and growth of processors, and (ii) the ever increasing need
for smaller size and lighter weight power electronic components. However,
these power electronics devices impose some serious problems on the quality
of power. The increasing reliance on the power converters and the need to
provide quality power has mandated that all such power electronics systems
should have low harmonic content, less Total Harmonic Distortion (THD),
and improved input power factor.

This chapter gives a brief overview of the static AC-to-AC power

and frequency conversion structures and introduces the structure and
operation of the matrix converter, which is the topic of this thesis. Later, the
 2

literature review and a new error integrative algorithm suitable for high
frequency switched three-phase-to-three-phase matrix converter are presented
along with the objective and organization of the thesis.

1.2 STATE-OF-THE-ART REVIEW OF THE THREE-PHASE

AC-TO-AC CONVERTER

The basic function of a power converter is to process the energy

using the power switches. AC power conversion can be classified as (i) direct
AC-to-AC and (ii) indirect AC-to-DC-to-AC. At present, voltage source
back-to-back converters (AC-DC-AC) are widely used in the AC conversion
systems. These converters require bulky storage electrolytic capacitors. The
operation of these converter stages (stage-1: AC-DC) and (stage-2: DC-AC) is
controlled independently since they are decoupled by means of an energy
storage element. Therefore, the instantaneous input power need not be equal
to the instantaneous output power. The difference between the instantaneous
input power and the instantaneous output power is absorbed or delivered by
an energy storage element within the converter. The storage element is the
bulky storage electrolytic capacitor prone to poor performance at high
temperatures and susceptible to failures (Hitachi inverter instruction manual).
Therefore, the use of the storage capacitor not only increases the system
weight and volume but also results in reduced reliability of the system.

The energy storage element is not required in a direct converter

(Gyugyi and Pelly 1976). Because of the absence of the energy storage
element, the instantaneous power input must be equal to the instantaneous
power output. However, the reactive power input need not be equal to the
reactive power output. Figure 1.1 shows the classification of the direct
AC-to-AC converter into three distinct topological approaches. The first
approach is the AC voltage regulator that changes the amplitude of the AC
waveform (Hashem and Darwish 2004). The second approach is the cyclo
 3

converter, which is used if the required output frequency (Maamoun 2003) is

much lower than the input source frequency. The third approach is the matrix
converter, which is the most versatile and has no limits on the output
frequency and the amplitude. In other words, the input may be three-phase
AC and the output DC, or both may be DC, or both may be AC (Mohan et al
2003). Therefore, the matrix converter topology is promising for the universal
power conversion such as AC to DC, DC to AC, DC to DC or AC to AC. The
matrix converter offers some significant advantages such as adjustable power
factor, inherent four-quadrant operation, high quality sinusoidal input/output
waveforms and high power density. Hence, it has received extensive attention
in research as a replacement for the traditional AC-DC-AC converter for
variable-voltage and variable-frequency AC drive applications.

AC-to-AC
Converter topologies

Direct AC-to-AC AC-to-DC-to-AC

Converter topologies Converter topologies
Conversion type
(Frequency & Amplitude)
AC Voltage Regulator
Conversion type
(Amplitude)
Cyclo-Converter
Conversion type
(Frequency & Amplitude) Matrix Converter
Conversion type
(Frequency & Amplitude)

Conventional Matrix Converter (CMC)

Direct (3×3) – nine switch type Indirect Matrix Converter (IMC)
Many topologies with reduced
number of switches

Figure 1.1 AC-to-AC converter topologies

 4

1.3 STRUCTURE OF THE MATRIX CONVERTER

The matrix converter is the force-commutated version of the

cyclo-converters (Huber and Borojevic 1989), which overcomes the
disadvantage of the conventional cyclo-converter such as the limitations in the
frequency conversion, rich output voltage harmonics and increased number of
switches (Rashid 2005 and Fa-Hai Li et al 1994). The matrix converters can
be classified as direct and indirect type matrix converters. Figure 1.2 shows
the direct or the conventional matrix converter (CMC) that is an array of 3×3
bidirectional switches. The indirect or the sparse matrix converter is a cascade
of the controlled rectifier and inverter topologies without a DC link in
between (Ziogas et al 1986). Both the topologies directly interconnect two
independent multi-phase voltage systems at different frequencies. In this
research, the CMC topology is chosen and is analyzed for its performance for
changes in its topology and with different pulse with modulation (PWM)
techniques.
Power Circuit
SAa SAb SAc
VA LA CA

LB SBa SBb SBc

VB CB

SCa SCb SCc

VC LC
CC

Input Filter Circuit

Va Vb Vc

LLa LLb LLc

Clamp Circuit
RLa RLb RLc

Figure 1.2 Structure of the conventional matrix converter

 5

The matrix converter is connected to a stiff voltage source at the

input and a stiff current source at the output. These externally connected
voltage and current sources impose constraints on the switching of the matrix
converter. At any instant, the voltage source should not be short-circuited and
the current source should not be open circuited. Equation (1.1) gives the
switching function of the switch Sij in Figure 1.2.

Sij ( t ) =1, Sij =closed

Sij ( t ) =0, Sij =open, where i ⋲ { A,B,C } & j ⋲ { a,b,c } (1.1)

Equation (1.2) gives the constraints namely that the inputs are not
short-circuited and the outputs are not open-circuited

d Aj + d Bj +d Cj =1 (1.2)

where, dij is the duty-cycle of the switch Sij. Equation (1.2) being less than one
indicates an open-circuit of the current source and Equation (1.2) being
greater than one indicates a short-circuit of the voltage source.

Therefore, Equations (1.3) and (1.4) represents the switching

function T of the matrix converter for the output voltages and the input
currents

V out = T × V in

V a S Aa SAb SAc VA

[ ][
V b = S Ba SBb SBc × VB
Vc SCa SCb SCc VC ][ ] (1.3)

where,

Va S Aa SAb SAc VA

[] [ ]
Vout = Vb , T= SBa SBb SBc and V in = VB
Vc SCa SCb SCc VC []
 6

I in = T T × I out

IA SAa SBa SCa Ia

[][IC SAc SBc SCc ][]

I B = SAb SBb SCb × I b
Ic
(1.4)

where,

IA SAa S Ba SCa Ia

[] [ T

] []
I in = I B , T = SAb S Bb SCb and I out = I b .
IC SAc S Bc SCc Ic

VA, VB, VC and Va, Vb, Vc are the input and the output phase voltages
respectively and IA, IB, IC and Ia, Ib, Ic are the input and the output currents
respectively.

1.3.1 Basic Components of a Practical Matrix Converter

The design of a practical matrix converter circuit shown in

Figure 1.2 involves the development of three essential circuits (i) the power
circuit, (ii) the input filter circuit and (iii) the clamp circuit.

The power circuit consists of nine bi-directional switches shown in

Figure 1.2 with 29 (512) possible switching states. However, only 27
switching states are used because of the limitations imposed on the power
circuit by the Equation (1.2).

The input filter is necessary to reduce the switching harmonics in

the input currents (Wheeler et al 2002a). Figure 1.2 shows the input filter
consisting of the source inductances LA, LB, LC and the source capacitors
CA, CB, CC.

The interruption of the inductive current during commutations leads

to high voltage spikes appearing across the switches. These high voltage
 7

spikes damage the switches, and therefore a clamp circuit, shown in

Figure 1.2, is required to store the inductive energy (Klumpner and Blaabjerg
2002). The clamp circuit transfers the inductive energy from the load to the
clamp capacitor during the turning OFF of the converter.

1.3.2 Bidirectional Switch Configurations

The power electronics realization of the matrix converter in

Figure 1.2 requires four quadrant bidirectional switches. Due to the lack of
semiconductor devices capable of operating in four quadrants, four quadrant
switches are constructed with two quadrant switches (Dynex Semiconductor
2007), as shown in Figure 1.3.

(a) (b) (c) (d)

Figure 1.3 Four quadrant bidirectional switches (a) diode-embedded

switch (b) reverse blocking IGBT (c) common emitter IGBT
and (d) common collector IGBT

The main advantage of the diode-embedded switch is its simple

configuration when compared to other bi-directional switch structures but the
main disadvantage of this configuration is the high conduction loss. The other
configurations have lower conduction losses than the diode-embedded switch.
The reverse blocking IGBTs are not often used as bidirectional switches
since, in practice, the IGBT has poor reverse recovery characteristics that
increases the switching losses and hence the overall system efficiency
decreases. Amongst the other two configurations, the common emitter
 8

configuration is widely used for high power applications

(Semikron-SK60GM123 2007). Common collector configuration although
requiring a reduced number of isolated power supplies for generating the
switching signals is not much preferred for high power applications
(Imayavaramban 2008).

1.4 COMMUTATION TECHNIQUES FOR THE MATRIX

CONVERTERS

With the constraints imposed on the matrix converter, as explained

in Equation (1.2), it is found that each output phase of the matrix converter
must always be connected to one and only one input phase even during the
commutation. Since the matrix converter does not have an inherent
freewheeling path, the commutation of its bidirectional switches is much
more difficult than the commutation of switches in an inverter.

Various commutation techniques have been proposed for matrix

converters namely (i) the dead-time commutation, (ii) the soft switching
technique, (iii) the multi-step current commutation and (iv) the multi-step
voltage commutation.

The implementation of the dead-time commutation in matrix

converters leads to the interruption of inductive currents due to the absence of
a freewheeling path. Use of such technique in matrix converters requires
snubber circuits to provide an alternate path to the inductive currents (Sunter
and Clare 1996), which increases the complexity and the size of the
converters.

Soft switching techniques have been investigated in many converter

topologies for reducing the switching losses. However, the implementation of
soft switching techniques in matrix converters (Marcks 1995) increases the
component count and complexity of the converters.
 9

At present, the most popular methods of commutation are the multi-

step current and multi-step voltage commutations. The idea of such multi-step
commutations techniques first appeared in Oyama et al (1989) and Burany
(1989).

1.4.1 The Four-Step Current Commutation

To determine the commutation sequence, the method relies on the

direction of the load current. The bidirectional switch (BS) that will stop
conducting after the commutation is known as the outgoing BS and the BS
that will start conducting after the commutation is known as the incoming BS.
Each BS consists of two switches, named as S + and S-, which indicates the
direction of the current flow through the respective switches.

Before the commutation process starts, both the switches S +, S- of

the outgoing BS are ON. With this condition, the safe commutation sequence
of the BS to transfer the load current from one phase to another phase is
explained below.
BS S1

LA S1+ S1- IL
VA
CA
RL - Load

VB LB S2+ S2-
CB
BS S2

Figure 1.4 Commutation of the bidirectional switches between the two

input phases
 10

Step 1 : When the commutation to an incoming BS is required, the

current direction is used to determine the non-conducting switch
in the outgoing BS. This switch is first turned OFF.

Step 2 : Then, the switch in the incoming BS that would conduct the
current in the same direction is turned ON. This is done to form
a path for the load current to continue flowing either at the point
when the next switch of the incoming BS is gated ON or when
the conducting switch of the outgoing BS is turned OFF.

Step 3 : The conducting switch of the outgoing BS can now be turned

OFF safely, since a new path is made available for the current to
flow as in Step 2.

Step 4 : Finally, the other switch of the incoming BS is switched ON to

complete the sequence of commutation.

For Example, in the Figure 1.4, when the iL > 0,

(i) Switch S1- is turned OFF, (ii) Switch S2+ is turned ON,
(iii) Switch S1+ is turned OFF, and (iv) Switch S2- is turned ON.

Similarly, the four-step current commutation sequence of switching

can be formulated for other cases and is given in Figure 1.5.

1 1 0
0 0 0
iL > 0 0 1 1
0 0 0

S1+ S1+ 0
1 0
1 S1- S1-
S2+ S2+ 1
0 1
0 S2- S2-

0 0 0
1 1 0
iL < 0
0 0 0
0 1 1

Figure 1.5 State diagram of the four-step current commutation

 11

Since the commonly used Hall effect sensors are prone to produce
uncertain results in high power and low current applications, it is difficult to
reliably determine the direction of current for commutation. To avoid this
problem, a technique named as voltage commutation that uses the voltage
across the bidirectional switch for measurement of the direction of current
(Wheeler et al 2002b) has been developed. Later, a technique utilizing the
zero vectors (Mahlein et al 2002) to avoid commutation error, when the line
voltage is zero, was proposed for robust commutation. However, the input
current in this technique was found distorted compared to the voltage and
current commutation techniques because of utilizing a different switching
sequence.

1.5 MODULATION TECHNIQUES FOR THE MATRIX

CONVERTERS

Several modulation algorithms are reported for matrix converters in

Wheeler (2002a) to achieve different control objectives; basic classifications
of these modulation techniques are shown in Figure 1.6.

Matrix converter modulation

techniques
Venturini method

Modified Venturini & Alesina method

Variable amplitude triangular carrier method

Simplified carrier PWM method Direct space vector modulation (DSVM)

Indirect space vector modulation (ISVM)

MIN-MID-MAX modulation

Singular value decomposition method

Figure 1.6 Classification of the matrix converter modulation techniques
Rotating space vector modulation (RSVM)
 12

The development of this converter and its modulation techniques

started three decades back based on the complex mathematical formulation by
Venturini and Alesina (1980) with the voltage transfer ratio of 0.5. Later, the
Optimum Alesina Venturini (OAV) method (Alesena and Venturini 1989)
was proposed, in which the modulation index was extended from 0.5 to 0.866
by using the third harmonic injection technique. It was also proved that the
modulation index of 0.866 is the physical limitation for the matrix converter.
The carrier based PWM method with varying amplitude triangular carrier was
proposed by Yoon and Sul (2006). Later, Thuta (2007) proposed a simplified
carrier PWM technique. Control technique for space vector control of the
matrix converter was proposed by Huber and Borojevic (1995). Using the
idea of the ‘fictitious DC Link’, a conceptually different idea (Casadei et al
2002), decoupled the control into smaller independent units. Researchers of
matrix converter now predominantly use this technique. Modulation
algorithm using MAX-MID-MIN technique (Oyama et al 1989) used the
relative magnitudes of the input line or phase voltages for generating the
switching signals. Gupta et al (2010) proposed the use of rotating space
vectors for synthesizing the required outputs of the matrix converter for the
elimination of the common mode voltage in the matrix converter fed
induction machines. A generalized technique for modeling, analysis and
control of a matrix converter using the singular value decomposition method
was proposed recently by Hojabri et al (2011), which leads to a unified
modulation technique that achieves the full capability for a matrix converter.
In general, many of the modulation methods, established for the matrix
converter, are specific cases of this technique.

Since the most commonly used matrix converter modulation

techniques now is the indirect space vector modulation technique, the same is
widely used in the thesis and a brief review of it is presented next.
 13

1.5.1 Indirect Space Vector Modulation Technique

The Space Vector Modulation (SVM) techniques are the extension

of the theory of flux in multi-phase rotating machines (Bose 2004) to the field
of static power converters. Space Vector PWM (SVPWM) techniques are
well known for the Voltage Source Inverters (VSI). The idea of Direct Space
Vector Modulation (DSVM) for the matrix converter is difficult to understand
because of the unified representation of the current and the voltage space
vectors. Therefore, it would be a good approach to decouple the space vectors
of the matrix converter into independent current and voltage space vectors for
understanding its control (Huber and Borojevic 1995). This leads to the
decoupling of the matrix converter into a fictitious converter (input converter)
and a fictitious inverter (output converter) connected back to back, as shown
in Figure 1.7. Later, both the current control and the voltage control are
unified for the actual matrix converter and this method is termed as the
Indirect Space Vector (ISVM) PWM.

VA
SAp SAn
VB

SBp SBn
VC
SCp SCn

P N LLa RLa

Sap San
LLb RLb
Vb
Sbp Sbn
LLc RLc
Vc
Scp Scn

Figure 1.7 Decoupled representation of the conventional matrix converter

 14

The ISVM method obtains the required output voltages through two
analytically independent stages or transformations of the input voltages. This
requires representing the switching function T, given by Equation (1.3), as the
product of the rectifier switching function and the inverter switching function,
as given in Equation (1.5). In the first stage, the three-phase AC voltage is
converted to an average DC bus voltage of constant value. In the second
stage, this constant average DC bus voltage is converted to a three-phase AC
voltage of the required frequency and amplitude. Equations (1.6) and (1.7)
give the equations for the output voltages, output currents, input voltages, and
input currents with respect to the fictitious DC bus

T= T I × TR

SAa SAb SAc Sap San

[ ][ ][ S S S
SBa SBb SBc = S bp Sbn × Ap Bp Cp
SCa SCb SCc Scp Scn
SAn SBn SCn ] (1.5)

where,

SAa SAb SAc Sap San

[ ] [ ] S S
[ S
T= SBa SBb SBc , T I = Sbp Sbn and TR = Ap Bp Cp
SCa SCb SCc Scp Scn
SAn SBn SCn ]
V a Sap San

[ ][ ][ ]
Vc Scp Scn
V
V b = S bp Sbn × DC+
V DC-
(1.6)

Ia
[ ][
I DC-
=
][]
I DC+ Sap Sbp Scp
San Sbn Scn
× Ib
Ic

I A SAp S An

[ ][ ][ ]
I C SCp SCn
I
I B = SBp SBn × DC+
I DC-
(1.7)
 15

VA
V DC+ SAp SBp SCp
[ ][
V DC-
=
SAn SBn SCn ][
× VB
VC ]
The restrictions on the switch states that were analyzed in section
1.3 can now be applied to the rectifier and the inverter sections independently.
The switches of the inverter stage, associated with lines P and N in Figure 1.7,
cannot be simultaneously closed but the switches of the converter stage,
associated with lines P and N, can be closed. Equations (1.8) and (1.9)
express these restrictions mathematically.

d jPI + d jNI = 1 (1.8)

d jPR + d jNR < 1 (1.9)

For maintaining the flow of the DC bus current constant on an

average basis, the DC bus voltage on the fictitious DC bus is maintained
constant. This indicates that the input stage is a constant current source.
Similarly, for maintaining the voltage constant (for a particular modulation
index) for any load, the output stage works as a constant voltage source.

It can be assumed that the power conversion happens through the

fictitious DC-link. Because of the absence of any energy storage element in
the matrix converter, the averaged value of this DC-link voltage VDC can be
found, as shown in Equation (1.10), on the basis that the input power flow and
the DC power flow are equal at any instant.

P DC = P IN

3 I
VDC = VIN IN cos(φ in )
2 I DC

3
V DC = V IN m c cos( φin ) (1.10)
2
 16

In a similar manner, Equation (1.11) gives the fictitious DC-link

current IDC.

P DC = P OUT

3 V OUT
I DC = IOUT cos(φ out )
2 V DC

3
I DC = IOUT m v cos( φout ) (1.11)
2

From Equation (1.10), it can be seen that the DC bus voltage is a

function of the mc. To make available the maximum DC bus voltage for the
inverter stage, mc is always fixed at its maximum value.

Equations (1.12) and (1.13) express the inputs IIN, VIN and the
outputs VOUT, IOUT as space vectors.

2π 4π 2π 4π
2 2
( j j
VIN = V A + VB e 3 + VC e 3 ,
3
) ( j j
I IN = I A + IB e 3 + IC e 3
3
)
(1.12)
2π 4π 2π 4π
2 2
VOUT =
3
( j j
Va + V b e 3 + V c e 3 , ) I OUT =
3
( j j
Ia + I b e 3 + I c e 3 )
(1.13)

Tables 1.1 and 1.2 present the space vectors and the relevant
switching states of the converter and the inverter stages.

Table 1.1 Switching states and input currents for the converter stage

m SCm IA IB IC | I IN | ∠ I IN
2 π
1 [1 -1 0] I DC - I DC 0 I DC -
√3 6
2 π
2 [1 0 -1] I DC 0 - I DC I DC +
√3 6
2 π
3 [0 1 -1] 0 I DC - I DC I DC +
√3 2
 17

2 5π
4 [-1 1 0] - I DC I DC 0 I DC +
√3 6
2 5π
5 [-1 0 1] - I DC 0 I DC I DC -
√3 6
2 π
6 [0 -1 1] 0 - I DC I DC I DC -
√3 2
7 [(1, -1) 0 0] 0 0 0 0 -
8 [0 (1, -1) 0] 0 0 0 0 -
9 [0 0 (1, -1)] 0 0 0 0 -

Table 1.2 Switching states and output voltage for the inverter stage

m SIm Va Vb Vc | V OUT | ∠ V OUT

2 1 1 2 0
1 [100] V - V - V V DC
3 DC 3 DC 3 DC 3
1 1 2 2 π
2 [110] V V - VDC V DC +
3 DC 3 DC 3 3 3
1 2 1 2 2π
3 [010] - VDC V - VDC V DC +
3 3 DC 3 3 3
2 1 1 2
4 [011] - VDC V V V DC π
3 3 DC 3 DC 3
1 1 2 2 2π
5 [001] - VDC - VDC V V DC -
3 3 3 DC 3 3
1 2 1 2 π
6 [101] V - VDC V V DC -
3 DC 3 3 DC 3 3
7 [000] 0 0 0 0 -
8 [111] 0 0 0 0 -

Note: 1 in the SCm represents the upper switch in an arm being ON,
-1 in the SCm represents the lower switch in an arm being ON, (1,-1) in the SCm
represents both the switches in an arm being ON and 0 in the S Cm represents
both the switches in an arm being OFF.

An arbitrary voltage VOUT in Figure 1.8(a) can be synthesized as a

vector sum of any two adjacent active vectors (V 1 to V6) and one of the zero
vectors (V0, V7). Similarly, the input current IIN in Figure 1.8(b) can be
 18

synthesized as a vector sum of any two adjacent active vectors (I 1 to I6) and
one of the zero vectors (I0a, I0b, I0c).

Vb Vb
V2 [110] IM ejπ/2
V3 [010] Zero Vectors
I3 [01-1]
VM ejπ/3 V0 [000]
VM ej2π/3
1 V7 [111] IM ejπ/6
2 1
I2 [10-1]
2 0 V1 [100] IM ej5π/6
V4 [011] I4 [-110]
Vβdvβ VM e-j0
VM ejπ 3
Va Iβ dIβ 0 Va
3 θv VM
Vαdvα

θc IM

Iα dIα
5 5
IM e-j5π/6 4
IM e-jπ/6
4 I5 [-101]
V5 [001] Zero Vectors I1 [1-10]
V6 [101]
VM e-j2π/3 VM e-jπ/3
I0a [(1,-1)00]
Vc Vc IM e-jπ/2
I0b [0(1-1)0] I6 [0-11]

(a) I0c [00(1-1)] (b)

Figure 1.8 (a) Inverter voltage hexagon and (b) rectifier current hexagon

In general, any arbitrary vector Av, shown in Figure 1.9, can be

expressed by the vector-time product sum of the adjacent active vectors and
the zero vector as Av = d x × v x + d y × v y + d z × v z.

Vy

dyVy
AV

θAv
dxVx Vx

Figure 1.9 Representation of the vector-time product

 19

The durations of the active vectors determine the direction of the

arbitrary vector while the zero vector is used to adjust the amplitude of the
arbitrary vector. Equations (1.14) to (1.16) give the duty cycle of the active
vectors and the zero vector

Tx π
dx = = m i sin( - θAv ) (1.14)
Ts 3

Ty
dy = = m i sin ( θAv ) (1.15)
Ts

Tz
dz = = (1 - dx - dy ) (1.16)
Ts

where, θAV represents the angle of the reference arbitrary vector within that
sector, mi is the modulation index defining the magnitude of the arbitrary
vector AV.

Applying this space vector concept on the voltage vectors of the

inverter stage and the current vectors of the converter stage, Equations (1.17)
and (1.18) give the expressions for the duty cycle of the vectors to synthesize
the required output voltage and the required input current.

T vα π
d vα = = m v sin( - θ v )
Ts 3

Tvβ
d vβ = = m v sin ( θv )
Ts

T v0
d v0 = = (1 - d vα - d vβ ) (1.17)
Ts

Tcα π
d cα = = m c sin( - θc )
Ts 3
 20

Tcβ
d cβ = = m c sin ( θc )
Ts

Tc0
d c0 = = (1 - dcα - d c0 ) (1.18)
Ts

These duty cycles correspond to the ON and OFF times of the

switches of the fictitious inverter and converter circuits. Therefore, the two
independent space vector modulations should be merged into one modulation
for the nine bi-directional switched matrix converter.

The combination of the six active states of the rectifier with the six
active states of the inverter produces a set of 36 active states. These states can
be grouped into 18 pairs of equivalent states. The states in each pair are
equivalent because both connect the same input to the same output. For
example, the combination of the rectifier state m=1 and inverter state m=6
given in Tables 1.1 and 1.2 is equivalent to the combination of the rectifier
state m=4 and inverter state m=3. Both result in the connection of the output
lines a and c to the input line A and the output line b to the input line B. Both
these combinations are the same state (ABA) in matrix converter, as shown in
Figure 1.10.

A B C A B C

Sap Scp P Sbp

SAp P
SBp
N Sbn SAn N San Scn
SBn
a b c a b c
(a) (b)
SAa SAc
A
B SBb
C

a b c
(c)
 21

Figure 1.10 Switching equivalence in the conventional matrix converter

Equations (1.19) to (1.23) give the duty cycles for the matrix
converter, which are derived from the product of the inverter duty cycles and
the rectifier duty cycles (Cha 2004).

π π T vα cα
d vα cα =d vα × d cα = m v sin ( 3 ) (
- θv × m c sin - θc =
3 Ts) (1.19)

Tvα cβ
d vα cβ = d vα × dcβ = m v sin (3π - θ ) × m sin (π3 - θ ) = T
v c c
s
(1.20)

T vβ cα
d vβ cα = d vβ × d cα = m v sin ( π3 - θ ) × m sin (π3 - θ ) = T
v c c
s
(1.21)

T vβ cβ
d vβ cβ = d vβ ×d cβ = m v sin (3π - θ )× m sin (π3 - θ ) = T
v c c
s
(1.22)

T0
d 0 =1 - d vα cα - d vα cα - d vβ cα - d vβ cβ = (1.23)
Ts

1.5.2 Minimum Error Switching Strategy (MESS)

In the Minimum Error Switching Strategy (MESS), the indirect-

space vectors of the matrix converter are used for the input current control and
the output voltage control. The switching vectors are selected based on the
integrated minimum computed square of the voltage error and the integrated
minimum computed square of the current error over every sampling period.
The hysteresis current controller has a constant error band and switches from
one vector to another vector at different time intervals as and when the error
exceeds the band limits, as shown in Figure 1.11(a). The MESS technique has
a constant time band and switches from one vector to another vector at
constant time intervals, as shown in Figure 1.11 (b).
 22

Figure 1.11 Control principle (a) hysteresis and (b) MESS

The error in the MESS technique is limited by the envelope of the

minimum error among the available space vector errors at the end of each
sampling time, as shown in Figure 1.12.

Figure 1.12 Envelop of the minimum square error

The method minimizes the error between the actual output and the
expected output in a switching period by selecting the switching vector that
provides the minimum square error. In the next switching instant, the
previously calculated minimum square error is added to the present square
errors of the available space vectors, which becomes the input to the
controller that finds the appropriate minimum error switching states. The
 23

proposed switching strategy decouples the CMC into an Output Converter

(OC) and a Input Converter (IC), as explained in section 2. It selects the
appropriate switching that minimizes the square of the output voltage error for
the OC and the square of the input current error for the IC.

It is assumed that the constant average DC voltage and the constant

average DC current are available at the Fictitious DC Bus (FDCB). During
every switching period, the error quantities Vemj for the OC and Iemj for the IC
are calculated using Equations (1.24) to (1.27), and Tables 1.1 and 1.2. Since
the input current magnitude is dependent only on the load, the modulation
index mc of the IC always operates at unity. Hence, the I DC of the FDCB link
is assumed to be constant with magnitude of one and used for error
calculations of the current for the IC. VDC is determined using the selected
switching pattern of the IC and the measured input voltage, as given by
Equation (1.32), which is used for the voltage error calculations of the OC.
The switching states SIon and SCon, given in Equations (1.28) and (1.29), are
selected that correspond to the smallest of the sum of the square of the
three-phase errors and the propagated error. Finally, both the OC and the IC
switching signals are processed through a digital logic circuit for generating
the CMC switching signals

Vmj ( t ) = SIm × V DC i ( t ) , m ∈ { 1→8 } , i ∈ {+,- } & j ∈ {a,b,c } (1.24)

Vemj ( t ) = ( V rj ( t ) - V mj ( t )) + Vepj ( t ) (1.25)

I mj ( t ) = SCmT × I DC i ( t ) , m ∈ { 1→9 } , i ∈ {+,- } & j ∈ { A,B,C } (1.26)

Ie mj ( t ) = ( I rj ( t ) - I mj ( t ) ) +Iepj ( t ) (1.27)

SIon ( t ) = SIm ∈ min ∑ |Ve mj ( t ) | 2 (1.28)

m→1…8 i=a,b,c
 24

SCon ( t ) = SCm ∈ min ∑ |Iemj ( t ) | 2 (1.29)

m→1…9 i=A,B,C

Vepj ( t ) = Vemj ( t-1) ∈ SIon ( t-1 ) (1.30)

Ie pj ( t ) =Ie mj ( t-1 ) ∈ SCon ( t-1 ) (1.31)

VA
VDC =
SAp SBp SCp
[
- SAn - SBn - SCn
× VB
VC
][ ] (1.32)

where, Vmj and Imj are respectively the output voltage and the input current
corresponding to the switching matrixes S Im and SCm. Vrj and Irj denote
respectively the reference output voltage and the reference input current; Ve mj
and Iemj are respectively the output voltage error and the input current error
corresponding to switching states SIm and SCm; Vepj and Iepj are respectively
the output voltage error and the input current error due to the previous
switching state and SIon and SCon are respectively the switching matrices used
in the present switching states for the OC and the IC.

1.5.2.1 Improved current control with the MESS

Considerably high harmonic content of the input current of the

CMC is experienced with the MESS technique for lower modulation indices.
Hence, a modified MESS technique is proposed in this section to improve its
performance for low modulation indices. It is observed that the zero vectors
of the IC do not influence the input current spectrum but zero vectors of the
OC influence the input current spectrum by a considerable factor. Hence, the
error of the IC is recalculated as explained in this section. The assumption that
a constant average I DC flows in the FDCB holds good only for the active
vectors of the OC. However, for the zero vectors of the OC, the above said
 25

assumption does not hold good. This is because, with the application of the
zero vectors of the OC, the IDC becomes zero due to the isolation of the source
from the load. There is a need to recalculate the current error, which could be
used for calculation in the next sampling time. Hence, it is proposed, for the
improvement of MESS technique, to ignore the calculated current error, Ie mj(t-
1) and use Iemj(t-2), when a zero vector is applied on the OC, as given by
Equation (1.33). Figure 1.13 shows the block diagram representation of the
improved MESS technique.

Ie pj ( t ) =Ie mj ( t-1 ) ∈ SCon ( t-1)

(when the OC uses an active vector) (1.33)

Ie pj ( t ) =Ie mj ( t-2 ) ∈ SCon ( t-2)

(when the OC uses a zero vector)

Calculate current error Iem for all Calculate voltage error Vem for all
current vectors SCm voltage vectors SIm

Delay Ts Add Add Delay Ts

Select SCon corresponding to the Select SIon corresponding to the

vector with minimum current vector with minimum voltage
error error

Propagate the error of SCon and

Propagate the error of SIon
calculate VDC from Equation 1.32

Delay Ts Delay Ts

Figure 1.13 Parallel execution sequence of the MESS algorithm

 26

Figure 1.14 shows that for lower modulation indices, in the

improved MESS technique, the input current Total Harmonic Distortion
(THD) reduces by 59% when compared to the unmodified MESS algorithm.

10

8 Fundamental (50Hz) = 2.712 , THD= 10.52%

Mag (% of Fundamental)

0
0 200 400 600 800 1000
Frequency (Hz)

(a)
10

8 Fundamental (50Hz) = 2.765 , THD= 4.14%

Mag (% of Fundamental)

0
0 200 400 600 800 1000
Frequency (Hz)

(b)
Figure 1.14 Current harmonics (a) MESS technique and (b) improved
MESS technique

The proposed technique has the inherent ability of mitigating the

effects of the unbalance and the harmonics present at the input. Since the
method works on the error propagation and compensation scheme, the effects
of the unbalance and the harmonics are completely eliminated or reduced
depending on the magnitudes of the unbalance, the harmonics and the present
modulation index.
 27

To evaluate the performance of the proposed techniques, simulation

with an R–L load was performed in the MATLAB-Simulink environment for
both the ISVM and the MESS techniques. The load parameters are RL = 20 Ω,
LL = 21 mH and the converter parameters are input voltage of 100 V,
modulation index of 0.75, input frequency of 50 Hz, output frequency of
25 Hz and switching frequency of 7 kHz.

200

100
Vab(V)

-100

-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time(s)
(a)

200

100
Vab(V)

-100

-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time(s)

(b)

Figure 1.15 Simulation results of the output phase voltage (a) ISVM
technique and (b) MESS technique

Figure 1.15 shows the MESS switching states that are compared
with the ISVM switching states. It can be observed in Figure 1.16 that in the
ISVM method multiple switchings occur within the sampling frequency when
 28

compared to the MESS technique. This results in an increased switching loss,

for the same switching frequency.

Figure 1.16 Total losses in the CMC with the ISVM and the MESS
techniques

The current harmonics of the MESS are comparatively high when

compared to the ISVM technique. At higher switching frequencies, the MESS
technique has superior performance as compared to the ISVM, because the
ISVM introduces multiple pulses within the switching interval, which
increases the actual switching frequency of the device due to which the device
may fail to respond. These introduce more harmonics at the output current.

An unbalance of 20% in the phase B was introduced at 0.06 s and

the converter operates at the modulation index of 0.75. The MESS technique
mitigates the unbalance automatically without any additional computation at
the output, as seen in Figure 1.17(d)

The experiment was conducted with a balanced input voltage of

100 V, switching frequency of 7 kHz, R L = 20 Ω, LL = 21mH and modulation
index of 0.75 on a 3 kVA matrix converter prototype. The CMC was used for
 29

converting the 50 Hz input frequency to the 25 Hz output frequency using the

MESS technique, as shown in Figures 1.18 (a) to 1.18 (e). The hardware
results verify the effectiveness of the proposed MESS method for the CMC.

100
50
VABC (V)

0
-50
-100
0 0.02 0.04 0.06 0.08 0.1 0.12
Time(s)

(a)

200

100
Va ( V)

-100

-200
0 0.02 0.04 0.06 0.08 0.1 0.12
Time (s)

(b)

200

100
Vab(V)

-100

-200
0 0.02 0.04 0.06 0.08 0.1 0.12
Time(s)
 30

(c)

Figure 1.17 (Continued)

2
Iabc (A)

-4
0 0.02 0.04 0.06 0.08 0.1 0.12
Time(s)

(d)

2
IABC(A)

-2

-4
0 0.02 0.04 0.06 0.08 0.1 0.12
Time(s)

(e)

Figure 1.17 Simulation results (a) input phase voltage, (b) output phase
voltage, (c) output line voltage, (d) output current and (e)
input current
 31

(a)

(b)

(c)

Figure 1.18 (Continued)

 32

(d)

(e)

Figure 1.18 Hardware results (a) input phase voltage, (b) output phase
voltage, (c) output line voltage, (d) output current and (e)
input current

1.6 CERTAIN ISSUES IN THE MATRIX CONVERTERS

1.6.1 Over Modulation Operation of the Matrix Converter

The over modulation operation has been described as a nonlinear

operation (Holtz et al 1993) since the output waveform of the converter does
not follow the original sinusoidal reference waveform in the regions of higher
magnitudes. The over-modulation in the DC-link converters has been widely
described in the literature (Bolognani and Zigliotto 1996) but only a few
 33

papers describe the detailed effects of over modulation operation of the matrix
converter (Thuta 2007). The paper discusses four ways of operating the
matrix converter under over modulation (i) output side over modulation,
(ii) input side over modulation with power factor control, (iii) input side over
modulation without power factor control and (iv) simultaneous output and
input side over modulation. Using the over modulation technique, the
theoretical voltage limit of the converter can be increased to 105 % of the
input voltage. It has been proved in Mahlein et al (1999) that some lower
order harmonics are generated at the output voltage and the input current by
the over modulation operation (Wiechmann et al 1997). Over modulation
operation of the matrix converter might cause the resonance of the line side
filter. This might damage the converter if not controlled properly. Thus, it
was concluded in Wiechmann et al (2002) that it is not advisable to operate
the matrix converter under over modulation for a long time but for a short
period, if demanded, for the ride-through operation.

1.6.2 Ride-Through Capability of the Matrix Converter

One of the desirable characteristics of the modern drives is its

ride-through capability. This is a common solution for the drives during
power loss. During ride-through, to magnetize the motor windings and to feed
the control circuits, the drive utilizes energy from the load inertia. This is
achieved by maintaining a constant voltage in the DC-link capacitor in the
AC-DC-AC converters (Narayanan and Tanganathan 2002, Kim and Sul 2001
and Jounne et al 1999). However, the matrix converters are an array of
controlled bidirectional switches without the DC-link capacitor and these are
highly susceptible to voltage disturbances such as voltage sags, voltage swells
and momentary power interruption. A new ride-through strategy for the
matrix converter developed by Klumpner et al (2001) uses the zero vectors of
the matrix converter and the clamp circuit to ride-through small interruptions.
 34

In Wiechmann et al (2002), an alternative strategy was presented that enables

the converter to ride-through the voltage sags and enforces constant V/f
operation with the minimum reduction in the speed. Later, a new approach
was presented in Cha (2004) that modified the topology of the matrix
converter with three additional unidirectional switches and a ride-through
capacitor.

1.6.3 Unbalanced Operation and Control of the Matrix Converter

The effect of the unbalance on the converter performance is a vital

aspect in determining the overall performance of the variable speed drive,
which is fed by a converter. The matrix converter, being a direct frequency
conversion system, the unbalance at the utility side is immediately reflected
on the load side and generates unwanted lower order input/output harmonic
currents (Enjeti and Wang 1990) that may resonate with the input filter
causing damage to the converter, if uncontrolled. Therefore, research has
been directed to investigate and compensate for these effects of input voltage
disturbance. In Nielsen et al (1996), balanced and sinusoidal output voltages
were produced even when the input voltages were unbalanced. In Casadei
et al (1998) and Blaabjerg et al (2002), the input current harmonic content and
the limits of the voltage transfer ratio of matrix converter under unbalanced
conditions were determined analytically for different operating conditions. In
Zhang et al (2001) and Sunter et al (2002), the line side voltage conditions
with high order voltage harmonic components are analyzed. However, it was
concluded in all these techniques that the input current harmonics could not
be reduced when compensated for the output harmonics under abnormal
conditions of the input voltage.
 35

1.6.4 Common Mode Effects of the Matrix Converter

The high frequency common mode voltage generated in the power

converters are reported to cause potential damage to the shaft and the bearings
of the electric motors. The reduction of the common mode voltage in matrix
converters using proper switching sequence has been reported in Nguyen and
Lee (2012), Cha and Enjeti (2003). Recently, Gupta et al (2010) presented
the elimination of the common mode voltage in the matrix converter fed
open-ended induction machine.

1.7 REVIEW OF TOPOLOGY CHANGES TO THE

CONVENTIONAL MATRIX CONVERTER

1.7.1 Reduced Number of Switches

New topologies that are different from the conventional matrix

converters, named as indirect matrix converter topologies, consisting of a
rectifier/ inverter circuit without a DC-link were proposed in Ziogas et al
(1986), Kim and Sul (1993), Wiechmann et al (1985) along with their PWM
control and commutation procedures. However, these papers showed a low
quality input current waveforms. For improving the quality of the input
current, a detailed PWM control method with a synchronized switching
strategy for both the line and the load side switches was proposed in Wei and
Lipo (2001), Kolar et al (2002). Zero current commutation methods of the line
side switches were also discussed in detail in Holtz and Boelkens (1989) for
the indirect matrix converter topologies to reduce the complexity involved in
the four-step commutation of bidirectional switches in the matrix converters.
Moreover, in Kolar et al (2002) and Wei et al (2002), the possibility of
reducing the total number of semiconductor switches required for the indirect
matrix converter topology was presented. Even though constructed with
reduced number of switching devices, these converters were still able to
 36

provide unity input displacement factor, sinusoidal supply currents and load
voltages that were identical to the conventional matrix converters. These
topologies are referred as the “sparse matrix converters”. These sparse matrix
converters were classified as (i) Simple Sparse Matrix Converter (SSMC)
with 15 switches, (ii) Very Sparse Matrix Converter (VSMC) with 12
switches and (iii) Ultra Sparse Matrix Converter (USMC) with 9 switches
(Meng Yeong Lee 2009). The VSMC and the USMC were designed based on
the fact that the DC link current only flows in one direction. This constraint
makes the VSMC and the USMC not applicable for regenerative operation.

1.7.2 Multilevel Output Voltage Operation

The evolution of the multilevel inverters (Mekhilef and Kadir

2011, Aneesh et al 2009 and Celanovic 2000) brought out the importance of
the reduced voltage stresses on the power devices by using many number of
lower rating power supplies and power devices. Using the same idea in matrix
converters, a new family of converters called the Multilevel Matrix
Converters (MLMC) evolved with different concepts; i) Replacing each
bidirectional switch in CMC with n cells, each cell consisting of a capacitor
connected to the centre of the H-Bridge (Erickson et al 2006). This topology
generates multilevel output but at the cost of a more complicated circuit
configuration and modulation strategy. ii) Modifying the topology of the IMC
with additional switches which makes available two different voltage levels at
the output i.e., the phase and the line voltages (Meng Yeong Lee et al 2010).
This multilevel matrix converter topology is a hybrid combination of a
simplified three-level neutral-point clamped voltage source inverter
(Rojas et al 1993) and an indirect matrix converter topology (Ziogas et al
1986). The indirect three-level sparse matrix converter has a simpler circuit
configuration than the multilevel matrix converter topologies proposed in
 37

Meng Yeong Lee et al (2010), but was still able to generate multilevel output
waveforms. A detailed analysis of this topology was presented in Meng
Yeong Lee (2009).

1.7.3 Polyphase Matrix Converter Operation

The use of 3×6 matrix converters for a six phase induction machine
drive system was presented in Wang et al (2011), Ghalem and Azeddine
(2010). In addition to the changes in the topologies of the matrix converter,
the use of the polyphase matrix converter for innovative active generator was
demonstrated in Beguin (2012). It explained along with a prototype, the
commutation, the modulation and the control principles of a 27×3 matrix
converter.

1.8 REVIEW OF THE MATRIX CONVERTER APPLICATIONS

Neft and Schauder (1992) experimentally confirmed that a matrix

converter with only nine switches can be effectively used in the vector control
of an induction motor with high quality input and output currents. The
compactness of the matrix converter suggested the possibility to integrate the
converter and the motor in a single unit, in order to reduce the costs and to
increase the overall efficiency (Klumpner et al 2002, Itoh et al 2005). Casadai
et al (2001) used the matrix converter in the direct torque control (DTC) of
induction machines. Podlesak et al (2005) presented the field oriented-control
of the matrix converter fed induction machine.

Matrix converters find their application in the field of wind power

generation in full power converter topologies and partial converter topologies
for the doubly fed induction generators control (Zhang et al 1997, Lie Xu and
Cartwright 2006). Research on modeling and analysis of the matrix converter
 38

based wind energy systems was carried out in Barakathi (2008). Control of
the reactive power supplied by a wind energy conversion system (WECS)
based on the induction generator fed by a matrix converter was presented in
Cardenas et al (2009). An increasing number of papers (Imayavaramban and
Wheeler 2007, Wheeler et al 2003 and Lillo 2006) investigating the
advantages/ limitations of the use of matrix converters in aircrafts are also
being reported.

Today, research in matrix converter are in advanced technological

and application issues such as reliable implementation of the modified
topologies, operation under abnormal conditions and the design of matrix
converter for control of machines with more number of phases. However,
industrial applications of the converter are still limited because of some
practical issues such as difficulty in implementing complex switching
methods, common mode voltage effects, high susceptibility to input power
disturbances and low voltage transfer ratio.

The desire to use all the advantages offered by the matrix converter
has inspired me to work in this area for my PhD research. This research work
attempts to investigate the existing PWM techniques and suggest
modifications for improving the performance of the matrix converter. This
thesis focuses on devising easier methods to implement complex switching
strategies, study and mitigation of effects of the unbalance, topological
changes to increase the performance indices, proper use of the modulation
technique to eliminate the common mode voltage and a new direct torque
control procedure for the control of induction motor fed by the modified
matrix converter topology.
 39

1.9 OBJECTIVES

The main objectives of the research study are given below.

(i) To extract a variable amplitude and a variable frequency

output voltage with a relatively simple firing scheme called
the Decoupled Indirect Duty Cycle (DIDC) technique suitable
for a direct three-phase-to-three-phase matrix converter that
strives to reduce the THD and retain the target fundamental
component.

(ii) To suggest the idea of using a six-phase matrix converter in a

three-phase induction motor drive system for the elimination
of the common mode voltage and design a switching
methodology to offer a higher modulation index and a lower
THD for the output voltage.

(iii) To analyze the performance of the matrix converter for the

effects of the unbalance and the harmonics at the input and to
mitigate the effects of the unbalance using a refined firing
algorithm termed as the Harmonic Tracking Algorithm (HTA)
in a way that facilitates the reduction in THD, ensuring the
maximum possible fundamental component.

(iv) To modify the matrix converter topology, termed as the Direct

Three-Level Matrix Converter (DTMC) to reduce the output
voltage THD. To demonstrate the ISVM method for the
DTMC and its required modification to achieve reduced
voltage THD and the highest fundamental value of the output
voltage.

(v) To develop the Direct Torque Control (DTC) procedure for

DTMC fed induction motor drive and to reduce the torque
 40

ripple in the AC-to-AC converter fed induction motor drive

with input power-factor control.

1.10 THESIS ORGANIZATION

The thesis contains seven chapters summarized as follows:

Chapter 1 reviews the need for investigating the matrix converter

and developing its control methods for applying it to the AC drive system.
The role of the matrix converter as an all silicon solution in industrial drives is
explained and elucidated. This chapter enumerates the necessity to bring
about topological changes in the matrix converter to ensure better quality of
the output waveforms. In addition, the need for developing simple PWM
methods for the matrix converter for industrial use is emphasized. The chapter
also proposes a new modulation technique, suitable for high switching
frequency, which uses the minimum error switching vector. At high switching
frequencies, the power devices do not effectively respond to pulses smaller
than one-tenth of the sampling time, as in the SVPWM. This requires that the
width of the switching vector to be equal to the sampling time. In the
proposed technique, constant pulse width is offered to each vector and the
vector for the next switching period is selected based on the minimum error
switching vector. This chapter also includes the review of the literature,
research objectives, and the organization of the thesis.

Chapter 2 develops a new PWM strategy called as the Decoupled

Indirect Duty Cycle (DIDC) PWM, with a focus on providing a carrier based
technique for the operation of the matrix converter with unity displacement
factor. The main idea is to guarantee a simple and computation-less
technique, as compared to the other techniques, that modulates the matrix
converter. The matrix converter is decoupled into a fictitious converter-
inverter pair and its modeling is presented. The technique extracts the duty
 41

cycles of the CMC from the available reference signals (without the need of
processors and memory) and simultaneously executes it with a simple digital
logic circuit making it suitable for online (computation-less) implementation.
Since the duty cycles of the fictitious converter inverter pair are combined
using a digital circuit to achieve the CMC duty cycle, the input current
harmonics increase. This increase in the input current harmonics is due to the
non-coordinated inverter and converter zero vectors. To improve the
performance of the DIDC technique, the carrier frequency adjustment method
is proposed to reduce the THD in the input current. The chapter includes
simulation and experimental validation to highlight the merits of the
approach.

Chapter 3 aims to design a Rotating Space Vector Modulation

(RSVM) PWM technique that uses the zero common mode voltage vectors
(ZCMVV) to eliminate the common-mode voltage in the matrix converter.
The procedure for using the ZCMVV for input current control is also
established. The proposed RSVM technique eliminates Common Mode
Voltage (CMV) with a low voltage transfer ratio of 0.5. A modified CMC
topology, namely the Phase Shifted Dual Source Matrix Converter
(PSDSMC), is proposed to increase the voltage transfer ratio to 0.866 with the
modified RSVM technique. The performance of this scheme is evaluated
through simulation in the MATLAB-Simulink environment. The approach
involves deriving the mathematical relations for the proposed techniques. In
addition, the chapter also brings out the conditions under which the approach
fails to eliminate the common mode voltage. The simulation results portray
the usefulness and limitations of the scheme.

In Chapter 4, the mathematical analysis of the matrix converter

under unbalanced conditions is carried out and a technique to mitigate the
effects of the unbalance at the output of the matrix converter is proposed. A
 42

simple dynamic ISVM approach for the matrix converter operation for the
unbalanced and the non-sinusoidal input voltage conditions are presented.
Analyses of the effects of the unbalance on the FDCB of the CMC operated
under ISVM PWM method is carried out. An unbalanced control method for
the CMC is developed which uses the line side switching functions
(converter) to track the oscillations of the average fictitious DC bus voltage
and generate a dynamic modulation index for the load side (inverter). This
approach is based on the simple compensation of the output voltage
modulation vector with respect to the oscillating fictitious DC bus vector. The
simulated results presented bring out the effectiveness of the proposed
technique.

In Chapter 5, a new DTMC topology, which requires three

bidirectional switches of lower ratings (rated for the phase voltage) in
addition to the CMC topology, is proposed. The structure is a 4×3 matrix
converter that facilitates the increase in the output voltage levels by making
the input filter neutral point available to the load terminals. The DTMC
topology with the modified ISVM technique reduces the THD at the output.
The proposed DTMC ISVM technique uses the idea of multilevel inverter
SVM technique along with the proposed neutral current balancing strategy for
generating the firing pulses. The switching loss model for the DTMC is
developed and the performance of the DTMC is compared with that of the
CMC. The proposed DTMC ISVM technique is evaluated in simulation and
validated with a hardware prototype.

Chapter 6 develops the DTC control method for the DTMC, which
uses the input phase voltage vectors (short vectors) and the input line voltage
vectors (long vectors). In the proposed algorithm, the large vectors are applied
during torque transition states whereas the short vectors are utilized for the
steady state conditions, which results in the reduction of the torque ripples.
 43

However, the short vectors cause a serious problem of fluctuations in voltage

at the input filter capacitance. Because of this problem, we obtain an output
voltage from the DTMC that is asymmetric and having a non-zero average
value. In this chapter, a solution to minimize this fluctuation is presented,
which uses an additional voltage hysteresis band for reducing the voltage
deviation at the neutral point due to the application of the short vectors. The
performance of the DTC scheme for the DTMC is investigated through
MATLAB-Simulink based simulation over a range of speed and torque.

Chapter 7 brings out the conclusions drawn from this research.

The scope for future research in this area and the limitations of the work are
also presented. The salient features of the work and the major contributions
are summarized.
 44

CHAPTER 2

A DECOUPLED INDIRECT DUTY CYCLE PWM

TECHNIQUE FOR MATRIX CONVERTERS

2.1 INTRODUCTION

PWM control schemes are receiving increased attention for their

ability to control the harmonic content of the output voltage and/ or the input
current (Boost and Ziogas 1988, Holtz 1992). The main advantage of the
PWM technique is the flexibility with which it can be built to generate the
firing pulses.

The carrier based sine triangular PWM technique for the power
converters (choppers, inverters and multilevel inverters) is easy to implement
and widely used. The Space Vector PWM (SVPWM) techniques provide a
much higher voltage transfer ratio but require a processor and a memory for
implementation (Bose and Sutherland 1983). The comprehensive relation of
the two PWM methods provides a platform not only to transform from one to
the other, but also to develop different PWM modulators. Therefore, many
attempts have been made to unite and derive the relationship between these
two types of PWM methods in the voltage source inverters (Blasko 1997,
Holmes 1992, Bowes and Lai 1997).

Most of the PWM techniques used for modulating matrix

converters, namely Venturini, direct space vector and indirect space vector are
complex and difficult to implement. Hence, there is a need to develop a
 45

simple but superior carrier based PWM technique for matrix converters, so
that these converters can be used in the industry. A simple PWM technique
called the Decoupled Indirect Duty Cycle (DIDC) PWM technique, developed
in this chapter, incorporates the carrier PWM technique with modifications.

2.2 PROBLEM FORMULATION

The carrier based PWM technique developed in this chapter for the
CMC, reduces the complexity of the switching strategy and improves the
performance of the converter. The basic idea of the proposed DIDC PWM
technique is to reduce the computations required to calculate the duty cycle
over every switching period. The duty cycle information, extracted from the
input voltage signal and the output reference voltage signal, through a
classical analog circuit, directly generates the firing pulses. The proposed
carrier frequency adjustment method increases the performance of the DIDC
PWM technique and offers considerable improvement in the quality of the
output voltages and the input currents.

MATLAB-Simulink based simulation verifies the proposed DIDC

PWM algorithm. Hardware experimentation on the laboratory prototype
validates the algorithm.

2.3 MODULATION TECHNIQUE AND THE MATHEMATICAL

MODEL OF THE PROPOSED DIDC PWM TECHNIQUE

In order to analyze the modulation technique, a converter model is

introduced, which is valid for the ideal switches, and for the switching
frequencies much higher than the input and the output frequencies. Under
these assumptions, the higher frequency components of the variables can be
neglected, and the input/ output quantities are represented by their average
values over a cycle period, TC.
 46

The DIDC PWM technique is developed by decoupling the matrix

converter shown in Figure 1.2 into a fictitious current source rectifier (input
converter) and a fictitious voltage source inverter (output converter), as given
in Figures 2.1(a) and 2.1(b).

VDC+ VDC+
Sap Sbp Scp Sp
SAp SBp SCp Sp
VA Va
IA Ia
VB IB Ib Vb
VC IC Ic
Vc
SAn SBn SCn Sn San Sbn Scn Sn
VDC-
VDC -

Figure 2.1(a) Input converter and (b) output converter

The modulation matrix, µ for the decoupled input and output

converters is given by Equation (2.1).

µAa µAb µ Ac µI ap µI an

[ ][ ][
µ = µBa µBb µ Bc = µI bp µI bn ×
µCa µCb µCc µI cp µI cn
µCAp µCBp µCCp
µCAn µCBn µCCn ] (2.1)

Based on the modulation matrix given in Equation (2.1), the

fundamental frequency model of the CMC can be represented by dependent
current and voltage sources at the input and output terminals respectively, as
shown in Figure 2.2.
 47

Transformation matrix µ
Rf IA Lf RL LL Va Ia
VA
- +
VB IB Vb Ib
- +
IC Vc Ic
VC
- +

Input side converter (fi) Cf Output side converter (fo)

Figure 2.2 Fundamental frequency model of the CMC

2.4 INPUT CONVERTER MODELING

Equations (2.2) to (2.4) give the expected input currents at each leg
of the input converter.

I A = I m sin(ωs t + φi ) (2.2)

I B = I m sin ( ω s t + φ i - 1200 ) (2.3)

I C = Im sin ( ω s t + φ i + 1200 ) (2.4)

The duty cycle for a leg is defined as the time for which that leg
conducts from the source to load (independent of the direction of the current)
in a given sampling period. It is proportional to the absolute value of the input
reference, as given by Equations (2.5) to (2.7) and shown in Figure 2.3

DA = | sin ( ω s t + φ i ) | (2.5)

DB = | sin(ωs t + φ i - 1200 )| (2.6)

 48

D C = | sin ( ωs t + φi + 120 0 ) | (2.7)

where, DA, DB and DC are the duty cycles of each leg, which are normalized
between 0 and 1.

X Y Z
Duty cycle

DB DA DC DB DA DC

Region 1-2 Region 3-4 Region 5-6 Region 7-8 Region 9-10 Regn 11-12

Time (s)

Figure 2.3 Duty cycles of the input converter legs

Considering the input power factor to be unity, each leg conducts

for a time proportional to the magnitude of its phase voltage. For example, at
the point marked Y, in which the phase A voltage is maximum, the leg
corresponding to phase A conducts for the entire switching period while the
legs corresponding to the phases B and C conduct for half the switching
period. It is observed that the duty cycle of the leg corresponding to the phase
B reduces progressively while the duty cycle of the leg corresponding to the
phase C increases progressively, during the interval X to Z, in which the
phase A leg duty cycle is maximum. Table 2.1 shows the duty cycle variation
for each leg for different maximum conditions.

Table 2.1 Duty cycle variation in each leg of the input converter

Leg with maximum Leg with decreasing Leg with increasing

duty cycle duty cycle duty cycle
A Phase Leg B Phase Leg C Phase Leg
 49

B Phase Leg C Phase Leg A Phase Leg

C Phase Leg A Phase Leg B Phase Leg
Equations (2.8) to (2.13) give the modulation function for each
switch

µCAp = ( D A + sin( ωs t + φ i ) )/2 (2.8)

µCBp = ( DB + sin ( ωs t + φ i - 1200 ) )/2 (2.9)

µCCp = ( D C +sin ( ωs t + φ i + 1200 ) )/2 (2.10)

µCAn = ( DA - sin( ωs t + φ i ) )/2 (2.11)

µCBn = ( D B - sin(ωs t + φ i - 1200 ) )/2 (2.12)

µCBn = ( DC - sin( ω s t + φ i + 120 0 ) )/2 (2.13)

where, μCAp, μCBp and μCCp are the modulation functions of the upper
(positive) switches corresponding to the phases A, B and C respectively;
μCAn, μCBn and μCCn are the modulation functions of the lower (negative)
switches corresponding to the phases A, B and C respectively.

Except at the point Y in the region X to Z, where D A is maximum,

the input converter does not conduct current from the source to the load for a
time (1 - DA) ×TS i.e. all the legs of the converter are turned OFF for a period
of (1 - Dmax) ×TS. The algorithm is derived on the assumption that a constant
DC current flows at the output of the converter, which means that the load is
highly inductive. Hence, during the period (1 - D max) ×TS, it is necessary to
provide a freewheeling path for the inductive load currents. This is achieved
by turning ON both the switches of any one leg, as shown in Figure 2.4. This
action modifies the modulation function for each switch.
 50

VDC+ VDC+ VDC+

SAp SBp SCp SAp SBp SCp SAp SBp SCp

VA IA VA IA VA IA
IB IB VB IB
VB VB
IC IC VC IC
VC VC

SAn SBn SCn SAn SBn SCn SAn SBn SCn

VDC - VDC - VDC -

Figure 2.4 Freewheeling paths for the input converter

The leg in which both the switches are ON for a period of

(1 - Dmax) × TS is selected based on the common mode voltage reduction rule
(Cha and Enjeti 2003). This states that the leg with the minimum phase
voltage, i.e. the switches in the leg having the minimum duty cycle, should be
connected to the floating load terminal during the freewheeling of the matrix
converter. With this idea, it can be formulated that in the region X to Y, both
the switches of the leg C conduct for an additional time of (1 - D A) ×TS, since
the leg C has the minimum duty cycle. Similarly, in the region Y to Z, both
the switches of the leg B conduct for an additional time of (1 - D A) ×TS. The
duty cycles of the switches, µCDmin_p and µCDmin_n, in the leg with the minimum
duty cycle Dmin, is modified, as given by Equations (2.14) and (2.15).

µCDmin_p = µCDmin_p + (1-D max ) (2.14)

µCDmin_n = µCDmin_n + (1- Dmax ) (2.15)

Figure 2.5 shows the modified duty cycle of the switches in the leg
A. When the phase A voltage is minimum, both the switches of the leg A
conduct for an additional period of (1 - D B) in the region 1 where the B phase
voltage is maximum, and conduct for an additional period of (1 - D C) in the
region 2 where the C phase voltage is maximum.
 51

Duty cycle
Region 1 Region 2 Region 3 Region 4 Region 5 Region 6

DB DA DC

1-DB 1- DC
µCAp DA +(1-DB) DA DA DA DA DA + (1-DC)

µCAn 0 + (1-DB) 0 0 0 0 0 + (1-DC)

Time (s)

Figure 2.5 Duty cycle formulations for the input converter switches S Ap
and SAn

The modulation function for each switch of the input converter, as a

function of the leg duty cycle, is given in Table 2.2 and shown in
Figures 2.6(a) and 2.6(b).

Table 2.2 Input converter switch modulation function

Switches Regions
1 2 3 4 5 6
µCAp 1+DA-DB DA DA DA DA 1+ DA-DC
µCBp 0 0 0 1-DA 1+DB-DC DB
µCCp DC 1+DC-DB 1-DA 0 0 0
µCAn 1-DB 0 0 0 0 1-DC
µCBn DB DB DB 1+ DB-DA 1-DC 0
µCCn 0 1-DB 1+DC-DA DC DC DC
Switches Regions
7 8 9 10 11 12
µCAp 1-DB 0 0 0 0 1-DC
µCBp DB DB DB 1+ DB-DA 1-DC 0
µCCp 0 1-DB 1+DC-DA DC DC DC
µCAn 1+ DA-DB DA DA DA DA 1+DA-DC
µCBn 0 0 0 1-DA 1+DB-DC DB
µCCn DC 1+DC-DB 1-DA 0 0 0
 52

Duty cycle µCAp µCBp µCCp

0
Regions 1-2 Regions 3-4 Regions 5-6 Regions 7-8 Regions 9-10 Regn 11-12

Time (s)

Figure 2.6(a)Duty cycles of the positive switches for the input converter

1
Duty cycle

µCCn µCBn µCAn

0
Regions 1-2 Regions 3-4 Regions 5-6 Regns 7-8 Regns 9-10 Regn 11-12

Time (s)

Figure 2.6(b) Duty cycles of the negative switches for the input converter

2.4.1 Carrier Based Implementation Procedure for the Input

Converter

This section explains the carrier based PWM scheme for generating
the modulation function, for each switch, of the input converter. The input
phase voltages, the rectified input phase voltages and the triangular carrier
signal with frequency fsic, are processed using simple comparator circuits to
generate nine digital signals. The nine digital signals are (a) M 1 = A > B, (b)
M2 = B > C, (c) M3 = C > A, (d) PA = A > 0, (e) PB = B > 0, (f) PC = C > 0, (g)
LA = Trig < A, (h) LB = Trig < B and (i) LC = Trig < C, where PA, PB and PC
are the signals that indicate the polarity of the input phase voltages; L A, LB
 53

and LC are the comparator signals that are high when the magnitude of the
triangular carrier wave is less than the magnitudes of the rectified input phase
voltages. The additionally generated digital signals M A = M1 . Ḿ 3, MB = M 2 . Ḿ 1,
and M C = M3 . Ḿ2 indicate the absolute maximum of the rectified input phase
voltages; N A = M3 . Ḿ1, N B = M 1 . Ḿ 2, and NC = M 2 . Ḿ 3 indicate the absolute
minimum of the rectified input phase voltages.

A digital circuit is designed to generate the six PWM pulses for the
input converter with the help of the signals Mi, Ni, Pi and Li where i=A, B, C
and the procedure to trigger the input converter is formulated as follows.

Let i be the phase with the maximum duty cycle, j be the phase with
the decreasing duty cycle and k be the phase with the increasing duty cycle.

 If Mi=1, Li=1, and Pi=1, the switch Sip is ON; else if Mi=1,
Li=1 and Pi=0, then the switch Sin is ON.

 If Lj=1 and Pj=1, the switch Sjp is ON; else if Lj=1 and Pj=0,
the switch Sjn is ON.

 If Pk=1, Lj=0 and Li=1, the switch Skp is ON; else if Pk=0, Lj=0
and Li=1, the switch Skn is ON.

 If Li=0 and Nj=1 then switches Sjp and Sjn are ON; else if Li=0
and Nk=1 then switches Skp and Skn are ON.

Signals Li, Mi, Ni, Pi and Table 2.1 are used to design the logic
circuit for triggering the input converter.

2.5 OUTPUT CONVERTER MODELING

Equations (2.16) to (2.18) give the expected output phase voltages

between a leg and the neutral point of the load of the output converter.
 54

V a = V m sin ( ωo t + φ o ) (2.16)

V b = V m sin( ωo t + φo - 1200 ) (2.17)

V c = V m sin ( ω o t + φ o + 120 0 ) (2.18)

The duty cycle for each leg is defined as the time for which the leg
conducts from the source to load (independent of the direction of current) in a
given sampling period. Equation (2.19) gives the leg duty cycles D a, Db and
Dc, implemented with the sine PWM method.

D a = D b = Dc =1

(2.19)

Equation (2.20) gives the constraints for the inverter (output

converter), namely that the load should never be open-circuited and that the
source should never be short-circuited

µI ip + µI in = 1 (2.20)

where, i = a, b, or c, and µIip and µIin are the duty cycles of the switches, in the
upper and the lower arms respectively, of the output converter.
Equations (2.21) to (2.23) give the duty cycle of each switch in the output
converter, implemented using the sine PWM method (Wang 2006).

µI ap = (1 + sin(ωo t + φ o) ) /2 (2.21)

µI bp = ( 1 +sin (ωo t + φo - 1200) ) /2 (2.22)

µI cp = ( 1 +sin ( ωo t + φ o + 1200 ))/2 (2.23)

 55

However, the sine PWM method reduces the DC bus utilization as

V dc
it provides only as the peak value (Blasko 1996) of the locally averaged
2
phase voltage, which reduces the performance of the matrix converter. To

2
increase the DC bus utilization of the output converter by a factor , a third
√3
harmonic zero-sequence component (Houldsworth and Grant 1984 and
Holmes 1996) is used to modify the duty cycles of the legs. Equation (2.24)
gives the modified duty cycles of the legs

D a = D b = D c = 1 - Z3c (2.24)

where, Z3c is the third harmonic zero-sequence component whose shape and
offset is derived in Zhou and Wang (2002) and given by Equation (2.25)

Z3c =- ( ( 1-2K 0 ) + K 0 µImax_p + ( 1- K 0 ) µImin_p ) (2.25)

where, K0 is the ratio that denotes the sharing between the two zero vectors
V0, V7 of the inverter. Except the points at which the duty cycles of the legs
are not 1, the output converter does not conduct current from the source to the
load for a time Z3c ×Ts. This means that all the legs of the output converter are
disconnected from the source for a period Z3c ×Ts. During the turn OFF of the
converter, a definite requirement is to provide a freewheeling path to the
inductive load currents. Figure 2.7 shows that this is achieved by turning ON
all the switches in the upper or the lower arms.
 56

VDC+ VDC+
Sap Sbp Scp Sap Sbp Scp

San Sbn Scn San Sbn Scn

VDC V7 VDC V0
- -

Figure 2.7 Output converter freewheeling path for the load current

For reducing the common mode voltage in the matrix converter, the
zero vectors of the output converter are not significant, as the common mode
voltage depends only on the zero vectors of the input converter. Hence, for
ease of digital implementation, the value K 0 is chosen as 1, i.e., the vector V 7
is used in the output converter. This modifies Equation (2.25) as
Equation (2.26)

Z3c = ( 1 - µI max_p ) (2.26)

where, µImax_p = max |µIa, µIb, µIc|. Figure 2.8 shows the modified duty cycles
of the legs of the output converter.

1
Duty cycle

Da = Db = Dc = 1- Z3c

Z3c = (1- µImax_p)

Time (s)
 57

Figure 2.8 Duty cycles of the output converter leg

Equations (2.27) to (2.29) give this modified duty cycles of the

switches µI*ap , µI *bp and µI*cp , of the output converter. Figure 2.9 shows the
pictorial representation of these equations.

2
µI *ap = ((1 + sin(ω o t + φ o) ) /2) + Z3c (2.27)
√3
2
µI *bp = ((1 + sin (ω o t + φo - 1200 ) )/2) + Z3c (2.28)
√3
2
µI *cp = ((1 + sin( ω o t + φo + 1200 ))/2) + Z3c (2.29)
√3

µ ap µ ap µ cp
1
µ*ap
Duty cycle

Z3c

Time (s)

Figure 2.9 Formulation of switch duty cycle, S ap, for the output
converter

Figures 2.10(a) and 2.10(b) shows the modulation functions for

each switch of the output converter.
 58

Duty cycle µIap µIbp µIcp

0
Time (s)

Figure 2.10(a) Duty cycles of the positive switches for the output
converter

1
Duty cycle

µIan µIbn µIcn

0
Time (s)

Figure 2.10(b) Duty cycles of the negative switches for the output
converter

On superimposing the three-phase rectified waveforms |W 123|, with

the duty cycle of each switch, as shown in Figure 2.11, it is observed that the
duty cycle of each switch is the selected portions of |W123|.
Duty cycle

W2- W3+ W3- W1+ W1- W2+

W3+ & W1+ & W2- W2+ & W3- W3+ &
W1- W1-
Time (s)
 59

Figure 2.11 Duty cycles of the negative switches superimposed on the

new reference W123

This defines the duty cycle for each switch, as a function of the new
reference signals |W123|, in each distinct region, as given in Table 2.3. The new
reference signals are used in the digital implementation for generating the
switching signals of the output converter.

Table 2.3 Duty cycles for all the switches of the output converter as a
function of |W123|

Regions W1+ & W2- W2+ & W3- W3+ & W1-
Switches
µIap 1 (1- |W2|) (1- |W1|)
µIbp (1- |W2|) 1 (1- |W3|)
µIcp (1- |W1|) (1- |W3|) 1
µIan 0 |W2| |W1|
µIbn |W2| 0 |W3|
µIcn |W1| |W3| 0
2.5.1 Carrier Based Implementation Procedure for the Output
Converter

The carrier based PWM scheme for generating the modulation

function for each switch of the output converter is developed in this Section.
The output reference voltages W123, rectified output reference voltages |W 123|
and the triangular carrier signal with a frequency of fs oc are processed using
simple comparator circuits to generate the six digital signals. These are further
processed in a digital circuit to generate the six PWM pulses for the output
converter. The six digital signals are (a) P 1 = W1 > 0, (b) P2 = W2 > 0 , (c) P3 =
W3 > 0, (d) L1 = Trig < |W1|, (e) L2 = Trig < |W2|and (f) L3 = Trig < |W3|. P1,
P2, P3 are the signals that indicate the polarity of the output reference voltages;
L1, L2, L3 are the comparator signals that are High when the triangular carrier
 60

voltage is less than the rectified output phase voltages. The pulse widths of
the signals L1, L2 and L3 are proportional to |W1|, |W2|, and |W3| respectively;
the pulse widths of the signals Ĺ1 , L´ 2 , and Ĺ3 are proportional to |1 - W1|, |1 -
W2|, and |1 - W3| respectively.

R 1 = P1 . Ṕ2, R2 = P2 . Ṕ3, R3 = P3 . Ṕ1 are the signals that indicate the

distinct regions of the rectified output reference signals. With the help of the
signals Ri and Li, where i=1, 2, and 3, and Table 2.3, the logic circuit to
trigger the output converter is designed.

Finally, the switching signals for the matrix converter are extracted
from the logic circuit that combines the information of the input converter and
the output converter. The circuit generates the switching signals for the nine
switches of the conventional matrix converter, as given by Equation (2.30)
(Cha 2004).

SAa SAb SAc Sap . SAp + San . SAn Sap .SBp + San .S Bn Sap .SCp + San .SCn

[ ][
SBa SBb SBc = S bp . SAp + Sbn .S An Sbp .SBp + Sbn .SBn S bp .SCp + Sbn .SCn
SCa SCb SCc Scp . SAp + Scn . SAn Scp .SBp + Scn .SBn Scp .SCp + Scn .SCn ]
(2.30)

2.6 EASE OF IMPLEMENTATION

Venturini method uses complex mathematical expressions for

calculating the duty cycles of the switches. This increases the computation
time and requires a high-speed digital signal processor. In the proposed carrier
based method (DIDC PWM), the need for calculating the duty cycles is
avoided. The target duty cycle is constructed from a segment of the whole set
of the available rectified three-phase reference voltages and currents, by
selecting the curve that matches the target duty cycle. It has been shown
(Zhang et al 2001) that the total computation time for the Venturini method is
 61

50 µs. The proposed method requires a set of logic gates and multiplexer
circuits to generate the duty cycles, which reduces the time for generating the
firing pulses to less than 5 µs. Thus, the proposed method permits the control
of a matrix converter at higher switching frequencies than those of the
Venturini method.

2.7 CARRIER FREQUENCY ADJUSTMENT TECHNIQUE

(CFAT)

The THD of the ISVM technique of the CMC is lower as compared

to the proposed method. The switching of the output and the input converters
are coordinated in the ISVM for computing the duty cycles of the space
vectors of CMC. This requires the need for high-speed processors and makes
the implementation challenging. Since the proposed method works on the
carrier based technique, coordination through computation is not possible.
Hence, to reduce the THD, the carrier frequency adjustment technique
(CFAT) is proposed. In this method, the carrier frequency, fs ic, of the input
converter is kept different from the carrier frequency, fs oc, of the output
converter. As shown in Figure 2.12(a), for an output frequency of 20 Hz,
maintaining the same carrier frequency fsic = fsoc causes the input current THD
to be much higher than when the carrier frequencies are different
(fsic != fsoc). The THDs for various combinations of fsic and fsoc for a constant
output frequency was computed through numerical simulations until the 100 th
harmonic, using the Equation (2.31)

100
THD =
1
I1 √∑
i=2
I2i (2.31)

where, I1 and Ii are respectively the fundamental and ith harmonic components
of the output currents. The THDs for different values of fs ic and fsoc, when the
load current frequency is 20 Hz, is shown in Figure 2.12(b).
 62

5.7

THD % of Fundamental 5.6

5.5

5.4

5.3

5.2
4 6 8 10 12 14 16 18 20
Frequency (kHz)

Figure 2.12(a) THD when fsic = fsoc with fo=20 Hz

6
THD % of Fundamental

0
20 18 16 14 18 20
12 14 16
10 8 10 12
6 6 8
4 4
FCSC Carrier Frequency(kHz) FVSI Carrier Frequency(kHz)

Figure 2.12(b) THD when fsic! = fsoc with fo=20 Hz

The THD for various ratios of fsic and fsoc for varying load
frequencies is plotted in Figure 2.13(a). It is observed that the THD for all the
output frequencies is nearly the same value of 3.14%, for the ratio of input
and output carrier frequencies of 1:3/4, which is well within the acceptable
limits. Hence, to improve the THD of the input currents for a wide range of
output frequencies, in the proposed method, the switching frequencies of the
input and the output converters are chosen to be in the ratio of 1: 3/4.

The THD vs. output load current frequencies for equal input and
output carrier frequencies and THD vs. output load current frequencies for the
input and the output carrier frequency in the ratio of 1: 3/4, are given in
Figure 2.13(b).
 63

Figure 2.13(a) THD for different ratios of fsic and fsoc with varying fo

Figure 2.13(b) THD for ratios of fsic= fsoc and 3/4 fsic= fsoc with varying fo

2.8 SIMULATION

To evaluate the performance of the proposed DIDC PWM

technique, the matrix converter of Figure 1.2 has been simulated using
MATLAB-Simulink. The simulation parameters are listed in Table 2.4.
 64

Table 2.4 Simulation parameters for the DIDC PWM technique

Quantity Value
R-L Load R = 20 Ω , L = 21 mH
Input Phase Voltage 100 V
Input Voltage Frequency 50 Hz
Input Filter L = 2.5 mH, C = 10 µF, Rd = 15 Ω
Output Voltage Frequency 25 Hz
Modulation Index 0.75
Switching frequency 7 kHz

Figures 2.14(a) and 2.14(b) show the harmonic spectrum of the

input currents with and without CFAT. The harmonic spectrum of the input
currents without CFAT has high lower order harmonics whereas these lower
order harmonics are reduced with CFAT. An LC low pass filter is designed at
1 kHz cutoff frequency to improve the input current spectrum. Figure 2.15
shows the output current spectrum of the matrix converter.

5
Mag (% of Fundamental)

Fundamental (50Hz) = 35.04 , THD= 6.95%

4

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)

(a)
 65

5
Fundamental (50Hz) = 32.75 , THD= 1.84%
4
Mag (% of Fundamental)

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)

(b)

Figure 2.14 Input current spectrum at fo = 25 Hz (a) fsic = fsoc,

and (b) 3/4 fsic = fsoc

5
Mag (% of Fundamental)

Fundamental (25Hz) = 40.47 , THD= 0.56%

4

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)

Figure 2.15 Output current spectrum at fo = 25 Hz with ¾ fsic = fsoc

Figures 2.16(a) and 2.16(b) illustrate the input and the output
current waveforms for unity input power factor. It is seen that the filtered input
and output currents are nearly sinusoidal. Thus, the proposed method provides
high quality input and output currents. For a modulation index of 0.75, the
output current spectrum has a THD of 0.56% and the filtered input current
spectrum has a THD of 1.84%, as shown in Figures 2.15 and 2.14 (b). For a
lower modulation index, the method shows increased harmonic contents in the
input current spectrum while the harmonic content in the output current
 66

spectrum remains nearly the same. Figures 2.16(c) and 2.16(d) show the
output line and phase voltage.

2
IABC(A)

-2

-4
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)
(a)

Figure 2.16 (Continued)

2
Iabc(A)

-2

-4
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(b)

200

100
Vab(V)

-100

-200
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(c)
 67

200

100
Van(V)

-100

-200
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(d)

Figure 2.16 Simulation results (a) input current, (b) output current,
(c) output line voltage and (d) output phase voltage

2.9 HARDWARE IMPLEMENTATION

To validate the proposed control algorithm, a 1.5 kVA matrix

converter prototype was developed. Figure 2.17 illustrates the functional block
diagram of the laboratory prototype matrix converter setup. The individual
circuits of the DIDCPWM hardware modules are given in Appendix -3

50 Hz Bipolar Sine
Wave Reference Zero Crossing Load Current
Signals Detectors direction sensor

3 3
3

3 6SD106EI
Unipolar High Precision
Frequency Carrier CONCEPT
Rectifier FPGA
(kHz) 3 Driver Module
Module 9
Comparators
3 9
3 3
Matrix Converter
Module

Figure 2.17 Block diagram of the hardware model

 68

The setup consists of a control circuit, a CONCEPT gate driver

module (6SD106EI), a matrix converter module with bidirectional switches
(ST Microelectronics-IRFP460). The control circuit consists of an analog input
acquisition board and logic circuits, implemented using FPGA (SPARTEN3E-
XC3S500E), for generating the switching pulses for the CMC. The absolute
values of the input references are obtained from the analog acquisition board.
This board consists of zero crossing detectors, comparators and precision
rectifiers. The input references are used to obtain the duty cycle information.
A simple circuit (Imayavaramban 2008) for sensing the current direction is
used for the four-step commutation. Since the duty cycle information is readily
available in the reference, ADCs and DSPs are not required for data
acquisition and computation. The duty cycles are compared with the unipolar
high frequency carriers, as shown in Figure 2.17. The output from the
comparators is used to generate the switching information for the input and the
output converters.

Switching information and the current direction information are

processed in the FPGA for generating the switching pulses of the CMC, using
the four-step commutation. The MATLAB System Generator Toolbox
generates the FPGA code in VHDL language. The FPGA generates the firing
pulses for the matrix converter. The experiment was conducted with an input
phase voltage of 100V, switching frequency of 7 kHz, RL=20 Ω, LL=21mH
and modulation index of 0.75. The CMC was used for converting the 50 Hz
input voltage to a 25 Hz output voltage. Figure 2.18 shows the laboratory
hardware prototype. Appendix I shows the individual units of the hardware.
 69

Figure 2.18 Laboratory prototype of the matrix converter

Figure 2.19 shows the selected waveforms obtained from the

experimental results that verifies the implementation and effectiveness of the
proposed DIDC PWM technique for the matrix converter. Figures 2.19(a) and
2.19(b) show the filtered input current and output current respectively.
Figures 2.19 (c) and 2.19(d) show the output line voltage and phase voltage
respectively.

(a)
 70

(b)

(c)

(d)
Figure 2.19 Hardware results (a) input current, (b) output current,
(c) output line voltage and (d) output phase voltage

In the practical implementation of the matrix converter, the four step

commutation procedure is implemented, as discussed in chapter 1, to overcome the
problem of commutation. This technique eliminates very narrow switching pulses,
which leads to the open circuiting of the inductive load. In order to overcome this
problem, the duty cycles are recalculated. Hence, the input and the output current
waveforms for practical implementation deviate from those of the simulation as
observed in Figures 2.16(a), 2.16(b), 2.18(a) and 2.18(b).

2.10 SUMMARY

A new method was proposed to extract the duty cycle for each
switch, under unity input power factor, using the carrier based PWM
technique for the CMC. This technique avoids the need for computing the
duty cycles for switches over every sampling period. Furthermore, the
 71

method eliminates the need for ADCs, and high-speed processors, which are
required in the ISVM. In addition, the proposed method does not affect the
voltage transfer ratio.

The DIDC PWM technique shows higher harmonic content in the

input current as compared to the ISVM technique. However, the harmonic
content of the output current does not show much deviation. The proposed
CFAT decreases the input current harmonics. A ratio of 1:3/4 for the input
carrier frequency to the output carrier frequency has been identified as the
one for the THD to be the lowest, under all output frequencies of the
converter. Finally, simulation and experimental results verify the
implementation of the proposed method.
 72

CHAPTER 3

ROTATING SPACE VECTOR MODULATION

TECHNIQUE FOR MATRIX CONVERTERS TO
ELIMINATE THE COMMON MODE VOLTAGE IN
INDUCTION MACHINES

3.1 INTRODUCTION

The conventional PWM voltage applied to an induction machine

terminal results in high frequency Common Mode Voltage (CMV). The CMV
applied to the machine by the converters creates common-mode currents.
Common-mode currents have the potential to cause physical damage or
unwanted tripping of ground fault relays in motor drives and electrical
networks. In addition, research has identified damages such as frosting; spark
tracks in surface of balls, races and pitting of electric machines caused by
bearing currents that flow due to the common mode voltage (Chen et al 1996).
In a typical three-phase AC to AC drive, there exists a substantial common-
mode voltage between the load neutral and the ground due to the conventional
PWM technique (Erdman et al 1996). As the modulation frequency increases
and the zero-sequence impedance of the machine decreases, the CMV causes
higher common-mode currents, worsening Electromagnetic Interference
(EMI) problems and potentially damaging the network or the machine. Most
of the common mode voltage appears across the input transformer insulation
leading to a higher transformer insulation requirement (Gupta et al 2010).
Matrix converters have the potential to eliminate the common mode voltages,
 73

which are caused by the conventional PWM techniques, by the application of

Zero Common Mode Voltage Vectors (ZCMVV).

In this chapter, a control strategy termed as the Rotating Space

Vector Modulation (RSVM) technique that uses ZCMVV is proposed, for a
direct AC-to-AC converter fed induction machine. A control procedure that
provides input current control in the RSVM technique is also proposed.

3.2 PROBLEM FORMULATION

The aim of this chapter is to design a PWM (RSVM) technique that

uses the Zero Common Mode Voltage Vectors (ZCMVV) for elimination of
the CMV in a matrix converter. The procedure to use ZCMVV for the input
current control is also established. The proposed RSVM technique eliminates
CMV content especially at low output voltage ranges. A modified CMC
topology termed as the Phase Shifted Dual Source Matrix Converter
(PSDSMC) is proposed, to increase the voltage transfer ratio to 0.866, with
the modified RSVM technique. The performance of this scheme is evaluated
through simulation in MATLAB-Simulink. The approach involves deriving
mathematical relations for the proposed techniques. The advantages and
disadvantages of this methodology are also highlighted in this chapter.

3.3 EXISTING TECHNIQUES

Different CMV reduction techniques such as PWM based (Lee and

Sul 1999 and Videt et al 2007), active filter and passive filter based current
injection for cancellation of the common mode (Rendusara and Enjeti 1998
and Ogasawara et al 1998) have been proposed for three-phase PWM inverters.
Using the optimal zero vector selection to reduce the maximum peak of the
common mode voltage by 34%, in the CMC and the IMC fed drives, have
been proposed in Cha and Enjeti (2003), Nguyen and Hong-Hee Lee (2012).
 74

A space vector based scheme to reduce the CMV in the cascaded multilevel
inverters, has been proposed in Gupta and Khambadkone (2007). Kanchan et
al (2006) have proposed the elimination of the CMV for open-ended winding
based induction motor drives fed by a three-level inverter. Gupta et al (2010)
have proposed the same for a matrix converter. However, methods to
eliminate the common mode voltage in drives fed by a CMC without an open-
ended winding are not available in the literature.

3.4 COMMON MODE VOLTAGE EFFECTS IN THE

INDUCTION MOTOR

Figure 3.1 shows a power converter connected to an induction

machine. Due to the stray impedance Z s between the motor neutral and the
ground, the presence of the common mode voltage Vcm at the motor neutral
point contributes to a high frequency leakage current I cm. Equations (3.1) to
(3.3) give the common mode voltage Vcm at the motor neutral point.
POWER CONVERTER

Va
Cws
SOURCE

Cwr
Crs
Vb

Cwr Cwr
Vc
Cws

Cws Crs Crs

Figure 3.1 Leakage current paths in an induction machine

 75

dI a
V a - V cm = R Ia + L (3.1)
dt

dI b
V b - V cm = R I b + L (3.2)
dt

dI c
V c - V cm = R I c + L (3.3)
dt

Assuming that the stray impedance Zs is high results in Icm ≈ 0,

which results in Ia+Ib+Ic ≈ 0. Adding Equations (3.1) to (3.3), we get V cm, as
given by Equation (3.4).

Vcm = ( V a + Vb + Vc ) /3 (3.4)

3.5 MATHEMATICAL CONCEPTS FOR THE PROPOSED

RSVM TECHNIQUE

The CMC topology, shown in Figure 1.2, has been chosen in this
work, as it is the only possible converter topology where the CMV can be
eliminated. Equation (3.5) gives the expression for the source neutral voltage
VN that is zero for any three-phase three-wire balanced system.

VN = ( V A + V B + V C ) /3 (3.5)

From Equations (3.4) and (3.5), the sum of load voltages Va, Vb and
Vc should be equal to the sum of input phase voltages VA, VB and VC for the
load neutral voltage Vn to be equal to VN i.e. zero. Hence, the elimination of
the CMV introduces a third constraint in addition to the two constraints
explained in Equation (1.2), namely that at any given instant, all the three
input phases must be connected to the load. This additional constraint, used
for the elimination of the CMV, allows the use of only six switching vectors
that connects all the input phases to the output phases, as shown in
Figures 3.2(a) and 3.2(b), from the valid 27 vectors of the CMC. The
 76

remaining vectors that are not used are the 18 stationary vectors and the three
zero vectors, as shown in Figure 3.2(c). These six vectors used are termed as
the rotating space vectors since their positions in the space are not fixed. They
are also called as ZCMVV since they produce zero CMV. Among these six
rotating space vectors, three space vectors rotate in the direction of the output
frame and the remaining three space vectors rotate in the direction opposite to
the output reference frame.

Y Y
V7 ωs V4 ωs
V9 V6
X X
V8 V5
(a) (b)

V14,V17,V25 Y V10,V19,V26

V15,V16,V24 V13,V21,V22

V1, V2 ,V3 X

(c)
V11,V18,V27 V12,V20,V23

Figure 3.2 (a) Clockwise rotating vectors, (b) counter-clockwise

rotating vectors and (c) stationary vectors and zero vectors

Equation (3.6) gives the switching patterns for the counter-

clockwise rotating vectors.

SAa SAb SAc 1 0 0 0 0 1 0 1 0

[ SBa SBb SBc

SCa SCb SCc
=
0 0][ ] [ ] [ ]
0 1 0
1
or 1 0 0
0 1 0
or 0 0 1
1 0 0
(3.6)
 77

Figure 3.3(a) shows the output space vectors, when any of the three
possible switching patterns, given in Equation (3.6), are employed.

Switching space vectors rotate at input frequency ω s rad/s while the

output reference space vector rotates at ωo rad/s. Determination of the duty
cycles for the switching space vectors that rotate is tedious. Hence, the
switching vectors rotating at ωs are taken as the reference. The relative angle
θv between the output reference voltage vector angle θ o and the actual
switching voltage space vector angle θ s is computed and used for duty cycle
calculations. Figure 3.3(b) illustrates the same. Equations (3.7) to (3.10) give
the positions of the active switching voltage vectors and the reference output
voltage vector in space

3
v abc+ = V i e jω t s
(3.7)
2
2π
3 j(ω t + )
v cab+ =
s
3
Vi e (3.8)
2
2π
3 j(ω t- )
v bca + =
s
3
Vi e (3.9)
2

3
vo = V o e jω t o
(3.10)
2

where, v abc + , v cab+ , v bca + are the active vectors with magnitude V i and vo is the
reference output vector with magnitude Vo.

Y
Y
vcab+ vcab+
(ωo - ωs)
VREF
ωo vabc+ VREF )
θv = (θ0 - θs) X
θS ωs X
θO vabc+
Mi_max=0.5

vbca+ (a) (b)

vbca+
 78

Figure 3.3 Dynamic space vector PWM (a) positive sequence rotating
reference frame and (b) fixed reference

Equations (3.11) to (3.14) give the duty cycles of the active vectors
and the zero vectors obtained by the sine law of triangles, as shown in
Figure 3.4.

d α vα dβ v β V o(REF)
o
= = (3.11)
sin ( 120 - θ v ) sin ( θv ) sin ( 60o )

d α = m v sin (120˚-θv ) (3.12)

d β = m v sin ( θv ) (3.13)
d0= 1 - dα - dβ (3.14)

y
ωo vβ
vβ
Vo(REF)
120˚ Vo(REF)
θv 120˚-θv
ωs x
60˚ dβvβ
θv
vα
(a)
dαvα vα
(b)

Figure 3.4 Duty cycle calculation (a) sector 1 and (b) weighted
combination of the active vectors

The conventional SVM technique utilizes zero vectors for the

sinusoidal output but in the proposed RSVM technique, the use of the zero
vectors introduces common mode voltage. Equations (3.7) to (3.9) show that
dm v abc+ + d m v cab+ + d m v bca + =0, where dm is some arbitrary duty cycle. This idea
is used to implement the zero vectors using the active rotating vectors. During
 79

the switching time of the zero vector, the RSVM technique uses all the three
active vectors with equal duty ratios. Equations (3.15) to (3.17) give the
modified duty ratios for the RSVM technique.

+ ' o d0
d 1 =d α = m v sin (120 - θv )+ (3.15)
3

+ ' d0
d 2 = dβ = m v sin ( θv ) + (3.16)
3

+ ' d0
d 3 = d0 = (3.17)
3

Hence, within any given sector, the required output can be

synthesized over a sampling period by applying the respective active rotating
vector, as given in Table 3.1. Equation (3.18) gives the relation between the
output voltage v oand the active vectors, whose duty ratios satisfy
Equation (3.19) at all times

v o = d 1+ v1 + d2+ v 2 + d 3+ v 3 (3.18)

d 1+ +d 2+ + d3+ = 1 (3.19)

where, d1+, d2+, d3+ are the duty cycles and v1, v2, v3 are the active positive
rotating vectors respectively.

Table 3.1 Positive rotating switching vectors and sector no. for the CMC

S. No. θv Sector No Active vectors

v1 v2 v3
1 0o < θv ≤ 120 o 1 v abc+ v cab+ v bca +
2 120o < θv ≤ 240 o 2 v cab+ v bca + v abc+
3 240o < θv ≤ 360o 3 v bca + v abc+ v cab+
 80

Substituting Equations (3.7) to (3.10) in Equations (3.18) and

(3.19), the duty cycle of each switch is obtained, as in Equations (3.20) to
(3.22). However, the modulation index mv of this method is limited to 0.5.

1 2 mv
D Aa = DBb = D Cc = + cos (ω o t - ωs t) (3.20)
3 3

1 2 mv 2π
D Ba = D Cb = D Ac = + cos ((ωo t - ωs t) + )
3 3 3
(3.21)

1 2 mv 2π
D Ca = D Ab = D Bc = + cos ((ωo t - ωs t) - )
3 3 3
(3.22)

With a similar procedure, the same output voltages can be

synthesized using three negative rotating active space vectors whose duty
ratios are given by Equations (3.15) to (3.17). Within any given sector, the
required output can be synthesized by applying the respective active rotating
vector, as given in Table 3.2.

Table 3.2 Negative rotating switching vectors and sector no. for the CMC

S. No. θv Sector Active vectors

No v1 v2 v3
o o - - -
1 0 < θv ≤ 120 1 v acb v bac v cba
2 120o <θ v ≤ 240o 2 v bac - v cba- v acb-
3 240o <θ v ≤ 360o 3 v cba- v acb- v bac -

3.6 INPUT POWER FACTOR CONTROL OF THE RSVM

TECHNIQUE
 81

Input power factor control in the direct AC-to-AC converters

(Milanovic and Dobaj 2000) is carried out using the principle of the space
vector technique applied to the input current but the RSVM technique uses the
shared duty ratio control technique for achieving the same. At any instant,
based on the applied active voltage space vector at the output, any of the input
phase currents (say ia(t)) should be equal to any one of the output phase
currents (say iA(t), iB(t) or iC(t)). Equations (3.33) to (3.36) give the positions
of the active output current vectors, when using the corresponding positive
directional rotating voltage vectors and the input current vectors in space.

+ 3 j (ω t-ρ)
i abc = I e o
(3.33)
2 o
2π
+ 3 j (ω t-ρ +o
3
)
i cab = Io e (3.34)
2
2π
+ 3 j(ω t-ρ-
3o )
i bca = Io e (3.35)
2

3
is = I e j(ω t-ρ)
s
(3.36)
2 o

Equations (3.37) to (3.40) give the positions of the active output

current vectors, when using the corresponding negative directional rotating
voltage vectors and the input current vectors in space.

3
i acb- = Io e - j (ω t-ρ)
o
(3.37)
2
2π
3 -j (ω t-ρ + )
i bac- =
o
3
Io e (3.38)
2
2π
3 - j(ω t-ρ- )
i cba - =
o
3
Io e (3.39)
2

3
is = I o e j(ω t+ρ)
s
(3.40)
2
 82

Equations (3.36) and (3.40) show that the input current lags or leads
respectively the input voltage by ρ degrees when positive or negative
directional voltage vectors are applied, where cos ρ lagging is the output load
power factor, as shown in Figure 3.5(a). Since the output power factor
depends upon the load, it is not possible to control the output power factor.
Hence, the only way to control the input power factor cos  is to apply both
+ve and -ve rotating voltage space vectors at the output terminals, as shown in
Figures 3.5(b) to 3.5(d). Equation (3.50) gives the ratio r with which the +ve
and –ve rotating voltage space vectors are applied to decide the input power
factor. However, the input power factor can be controlled in a limited range
between the output power factor and unity i.e. cos ρ < cos  < 1.
Equations (3.41) to (3.49) give the duty cycles of each switch.

1 2r m v 2(1-r) m v
D Aa = + cos ( ωo t- ωs t ) + cos ( ω o t+ωs t ) (3.41)
3 3 3

1 2r m v 2π 2(1-r) m v 2π
D Ba = + cos ( ( ω o t- ωs t ) + )+ cos ( ( ω o t+ ωs t ) - ) (3.42)
3 3 3 3 3

1 2r m v 2π 2(1-r) m v 2π
D Ca = + cos ( ( ωo t-ω s t ) - )+ cos ( ( ωo t+ω s t ) + ) (3.43)
3 3 3 3 3

1 2r m v 2(1-r) m v 2π
D Bb = + cos ( ω o t- ωs t ) + cos ( ( ωo t+ω s t ) + ) (3.44)
3 3 3 3

1 2r m v 2π 2(1-r) m v
D Cb = + cos ( ( ω o t- ω s t ) + )+ cos ( ωo t+ω s t ) (3.45)
3 3 3 3

1 2r m v 2π 2(1-r) m v 2π
D Ab = + cos ( ( ω o t- ωs t ) - )+ cos ( ( ω o t+ ωs t ) - ) (3.46)
3 3 3 3 3

1 2r m v 2(1-r) m v 2π
D Cc = + cos ( ωo t- ωs t ) + cos ( ( ωo t+ω s t ) - ) (3.47)
3 3 3 3
 83

1 2r m v 2π 2(1-r) m v 2π
D Ac = + cos ( ( ω o t- ω s t ) + )+ cos ( ( ωo t+ ωs t ) + ) (3.48)
3 3 3 3 3

1 2r m v 2π 2(1-r) m v
D Bc = + cos ( ( ωo t-ω s t ) - )+ cos ( ω o t+ ωs t ) (3.49)
3 3 3 3

y
Vs ωs
Is+

Is- ωs ρ
ρ ω0
Vo (REF)
ρ ω0
Io x (a)

ωs ωs ωs
Is+ Is+ Is+

d+ Is+
d+ Is+ d+ Is+
ρ Is θ
ρ θ ρ ρ
Vs Vs Vs
d- Is- Is d- Is- d- Is- Is

Is- Is- Is-

(b) (c) (d)

Figure 3.5 Input power factor control (a) input current positions,
(b) lagging power factor (d+ < d-), (c) unity power factor (d+
= d-) and (d) leading power factor (d- < d+)

Let T+ be the time for which the positive rotating space vectors are
applied and T- be the time for which the negative rotating space vectors are
applied, within a given sampling time Ts. The respective duty ratios are d+ and
 84

d- and they satisfy the relation d + + d- =1 at all times. Equation (3.50) gives
the input power angle θ.

θ= tan -1 [ ( 1-2 d + ) tan ρ ] (3.50)

3.7 RSVM TECHNIQUE FOR THE PSDSMC

The RSVM technique for the CMC uses only three vectors with the
modulation index limited to 0.5, which is a major limitation of the RSVM
technique. The shortcoming of this technique is overcome by using a 6×3
CMC consisting of two 3×3 CMCs [MC x , MC y] fed by a three-phase center-
tapped transformer. The transformer produces 180° shifted space vector
pattern by generating a six-phase supply, as shown in Figure 3.7. In the
proposed topology, the modulation index is extended to 0.866 with the help of
the newly available three space vectors, as shown in Figure 3.6.
Equations (3.51) and (3.52) give the six switching patterns for the counter-
clockwise rotating space vectors, where all the elements of the SMC_x are equal
to 0 if any one switching sequence of the SMC_y is applied. Similarly, all the
elements of the SMC_y are equal to 0 if any one switching sequence of the SMC_x
is applied.
 85

Y
vcab+x vbca+y

ωo
VREF

θv X

vabc+y ωs vabc+x

Mi_max=0.866

vbca+x vcab+y
(a)

Figure 3.6 (Continued)

Y
vbac-x vcba-y

ωo
VREF

θv X

vacb-y ωs ωs vacb-x

Mi_max=0.866

vcba-x vbac-y
(b)

Figure 3.6 Space vector distribution of the PSDSMC (a) +ve sequence
vectors and (b) -ve sequence vectors
 86

SAax SAbx SAcx

VA

SAay SAby SAcy

MCx SBax SBbx SBcx

VB

SBay SBby SBcy MCy

SCax SCbx SCcx

VC

SCay SCby SCcy

Ia Ib Ic

Van Vbn Vcn

Figure 3.7 Phase shifted dual source matrix converter

SAax SAbx SAcx

SMC
x

[
= SBax SBbx SBcx
SCax SCbx SCcx ]
1 0 0 0 1 0 0 0 1

[ ] [ ] [ ]
= 0 1 0 or 0 0 1 or 1 0 0
0 0 1 1 0 0 0 1 0
(3.51)

SAay SAby S Acy

SMC
y

[
= SBay SBby SBcy
SCay SCby SCcy ]
1 0 0 0 1 0 0 0 1

[ ] [ ] [ ]
= 0 1 0 or 0 0 1 or 1 0 0
0 0 1 1 0 0 0 1 0
(3.52)
 87

Equations (3.53) to (3.59) give the positions of the active switching

voltage space vectors and the reference output voltage space vector

3
v abc+ x = V i e jω ts
(3.53)
2
2π
+ 3 j(ω t +
3 s )
v cab x = Vi e (3.54)
2
2π
+ 3 j(ω t-
3 s )
v bca x = Vi e (3.55)
2

3
v abc+ y = V e j(ω t+π) s
(3.56)
2 i
π
3 j(ω t- )
v cab+ y =
s
3
Vi e (3.57)
2
π
+ 3 j(ω t +
3 s )
v bca y = Vi e (3.58)
2

3
vo = V o e jω t
0
(3.59)
2

where, v abc+ x , v cab+ x , v bca + x and v abc+ y , v cab+ y , v bca + y are respectively the
active positive rotating switching vectors corresponding to SMC_x and SMC_y
respectively. Vi and Vo are the magnitudes of the input and the output space
vectors respectively. The duty cycles of the active vectors and the zero vector
are computed using the sine law of triangles, as explained in section 2, and
given by Equation (3.60).

d α = m v sin ( 60o - θv ) , d β = m v sin ( θv ) , d 0 = 1- dα - d β (3.60)

As explained in section 2, this technique does not utilize zero

vectors. From Equations (3.53) to (3.59), it can be shown that
dm v abc+ x + d m v abc+ y =0, where dm is some arbitrary duty cycle. To achieve the
sinusoidal output and to eliminate the common mode voltage, RSVM
 88

technique utilizes two opposite active vectors in equal ratio within the time
for zero switching that modifies the duty ratios, as given by Equation (3.61).

+ + d0 + d0
d 1 =d α , d2 = dβ + , d3 = (3.61)
2 2

Hence, within any given sector, the required output can be

synthesized by applying the respective active rotating vectors, as given in
Table 3.3. Equation (3.62) gives the relation between the output voltage v o
and the active vectors.

v o = d1+ v 1 + d 2+ v 2 + d 3+ v 3 (3.62)

Table 3.3 Positive rotating switching vectors and sector no. for the
PSDSMC

S. No. θv Sector Active vectors

No. v1 v2 v3
1 0o <θ v ≤ 60o 1 v abc+ x v bca + y v bca + x
o o + + +
2 60 <θ v ≤ 120 2 v bca y v cab x v cab y

3 120o <θ v ≤ 180o 3 v cab+ x v abc+ y v abc+ x

o o + + +
4 180 <θ v ≤ 240 4 v abc y v bca x v bca y
o o + + +
5 240 <θ v ≤ 300 5 v bca x v cab y v cab x

6 300o <θ v ≤ 360o 6 v cab+ y v abc+ x v abc+ y

As described in section 2, the same output voltage can be obtained
by using the negative rotating space vectors, as shown in Figure 3.6(b).
Within any given sector, the required output can be synthesized by applying
the respective active rotating vectors, as given in Table 3.4.

Table 3.4 Negative rotating switching vectors and sector no. for the
PSDSMC

S. No. θv Sector No. Active vectors

v1 v2 v3
1 0o <θ v ≤ 60o 1 v acb- x v cba- y v cab- x
 89

2 60o <θ v ≤ 120 o 2 v cba- y v bac - x v bca - y

o o - - -
3 120 <θ v ≤ 180 3 v bac x v acb y v acb x

4 180o <θ v ≤ 240o 4 v acb- y v cba- x v cba- y

o o - - -
5 240 <θ v ≤ 300 5 v cba x v bac y v bac x

6 300o <θ v ≤ 360o 6 v bac - y v acb- x v acb- y

In a similar manner, as described in Section 2, the ratio in which the

+ve and –ve rotating voltage space vectors are applied decides the input
power factor at the primary of the center tapped transformer, as given by
Equation (3.50).

It is also observed that the input power factor control reduces the
magnitude of the input current, as shown in Figure 3.8, by a factor given in
Equation (3.63)

|I s_c| cos ρ
+
= (3.63)
|I | s cos ( tan -1 [ ( 1-2 d+ ) tan ρ ])

where, |Is_c| and | Is+| are respectively the peak magnitude of the controlled
input current and the peak magnitude of the uncontrolled input current of the
CMC.

ωs
V Is+
Magnitude

d+ Is+
I+s ρ Is_c
I-s

Is_c ρ Vs
d- Is-
- ρ-- ρ- Time (s)
Is- (b)
(a)

Figure 3.8 Input current magnitude for unity power factor

(a) instantaneous and (b) vector
 90

From Equation (3.63), it is observed that the modulation index at

the output of the matrix converter reduces by the same factor, as described in
Equation (3.64).

cos ρ (3.64)
m v_c = mv
-1 +
cos ( tan [ ( 1-2 d ) tan ρ ] )

3.8 UNBALANCE AND HARMONIC ANALYSIS OF THE

RSVM TECHNIQUE

From Equation (3.5), it can be seen that when unbalanced inputs are
applied to the CMC or the PSDSMC, the RSVM technique does not eliminate
the CMV. For the inputs containing homopolar harmonics, the RSVM
technique fails to eliminate the CMV, as homopolar harmonics introduce a
zero sequence component. However, the magnitudes of the CMV introduced
under such conditions are very low and that they do not affect the system very
seriously. The RSVM technique is unaffected by non-homopolar harmonics
since they do not introduce a zero sequence component in the system.

3.9 SIMULATION

Simulation of the CMC and the proposed PSDSMC was carried out
using mathematical models, as shown in Figures 3.9 and 3.10, and also
verified using ideal switches. The system parameters used in the simulation
were: Supply – 220 V, 50 Hz, Load – R=5Ω, L=12 mH, cos ρ = 0.8 at 25 Hz
output frequency and switching frequency of 7 kHz. The input filter
capacitance and inductance were designed to be C f =10 μF and Lf =1 mH with
a damping resistor rd = 15Ω for filtering the higher order frequencies very
near to the switching frequency.
 91

Ia
VA IA
VaN

SAa SBa SCa

SAa SAb SAc Vcm VbN
1/3 Ib
VB
IB

SAb SBb SCb

SBa SBb SBc
VcN Ic
VC

IC

(a) SAc SBc SCc

(b)
SCa SCb SCc

Figure 3.9 Mathematical model of the CMC (a) voltage model and
(b) current model

The mathematical model of the PSDSMC is implemented using

two three-phase AC voltage regulators connected to a single matrix converter,
as shown in Figure 3.10. Although this topology reduces the switch count by
three, it operates with three additional devices during conduction, which
increases the conduction losses by 100%. Figure 3.11 shows the block
diagram for implementing the RSVM technique.

SACVR_1

VA
VaN

VA’

VB SAa SAb SAc Vcm

VbN
1/3

VB’

SBa SBb SBc

VC

VcN

VC’

SACVR_2 SCa SCb SCc

(a)
 92

IA
Ia
IA’

SAa SBa SCa

IB
Ib
IB’

SAb SBb SCb

Ic
IC

IC’

SAc SBc SCc

(b)
SACVR_1 SACVR_2

Figure 3.10 Mathematical model of the PSDSMC (a) voltage model and
(b) current model

Figures 3.12 and 3.13 show the simulation results of the CMC
controlled by the RSVM technique without and with current control
respectively. Figures 3.14 and 3.15 show the simulation results of the
PSDSMC controlled by the RSVM technique without and with current control
respectively. Figures 3.3 and 3.6 show that the modulation index of the
PSDSMC controlled by the RSVM technique increases by 73.2% as
compared to modulation index of the CMC controlled by the RSVM
technique.
 93

Output Reference 3(3) θo, θi+ ,θi- θv+

Sector
abc to αβ Identification
+ve sequence input θv-
Reference & Duty cycle
αβ to Theta within
calculation
a Sector
-ve sequence input d1+, d2+,
Reference Comparator Duty cycle d3+
R-1 calculation
d1-, d2-,
d3-
R

Vector Selection
Timing V1+, V2+, V3+

Vectors
Matching Vector Selection
V1-, V2-, V3-

Switching Pulses

Figure 3.11 Block diagram of the proposed current controlled RSVM

technique

Figure 3.15(f) shows the increased modulation index of the

PSDSMC as compared to the CMC in Figure 3.13(f). The peak magnitude of
the load current in PSDSMC increases by approximately 73%.

40
V A /8 (V ) , IA (A )

20

-20

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(a)
Figure 3.12 (Continued)
 94

400

Vab(V) 200

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(b)
400

200
Va(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)
(c)
400

200
Vab(V)

-200

-400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(s) x 10
-3

(d)
20
IA(A), IB(A), IC(A)

10

-10

-20
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(e)
Figure 3.12 (Continued)
 95

20

Ia(A), Ib(A), Ic(A) 10

-10

-20
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(f)
Figure 3.12 RSVM technique for the CMC without current control (a)
input current and voltage respectively, (b) output line
voltage, (c) output phase voltage, (d) output line voltage
magnified, (e) input currents and (f) output currents
40
V A /8(V ) , IA (A )

20

-20

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)
(a)
400

200
Vab(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)
(b)
400

200
Va(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(c)
Figure 3.13 (Continued)
 96

400

200
Vab(V)
0

-200

-400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(s) x 10
-3

(d)
20
IA(A), IB(A), IC(A)

10

-10

-20
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(e)
20
Ia(A), Ib(A), Ic(A)

10

-10

-20
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(f)

Figure 3.13 RSVM technique for the CMC with current control (a)
input current and voltage respectively, (b) output line
voltage, (c) output phase voltage, (d) output line voltage
magnified, (e) input currents and (f) output currents

Figures 3.12(d), 3.13(d), 3.14(d) and 3.15(d) show that the output
voltage consists of three levels when the positive rotating vectors are applied
while it consists of six levels when both the positive and the negative vectors
are applied. This indicates that the number of switching states increases with
 97

the current control technique. Figures 3.12(a), 3.13(a), 3.14(a) and 3.15(a)
show that the input peak current reduces approximately by the factor given by
the Equation (3.30).

100
VA/4 (V), IA(A)

50

-50

-100
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(a)
400

200
Vab(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(b)
400

200
Va(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(c)

Figure 3.14 (Cotninued)

 98

400

200
V ab (V )
0

-200

-400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(s) x 10
-3

(d)
40

20
IA(A), IB(A), IC(A)

-20

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(e)
40
Ia(A), Ib(A), Ic(A)

20

-20

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(f)

Figure 3.14 RSVM technique for the PSDSMC without current control
(a) input current and voltage respectively, (b) output line
voltage, (c) output phase voltage, (d) output line voltage
Magnified, (e) input currents and (f) output currents
 99

100

50
VA/4 (V) , IA(A)

-50

-100
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(a)
400

200
Vab(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(b)

400

200
Va(V)

-200

-400
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(c)

Figure 3.15 (Cotninued)

 100

400

200
Vab(V)
0

-200

-400
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(s) x 10
-3

(d)
40
IA(A), IB(A), IC(A)

20

-20

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(e)
40
Ia(A), Ib(A), Ic(A)

20

-20

-40
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Time(s)

(f)

Figure 3.15 RSVM technique for the PSDSMC with current control
(a) input current and voltage respectively, (b) output line
voltage, (c) output phase voltage, (d) output line voltage
magnified, (e) input currents and (f) output currents

From Figures 3.3 and 3.6, it can be observed that for the CMC and
the PSDSMC the space vectors are distributed by 120 o and 60o respectively.
Due to this, the maximum voltage stresses on the devices during the
 101

commutation for the CMC and the PSDSMC are √3*Vm and Vm respectively.
Hence, it can be inferred that during commutation the devices in the CMC
topology are subjected to higher voltage stresses.

Figure 3.16 (a) shows the CMV induced due to the ISVM technique
in the CMC and Figure 3.16 (b) shows the elimination of the CMV by the
RSVM technique for both the CMC and the PSDSMC. The peak of the CMV
can be as high as the magnitude of the input phase voltage in the ISVM
technique. This has been eliminated in the proposed RSVM technique along
with the input current control.

200
Vcm (V)

-200

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time(s)

(a)

300
200
100
Vcm(V)

0
-100
-200
-300
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time(s)

(b)

Figure 3.16 Common mode voltage (a) ISVM technique for the CMC
and (b) RSVM technique for the CMC (or) the PSDSMC
 102

Figure 3.17(a) shows that an unbalance of 4.3% in the B phase of

the input voltage is applied to the CMC and the PSDSMC. Figure 3.17(b)
illustrates that a low magnitude, low frequency CMV, proportional to the
magnitude of the unbalance, is present in the CMC. However, Fig. 3.17(c)
indicates that in the PSDSMC, a low magnitude, high frequency CMV is
introduced by the space vectors of the phase shifted matrix converter.

200
100
VABC (V)

0
-100
-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time (s)

(a)
100

50
Vcm (V)

-50

-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time (s)

(b)
100

50
Vcm (V)

-50

-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Time (s)

(c)

Figure 3.17 (a) Unbalanced input voltage, (b) CMV of the CMC and
(c) CMV of the PSDSMC
 103

Figure 3.18(a) shows a third harmonic (homopolar) component

injected at the input from 0.04 s to 0.08 s and a second harmonic (non-
homopolar) component injected from 0.08 s to 0.12 s. Figures 3.18(b) and (c)
indicate the elimination of the CMV for the non-homopolar harmonics while
the homopolar harmonics introduce a CMV due to the zero sequence voltage.

200
V A B C (V )

100

-100

-200
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Time (s)

(a)
100

50
Vcm (V)

-50

-100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Time (s)

(b)
100

50
Vcm (V)

-50

-100
0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16
Time (s)

(c)

Figure 3.18 (a) Non-sinusoidal input voltage, (b) CMV of the CMC and
(c) CMV of the PSDSMC
 104

As the number of branches increases, as in the case of the

PSDSMC, the current and voltage stresses are shared among the branches
equally, hence reducing the stresses on each device and extending the life of
the device. If one of the arms fails to conduct, the PSDSMC can be made to
operate as a CMC with reduced CMV by optimal vector selection in the
ISVM technique. Considering the economic aspect, this solution for the CMV
elimination seems to be costly. However, with the growth of the power
electronics technology, the cost of the devices is expected to come down.
Although the design looks expensive, it can be used where CMV elimination
is essential.

3.10 SUMMARY

The PSDSMC topology has twice the number of switches as

compared to the CMC topology. However, it is the only possible
configuration to eliminate the common mode voltage with an increased
modulation index of 0.866 in the direct AC-to-AC converters fed machines. It
is found that in the RSVM technique, current control can be carried out using
both the positive and the negative rotating vectors. RSVM technique also
eliminates the CMV for the inputs having non-homopolar harmonics.
However, it does not eliminate the CMV for unbalanced inputs or inputs with
homopolar harmonics.

The input current control range of the PSDSMC and the CMC is
limited from unity power factor to output power factor. In the current
controlled technique for the PSDSMC and the CMC, the modulation index
reduces further. It is also found that the switching stresses of the individual
switches reduce in the PSDSMC as compared to the CMC because of the
additional states introduced in the PSDSMC topology. Hence, the proposed
PSDSMC modulated by the RSVM technique can be used for the elimination
of the CMV in electrical machines with a higher modulation index.
 105

CHAPTER 4

ANALYSIS AND SIMPLIFIED CONTROL OF THE

MATRIX CONVERTER UNDER UNBALANCED
INPUT CONDITIONS

4.1 INTRODUCTION

Voltage unbalance is a power quality problem of significant

concern at the electricity distribution level. An excessive level of voltage
unbalance can have serious impact on mains connected induction motors. The
level of the current unbalance that is present is several times that of the level
of the voltage unbalance. Such unbalance in the line currents can lead to
excessive losses in the stator and the rotor, which may cause protection
systems to operate, causing loss of power production. Although induction
motors are designed to tolerate a small level of unbalance, they have to be
derated. If the unbalance is excessive and if operated at the nameplate rated
capacity without derating, the useful life of such induction motors is reduced.
However, there are utility system level mitigation techniques and plant level
mitigation techniques that can reduce the voltage unbalance and its effects.

Because the CMC is a direct frequency conversion system, the

unbalance at the utility side is immediately reflected on the load side, which
will generate unwanted input /output harmonic currents (Enjeti and Wang
1990). The effect of the unbalance on the converter performance is important
to determine the overall performance of the variable speed drive that is fed by
the converter. Several techniques that improve the performance of the CMC
 106

under unbalanced input voltage have been reported in the literature (Casadei
et al 1998, Blaabjerg et al 2002, Zhang et al 2001 and Sunter et al 2002).
However, a simple fictitious DC bus (FDCB) based analysis of the unbalance
and the technique for mitigating the effects of the unbalance has not been
reported for the CMC. An unbalance control method for the CMC is
developed in this chapter. The output of the converter remains balanced with
the input current being distorted.

4.2 PROBLEM FORMULATION

A simple dynamic ISVM approach for the matrix converter

operation for unbalanced and non-sinusoidal input voltage is presented.
Analyses of unbalance effects on the FDCB of CMC operated under ISVM
PWM method is carried out. An unbalance control method for the CMC is
developed by tracking the oscillations of the fictitious average DC bus voltage
from the switching functions of the line side and generating a dynamic
modulation index for the load side. In this approach, the output voltage
modulation vector is compensated based on the oscillations in the FDCB. The
validity of the tracking algorithm approach is verified through
MATLAB/Simulink simulation.

4.3 DYNAMIC MODEL OF THE MATRIX CONVERTER AS A

TWO STAGE CONVERTER

The CMC can be described by an equivalent circuit that consists of

a current source rectifier and a voltage source inverter connected through a
virtual DC link (Huber and Borojevic 1989), as given in Figure 1.7. For
observing the dynamics of the FDCB voltage under unbalanced conditions,
the direct transformation matrix D (Barakati et al 2007) is decomposed into
two matrixes DI (ωo ) and DR (ωs ), as given in Equation (4.1). Equation (4.2)
gives the fictitious DC bus voltage VDC.
 107

T
sin ( ω o t+ φo ) sin ( ωs t- φi )

D= m c m v

[ ][ ]
( 2π
3 )
sin ωo t+φ o -

2π
sin ( ω t+φ + )
o
3 o
× ( 2π3 )
sin ωs t- φ i -

s
2π
sin ( ω t- φ + )
3 i
(4.1)

T
sin ( ωs t- φi ) Vam sin ( ω s t )

VDC = m c

[ ][ ]
( 2π3 )
sin ω s t- φ i -

2π
sin ( ω t- φ + )
s i
3
×

Vcm
( 2π3 )
V bm sin ωs t-

s
2π
sin ( ω t+ )
3
(4.2)

Under balanced condition, substituting Vam = Vbm = Vcm = Vm and

mc = 1 in Equation (4.2), Equation (4.3) is obtained that gives the FDCB
voltage.

V DC = 1.5× V m × cos ( φ i ) (4.3)

4.4 EFFECT OF THE INPUT UNBALANCE ON THE

FICTITIOUS DC BUS

Disturbances at the inputs introduce oscillations on the FDCB. Any

i th harmonic at the input can be decomposed into two components, namely
(i - 1) ωs t and (i + 1) ωs t. Considering a three-phase system with m harmonics

that are unbalanced, the Fourier series for the phase voltages can be expressed
by Equation (4.4).

m
Va = ∑ Va,i sin( iωs t+ φi ) (4.4)
i=1

Resolving the A phase input voltage into its symmetrical sequence

components, we get Equation (4.5).
 108

m
V pi sin ( iωs t+φ i + ϕ pi ) + V ni sin ( iωs t+φ i +ϕ ni )
Va = ∑
i=1 [ + V 0i sin ( iωs t+ φi + ϕ0i ) ] (4.5)

The current lags the voltage by ρ for all the phases. For the ith
harmonic with positive sequence Vpi ∠ ( φi + ϕpi ) and negative sequence
V ni ∠ ( φi + ϕni ), the space vector of the current for positive sequence of the ith

harmonic is given by Equations (4.6) to (4.8).

f ai+ = Vpi sin ( θ - ρ ) sin ( iω s t + φi + ϕ pi ) (4.6)

f bi+ = Vpi sin ( θ - ρ - 120 0 ) sin ( iωs t + φ i + ϕpi - 1200 ) (4.7)

f ci+ = Vpi sin ( θ - ρ + 1200 ) sin ( iωs t + φ i + ϕ pi + 1200 ) (4.8)

The d-q frame rotates in synchronism with the fundamental supply

frequency, therefore θ=ω s t and Equations (4.6) to (4.8) can be reduced to
Equation (4.9).

3
f i+ = f ai+ + f bi+ + f ci+ = V pi ( cos ( ( i-1) ω s t+ ϕpi +φ i +ρ ) ) (4.9)
2

Similarly, the space vector of the current for the negative sequence
of the ith harmonic is given by Equation (4.10).

3
f -i = f -ai + f -bi + f -ci = - V cos ( ( i+1 ) ωs t+ ϕni + φi -ρ ) ) (4.10)
2 ni (

Under any switching, zero sequence components are not present in

the DC bus voltage. Hence, f i0 =0 and the total space vector current f i is given
in Equation (4.11).

f i = f i+ + f -i (4.11)
 109

Equation (4.12) gives the calculated FDCB voltage.

m
V DC_Calc = ∑ f i (4.12)
i=1

In the unbalanced case, with no harmonic content, Equation (4.12)

reduces to Equation (4.13), as shown in Figure 4.1.

3
V DC_Calc = ( V cos ( ϕ p1 +ρ ) + Vn1 sin ( 2 ωs t + ϕ n1 -ρ- 900 ))
2 p1
(4.13)

Figure 4.1(b) shows that the second harmonic component is

introduced in the FDCB voltage. If the inverter stage switching calculation is
carried out without compensating for the second harmonic oscillations, the
output voltage will be unbalanced and the space vector will trace an elliptical
path.
Magnitude
Magnitude

Time (s)
(a) (b)

Figure 4.1 (a) Phasor representation and (b) time representation

4.5 EFFECT OF OSCILLATIONS IN THE FICTITIOUS DC BUS

ON THE OUTPUT VOLTAGE AND THE INPUT CURRENT

The input unbalance introduces a second harmonic ripple on the

FDCB, as given in Equation (4.13). When this voltage is used to synthesize
 110

the output at a frequency ωo , the fundamental of output current is given by

Equation (4.15) and the harmonic spectrum of the output current is given by
Equation (4.16).

V out = f comp + H comp (4.14)

f comp = V p1 cos ( ϕp1 +ρ ) × sin( ω o t) (4.15)

Hcomp = Vn1 ( sin ( 2 ω s t +ϕ n1 - ρ - 900 ) × sin( ωo t)) (4.16)

On solving Equation (4.16), it is found that the output current

spectrum contains two lower order harmonic components (2 ω s + ω0 ) and
(2 ωs - ω0 ) and a fundamental component, as shown in Figure 4.2.

VO
LT
AG
E
(V)

TIME (s)

Figure 4.2 Output current harmonic spectrum with unbalanced input

 111

Harmonics at the output due to the effect of the ripples on the

FDCB is eliminated by modulating the switching function with the ripples on
the FDCB, as explained in the compensation technique given in Section 4.6.

From Equation (4.13), the current in the FDCB is given by

Equation (4.17). The synthesized fundamental input current and its harmonic
spectrum are given by Equations (4.18) to (4.20).

3
I DC_Calc = ( I p1 cos ( ϕ p1 +ρ ) + In1 sin ( 2 ωs t + ϕn1 - ρ - 900 ) ) (4.17)
2

I in = I f + I h (4.18)

I f = I p1 cos ( ϕ p1 + ρ ) ×sin( ωs t) (4.19)

I h = I n1 ( sin ( 2 ωs t + ϕ n1 - ρ - 900 ) × sin( ω s t) ) (4.20)

On solving Equation (4.20), it is found that the input current

spectrum contains a lower order harmonic component ( 2 ω s + ωs ) = 3 ω s in
addition to the fundamental component.

4.6 THE UNBALANCE COMPENSATION TECHNIQUE

Figure 4.3 shows the input line voltage space vector and the
rectifier current space vector. Equation (4.21) gives the synthesized FDCB
voltage.

VDC = dIα ×|V1| + d Iβ ×|V2| (4.21)

The sector correspondence between the input current space vector

and the input line voltage space vector is given in Table 4.1.
 112

VLM ejπ/2

IM ejπ/2
I3 [01-1]

IM ejπ/6
IM ej5π/6 2 1 I2 [10-1]
I4 [-110]

3 S3 0
S2

IM e-j5π/6 IM e-jπ/6
S1 I1 [1-10]
I5 [-101]
4 5
VLM ej5π/6 VLM ejπ/6

IM e-jπ/2
I6 [0-11]

Figure 4.3 The input voltage space vector and the rectifier current
space vector

Table 4.1 Selection of voltage and current sectors

S. No. Voltage sector Current sectors

1 S1 0, 3
2 S2 1, 4
3 S3 5, 2

where, V1, V2 are the line voltages of the corresponding sector and d Iα, d Iβ are
the duty cycle of the input current space vector with m c =1. The output
modulation index is modified dynamically based on the computed FDCB
voltage. Vdc_min is chosen as the maximum length of output voltage vectors.
For an increase in the FDCB voltage above this limit, the modulation index of
the voltage source converter is reduced correspondingly to keep the output
vector at the constant value as given in Equation (4.22). The output voltage
 113

vector traces a circular path; hence, a balanced output voltage is obtained for
the three-phases. A simple memory technique is used to find the Vdc_min in
every cycle and this value is used in the subsequent cycle. As a result, the
harmonic characteristic of the output current is improved while the input
current harmonics are left uncompensated

m v,comp = m v × Vdc_min / Vdc (4.22)

where, m v,comp is the compensated inverter side modulation index.

4.7 ANALYSIS OF THE PROPOSED UNBALANCE CONTROL

TECHNIQUE

Although the compensation technique can eliminate the effect of

the line side unbalance on the load side, it reduces the output voltage capacity.
The output voltage capacity of the CMC with two-phase unbalance is
analyzed. Let the unbalance in the two phases be defined by
Equation (4.23)

VA = V m sin ( ωs t )

2π
(
V B =(1 - b)× V m sin ωs t-
3 )
2π
(
V C =(1 - a)× V m sin ωs t+
3 ) (4.23)

where, 0< a, b <1 are the unbalance constants in each phase. Then from Kang
and Sul (1997), the positive sequence voltage of each phase can be obtained
as given in Equation (4.24).

1 2T
VpA =
3 (
VA ( t ) + VB t - (
3 ) ( ))=(1- a3 - b3 ) × V
+ VC t -
T
3 A
 114

1 2T
V pB =
3 (
VB ( t ) + V C t -(3 ) ( )) =(1- a3 - 3b ) × V
+ VA t -
T
3 B

1 2T
V pC =
3 (
VC(t )+ VA t -
3 (
+ VB t -
T
3) ( )) =(1- a3 - 3b ) × V C (4.24)

In general, the positive sequence voltage can be defined by

Equation (4.25).

a b ⃗
⃗
(
VP = 1 - -
3 3
× V in ) ( 00 ) (4.25)

Similarly, the negative sequence voltage of each phase is given by

Equation (4.26).

1
VnA =
3 ( T
( ) ( )) = - 13 ( aV + bV )
VA ( t ) + VB t- + VC t-
3
2T
3 B C

1
VnB =
( T
( ) ( )) = - 13 (aV + bV )
V ( t ) + VC t- + V A t-
3 B 3
2T
3 A B

1
VnC =
3 ( T
3( ) ( )) = - 13 (aV + bV )
VC ( t ) + V A t- + V B t-
2T
3 C A (4.26)

In general, the negative sequence voltage can be defined by

Equation (4.27).

1
V in 1200 + b× ⃗
V N = - ( a× ⃗
⃗ V in -1200 )
3

V N| = -
|⃗ √a 2 + b2 -ab
3
(4.27)

Equation (4.28) gives the relation between the positive sequence

and the negative sequence.
 115

V N| √ a 2 + b 2 -ab
|⃗
= (4.28)
V P|
|⃗ ( a+b ) -3

From Wei (2003), the maximum voltage transfer ratio K ub

max under

unbalance condition is given by Equation (4.29). Substituting Equations

(4.25) and (4.27) in Equation (4.29), the maximum voltage transfer ratio with
two unbalanced phases is given by Equation (4.30).

v 2n v 2p
K ub
max
( )|
=0.866× 1-
v 2p
×
v in|
2 (4.29)

2
a 2 + b2 -ab (3-(a+b) )
K ub
max
(
=0.866× 1-
( a+b-3 )2
× 2
3 ) (4.30)

The maximum voltage transfer ratio as a function of the unbalance

constants a and b is shown in Figure 4.4. It is found that the input voltage
transfer ratio decreases as the unbalance ratio increases in one phase and
decreases more quickly when the unbalance ratio increases in both the phases.
The maximum output voltage is 28.9% of the input line voltage when one
phase is switched off with the other phases healthy.

Figure 4.4 Voltage transfer ratio vs unbalance factor across two phases
 116

From Equation (4.3), it can be seen that as the input power factor
decreases, the fictitious DC bus voltage decreases. Hence, for a balanced
input, the output voltage transfer ratio decreases as the power factor
decreases. Using the same idea, it can be written that the maximum voltage
transfer ratio Kp ub
max for an unbalanced system with input power factor control

is given by Equation (4.31).

2
a 2 + b 2 -ab (3-(a+b) )
Kp ub
(
max =0.866× 1-
( a+b-3 )2) ×
32
× cos ( φ i ) ( 4.31 )

Figure 4.5 shows the variations of the Kp ub

max with the variations in

the input power factor and the unbalance ratio a = 0, 0>b >1. It is hence
preferred to operate the CMC at unity power factor at the input during higher
input unbalance to improve the voltage transfer ratio. This avoids the derating
of the load to the largest possible extent.

Figure 4.5 Voltage transfer ratio vs unbalance factor and input power
factor

4.8 SIMULATION
 117

Using the tracking algorithm, an ISVM switching sequence for a

balanced output was synthesized under abnormal input voltage conditions. An
analysis of the uncompensated system and the compensated system has been
carried out and the results are presented in Figure 4.6. When synthesizing a 25
Hz output from a 50 Hz input, with an unbalance ratio of a = 0.7 and b = 0,
without the unbalance compensation, the output current has high third and
fifth order harmonics (4% at 75 Hz and 3% at 125 Hz). The harmonic
spectrum of the input current shows the presence of high third harmonic
component (4%) compared to other harmonics. When the compensation
technique was applied to the switching algorithm, lower order harmonics of
the output current were completely eliminated but the input current spectrum
had higher harmonic content (6%) as compared to the uncompensated case, as
shown in Figure 4.6.

Fundamental (50Hz) = 29.21 , THD= 3.97%

10
Mag (% of Fundamental)

0
0 50 100 150 200 250 300 350 400 450 500 550
Frequency (Hz)

(a)
Fundamental (50Hz) = 22.88 , THD= 6.25%
10
Mag (% of Fundamental)

0
0 50 100 150 200 250 300 350 400 450 500 550
Frequency (Hz)

(b)
 118

Figure 4.6 (Continued)

Fundamental (25Hz) = 36.49 , THD= 4.89%

10
Mag (% of Fundamental)

0
0 100 200 300 400 500 600
Frequency (Hz)

(c)
Fundamental (25Hz) = 32.39 , THD= 0.70%
10
Mag (% of Fundamental)

0
0 100 200 300 400 500 600
Frequency (Hz)

(d)
Figure 4.6 Harmonic spectrum (a) uncompensated input current,
(b) compensated input current, (c) uncompensated output
current and (d) compensated output current

Improved input current spectrum has been reported in Wei (2003)

with corrections on the converter side switching for the indirect matrix
converter (IMC). However, the improved current spectrum cannot be
achieved in the CMC as it does not have independent switchings for the
converter and the inverter.

To evaluate the performance of the proposed techniques for both

the unbalance and the harmonic control, simulation with an R–L load was
carried out. The simulation parameters are shown in Table 4.2.
 119

Table 4.2 Simulation parameters for the unbalance control of the CMC

Quantity Value
R-L Load RL = 2.7Ω , LL = 4.77 mH
Input phase voltage 100 V
Input voltage frequency 50 Hz
Input filter L = 1 mH, C = 35 µF, Rd =15Ω
Output Voltage frequency 40 Hz
Switching frequency 6 kHz
Unbalance & Harmonic V a =100 % V b =90 % V c =100 %
Content V a 2=4 % V b 2=10 % V c 2=10 %
V a 3=3 % V b 3=25 % V c 3=12 %

The input voltages were initially kept balanced. The unbalance and
harmonics, given in Table 4.2, were created at the source at 0.1 ms.
Oscillations in the FDCB, as shown in Figure 4.8(a), reflect harmonics and
unbalance in the input. By modifying the modulation index dynamically, as
shown in the Figure 4.7, it is found that the output current spectrum contains
no harmonic content and is balanced with THD = 0.73%. The input current
spectrum shows harmonic contents with THD =11.19% with a large third
harmonic component of 8.7%, as shown in Figure 4.8.

(a) (b)
Figure 4.7 Polar plot of the modified mv,comp for (a) f=20 Hz, (b) f=40 Hz
 120

Fictitious DC bus Voltage (V)

200

150

100

50

0
0.05 0.1 0.15 0.2
Time(s)

(a)
Source Voltage sV[ABC] (V)

100

50

-50

-100

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
Time(s)

(b)
150
100
Load Voltage (V)

50
0
-50
-100
-150
0.05 0.1 0.15 0.2
Time(s)

(c)

30
t I B C ] (A )

20

10
So u rce C u rreSn [A

-10

-20

-30
0.05 0.1 0.15 0.2

Time
Time(s) (s)
(d)

Figure 4.8 (Continued)

 121

40

Load Current I L[ABC] (A) 20

-20

-40
0.05 0.1 0.15 0.2
Time(s)

(e)

Fundamental (50Hz) = 19.76 , THD= 7.25%

10
Mag (% of Fundamental)

0
0 50 100 150 200 250 300 350 400 450 500 550
Frequency (Hz)

(f)

Fundamental (40Hz) = 29.81 , THD= 0.72%

10
Mag (% of Fundamental)

0
0 40 80 120 160 200 240 280 320 360 400 440 480 520 560
Frequency (Hz)

(g)

Figure 4.8 (a) FDCB voltage, (b) input phase voltage, (c) output phase
voltage, (d) input phase current, (e) output phase current, (f)
harmonic characteristics of the input current and (g)
harmonic characteristics of the output current
 122

4.9 SUMMARY

The proposed method provides a comprehensive scheme for

eliminating the effects of the unbalance and the harmonics. The theoretical
analysis and simulation results are provided to verify the effectiveness of the
proposed scheme. In the proposed method, only the modulation index has
been determined dynamically. The same is solved using the new space vector
technique in Lozano and Ramirez (2008), which makes the system complex
as many memory tables are required for calculating the duty cycles resulting
in the increased memory requirement of the DSP or the FPGA used.

In the proposed technique, the harmonic characteristic of the output

current of the CMC improves with minimum de-rating of the load. However,
the input current harmonics characteristics show no improvement. The
proposed method is a direct feed-forward compensation scheme and does not
require feedback or current sensors. Under the unbalanced conditions, the
highest voltage transfer ratio and the adjustability of the input power factor
are reduced.
 123

CHAPTER 5

A NEW SPACE VECTOR TECHNIQUE FOR THE DIRECT

THREE-LEVEL MATRIX CONVERTER

5.1 INTRODUCTION

The voltage stresses on the power devices can be reduced by using

multi-level inverters (MLIs) (Celanovic and Boroyevich 2000, Lopez et al
2008 and Aneesh et al 2009). MLIs permit the use of lower rating power
supplies and power devices for achieving higher output power rating. Using
the same idea in the matrix converters, a new family of converters called
multilevel matrix converters evolved with different concepts: i) Replacing
each bidirectional switch in the CMC with n cells, each cell consisting of a
capacitor connected to the centre of the H Bridge (Erickson and Al-Naseem
2001 and Erickson et al 2006). This topology generates multi-level output but
at the cost of a more complicated circuit configuration and modulation
strategy. ii) Modifying the topology of the IMC with additional switches,
which makes available two different voltages levels at the output, i.e., the
phase and the line voltages (Meng Yeong Lee et al 2010). This topology is
effective for two-level and three-level voltage conversion with less
complicated circuit configuration and modulation strategy as compared to (i).

Modified IMC based three-level converter uses the diode clamped

multi-level space vector technique (Meng Yeong Lee et al 2010) on the
inverter side and the conventional space vector technique on the rectifier side.
In this chapter, a new class of direct three-level matrix converter (DTMC)
along with its modulation techniques is developed and its performance is
analyzed.
 124

5.2 PROBLEM FORMULATION

The objective of this chapter is to develop a new DTMC topology

namely, the direct three-level matrix converter, which requires three
bidirectional switches of lower ratings (phase voltage rated) and the CMC
topology. The structure is a 4 × 3 matrix converter that facilitates the increase
in the output voltage levels by making the source neutral available to the load
terminals. In addition to the multilevel operation, the converter also has the
ability to control bi-directional power flow. The proposed DTMC is evaluated
by simulation and hardware experimentation. The modulation strategy of the
DTMC uses the multi-level space vector modulation technique along with the
proposed neutral current balancing strategy. The same is implemented using
the Xilinx based system generator facility, which is available as a toolbox in
MATLAB R2010a, along with an FPGA.

5.3 PROPOSED TOPOLOGY

A DTMC in its very generic form, shown in Figure 5.1, consists of

three arms that are connected to the source and one arm connected to the star
point (neutral) of the input filter capacitances. Figure 5.1 depicts the general
configuration of the proposed DTMC structure which consists of a CMC and
a neutral point connecter.

5.3.1 Indirect Matrix Converter Representation for the DTMC

The proposed DTMC topology consists of an array of 4 × 3 bi-

directional switches, which includes the 3 × 3 switches of the CMC and three
additional switches for making the neutral point of the input filter capacitance
to be available at the load terminals. Equations (5.1) and (5.2) give the output
voltages and the input currents of the DTMC.
 125

IA
VA

SAa SAb SAc

IB
VB

SBa SBb SBc

IC
VC
SCa SCb SCc
IN

SNa SNb SNc

Ia Ib Ic
Va Vb Vc

Figure 5.1 Topology of the direct three-level matrix converter

VA

][ ]
V a S Aa SBa SCa SNa

[ ][
V b = S Ab SBb SCb
Vc S Ac SBc SCc SNc
V
SNb × B
VC
0
(5.1)

IA SAa SAb S Ac

[][
IB
IC
IN
S
= Ba
SCa
SNa
SBb
SCb
SNb
SBc
SCc
SNc
][]
Ia
× Ib
Ic
(5.2)

Since the DTMC is supplied by a voltage source, the input phases

must never be shorted, and due to the inductive nature of the load, the output
phases must never be left open. These constraints are realized by
Equation (5.3).

S Aj +SBj + SCj + SNj =1 j∈ {a,b,c } (5.3)

 126

The DTMC can be decoupled into an indirect three-level matrix

converter (ITMC) consisting of a fictitious two-level converter (FTC – input
converter) and a fictitious inverter (FI - output converter), as shown in
Figure 5.2.

VDC+
IDC+

SCA SCB SCC SCN SIA SIB SIC

VA IA Ic
Vc
VB IB Ib
IC VDC Vb
VC Ia
IN Va
VN

SCa SCb SCc SCn SIa SIb SIc

Rectifier part IDC- VDC- Inverter part

(FTC) (FI)

Figure 5.2 Topology of the indirect three-level matrix converter

The FTC consists of three phase arms and one neutral arm.
Switching ON any of the two phase arms leads to the line voltage being
available at the FDCB and switching ON any one phase arm with the neutral
arm leads to the phase voltage being available at the FDCB. This results in
twelve active voltage vectors on the rectifier side. This decoupled
representation simplifies the control of the input current and the output
voltage in DTMC, as described in the next section.
 127

5.4 SPACE VECTOR MODULATION TECHNIQUE FOR THE

DTMC

The switching function for the DTMC is represented as the product

of the rectifier switching function and the inverter switching function and is
given by Equation (5.4).

SAa SBa SCa SNa SIA SIa

[ ][ ][S S S S
SAb SBb SCb SNb = SIB SIb × CA CB CC CN (5.4)
SAc SBc SCc SNc SIC SIc
SCa SCb SCc SCn ]
The switching states for synthesizing the required currents and
voltages are described in the following subsections.

5.4.1 The Fictitious Two-Level Converter Stage

Assuming that the output of the FTC is a constant current source

IDC, the space vector for all valid switching states are determined by Equations
(5.5) to (5.7).

2π 4π
I α = I A + I B cos + I C cos (5.5)
3 3

2π 4π
I β = IB sin + I C sin
3 3
(5.6)

I0 = IA + IB + IC (5.7)

As described in Section 5.3.1, switching ON the neutral arm causes

the current to flow in the source neutral resulting in the space vector having a
component along the I0 axis. Table 5.1 gives the space vector components for
different valid switching states and Figure 5.3(a) shows the space vectors
distribution
 128

Table 5.1 Space vectors for the fictitious two-level converter

SCA SCB SCC SCN

[ ]
Type

Vector IA IB IC I N = I0 I in ∠ I¿ V DC
SCa SCb SCc SCn

I L1 [AB] [ 10 01 00 00] + I DC - IDC 0 0 √3 I DC 3300 VAB

I L2 [AC] [ 10 00 01 00] + I DC 0 - IDC 0 √3 I DC 300 V AC

Active long vectors

I L3 [BC] [ 00 00 10 01] 0 + I DC - IDC 0 √3 I DC 90 0 VBC

I L4 [BA] [ 01 10 00 00] - IDC + I DC 0 0 √3 I DC 1500 V BA

I L5 [CA] [ 01 00 10 00] - IDC 0 + I DC 0 √3 I DC 2100 VCA

I L6 [CB] [ 00 01 10 00] 0 - IDC + I DC 0 √3 I DC 2700 V CB

I P1 [AN] [ 10 00 00 01] + I DC 0 0 - IDC I DC 00 VAN

I P2 [NC] [ 00 00 01 10] 0 0 - IDC + I DC I DC 600 VNC

Active short vectors

I P3 [ BN ] [ 00 10 00 01] 0 + I DC 0 - IDC I DC 1200 VBN

I P4 [ NA ] [ 01 00 00 10] - IDC 0 0 + I DC I DC 1800 V NA

I P5 [CN] [ 00 00 10 01] 0 0 + I DC - IDC I DC 2400 VCN

I P6 [NB] [ 00 01 00 10] 0 - IDC 0 + I DC I DC 3000 VNB

vectors Zero

IZ
[ 11 00 0
0
0 0 1 0
][
0 0 1 0
0
0 ] 0 0
[ 00 00 1
1
0 0
0 ][ 0
0 0
0 0
1
1]

-1 Iβ
where, I in = √ I α2 + I β2 and Iin = tan .
Iα

Vectors represented by ILi (active long vectors) are conventional

rectifier space vectors, which do not contribute to the neutral current. Vectors
represented by IPi (active short vectors) contribute to the neutral current. To
 129

ensure that the input current is sinusoidal, the reference space vector must lie
on the αβ plane requiring the neutral current to be zero on application of the
vector IPi. This is carried out by applying equally the adjacent I Pi vectors,
which lie on the upper and the lower halves of the αβ plane. This ensures that
the average neutral current is zero over a switching period. The example in
Table 5.2 explains the same.

Table 5.2 Neutral current balancing and virtual vector synthesis

Switching IA IB IC IN VDC
Applied vectors
time
Ts
I P6 0 - IDC 0 + I DC VNB
2
Ts
I P1 + I DC 0 0 - IDC VAN
2
1 1 1 1 1
Ts I VP1 = I P6 + I P1 + IDC - I DC 0 0 V
2 2 2 2 2 AB

This solution to the neutral current balancing problem (Celanovic

and Boroyevich 2000) introduces virtual vectors IVPi, which lie completely on
the αβ plane, as given in Table 5.3 and shown in Figure 5.3(b).
 130

IP4 IP2
IP6

IL3
IL4

IL2
IZ1, IZ2, IZ3, IZ4
IL1
IL5 IL6

IP3 IP1
IP5

Figure 5.3(a) Space vectors of the FTC

IL3

2 1
IL4 IL2
IP3 IVP3 IP2

IVP4 IVP2
IP4
IP10
3
IVP5 IVP1

IP5 IP6
IVP6
IL5 IL1
4 5

IL6

Figure 5.3(b) Space vectors and virtual vectors of the FTC

 131

Table 5.3 Virtual current space vectors

Virtual Sharing
IA IB IC IN = I0 Iin Iin VDC
vectors vectors
1 1 √3 1
I VP1 [AN] I P6 , I P1 + IDC - I DC 0 0 I DC 3300 V
2 2 2 2 AB
1 1 √3 1
I VP2 [NC] I P1 , I P2 + IDC 0 - I DC 0 I DC 300 V
2 2 2 2 AC
1 1 √3 1
I VP3 [BN] I P2 , I P3 0 + IDC - I DC 0 I DC 90 0 V
2 2 2 2 BC
1 1 √3 1
I VP4 [NA] I P3 , I P4 - I DC + IDC 0 0 I DC 1500 V
2 2 2 2 BA
1 1 √3 1
I VP5 [CN] I P4 , I P5 - I DC 0 + IDC 0 I DC 2100 V
2 2 2 2 CA
1 1 √3 1
I VP6 [NB] I P5 , I P6 0 - I DC + IDC 0 I DC 2700 V
2 2 2 2 CB

Figure 5.4(a) shows the sector zero of the space vector diagram of
the FTC. Each sector consists of two active long vectors, two active virtual
short vectors and four zero vectors. To synthesize the required reference input
current and the FDCB voltage, the three nearest current vectors (Busquets-
Monge et al 2004) are selected, as shown in Figure 5.4(b), depending on the
modulation index mc of the FTC.

IL2 E
F
IVP2 IREF
R2
IZ R4
R5 G D
θC R3 H
A
R1

IVP1
B
IL1 C

Figure 5.4(a) Sector region identification of the FTC

 132

E E
E
I1 I1
F F F I1
I3 R2 I3
F
I3 R4
I3
H D G H D
A I1 R5 H
G H
R3
I2
I2 R1
I2 I3
B B I2 B
B
I1 I2
C
C C

Figure 5.4(b) Region vector identification of the FTC

In order to identify the region in which the reference vector lies,

equations of the three lines are derived and shown in Figure 5.5. Table 5.4
gives the rules for identifying the region in which the reference vector lies in
the FTC for different values of modulation indices mc.

IL2 1 √3
cosec ( 600 + θc ) ; 00 <θc < 600
1/2 4
IVP2
IREF

1
IZ
√3/4 1/√3 √3/2 sec ( 600 - θc ) ; 300 <θc < 600
θC 2

IVP1 1
1/2 sec ( θc ) ; 0 0 < θc <30 0
IL1 1 2

Figure 5.5 Equations of lines used for identifying regions in the FTC

Table 5.4 Region identification for a given IREF

Region
Sl. No.

Conditions

1
1 R1 m c > sec ( θc ) ; 00 <θc < 300
2
 133

1
2 R2 m c > sec ( 600 - θc ) ; 300 < θc <600
2
√3 1
3 R3 cosec ( 600 + θc ) < m c ≤ sec ( θc ) ; 00 <θc < 300
4 2
√3 1
4 R4 cosec (600 + θc ) < m c ≤ sec ( 600 - θc ) ; 30 0 < θc <60 0
4 2
√3
5 R5 mc≤ cosec ( 600 + θc ) ; 00 <θc < 600
4

Duty cycles of the selected vectors for different regions are

computed using Equation (5.8), where (xi, yi) are the coordinates of the
selected vector Ii and di is its duty cycle. X and Y are the coordinates of the
reference vector IREF and are given by Equation (5.9).

x 1 x2 x 3 d 1 X

[ ][ ] [ ]
y1 y2 y3 d2 = Y
1 1 1 d3 1
(5.8)

X = m c × cos θc & Y = m c ×sin θc (5.9)

While computing the duty cycle, the sector in Figure 5.6(a) is

rotated as shown in Figure 5.6 (b). The coordinates are chosen according to
the region in which the reference vector lies, as shown in Figure 5.6 (b).
Table 5.5 gives the duty cycles derived for different regions

IL2
Y IL2( cos600, sin600)
Y
IVP2
IREF
IVP2 (0.5 cos600, 0.5 sin600)

IZ IREF(mccosθc, mcsinθc)
θC X
θC
IVP1
X
IZ(0, 0) IVP1(0.5, 0) IL1(1, 0)
IL1
 134

Figure 5.6 (a) Sector 1 and (b) sector 1 rotated

Table 5.5 Duty cycles for different regions in a given sector

Region

Duty Cycle
d1- I1 d2- I2 d3 - I3
2 4
R1 m sin ( θc ) 2 m c cos ( θc ) -1 2- m c sin ( 600 +θ c )
√3 c √3
2 4
R2 2 m c sin ( 300 + θc ) -1 m sin ( 600 - θc ) 2- m sin ( 600 +θ c )
√3 c √3 c
4 4
R3 m c sin ( 600 + θc ) -1 m c sin ( 600 - θc ) 2 - 4 m c cos ( θc )
√3 √3
4 4
R4 m c sin ( 600 + θc ) -1 2 - 4 m c sin ( 300 +θc ) m sin θc
√3 √3 c
4 4 4
R5 1- m sin ( 600 +θc ) m sin ( 600 - θc ) m sin θc
√3 c √3 c √3 c
where, θc is the angle of IREF within the sector and mc is the inverter zero
compensated converter modulation index discussed later and is given in
Equation (5.14).

5.4.2 The Fictitious Inverter Stage

The conventional SVPWM is implemented in the inverter stage.

This consists of six active voltage vectors and two zero voltage vectors, as
shown in Figure 5.7. To generate the required reference vector V OUT, adjacent
active vectors Vγ, Vδ and a zero vector V0 are selected whose duty cycles dγ, dδ
and d0 are given by Equation (5.10)

d γ = sin ( 600 - θ v ) , d δ = sin ( θ v ) and d 0 = 1- (d γ +d δ ¿ (5.10)

where, θv is the angle of VOUT within a sector. The output voltage of the
inverter can be adjusted by any one of the two schemes: (i) changing the
FDCB voltage to the inverter, (ii) changing the modulation index m v of the
inverter. The second scheme is not used for reasons explained in the next
paragraph and hence mv=1. The FDCB voltage can be varied by changing the
modulation index m 'c of FTC as given in Equation (5.11)
 135

Vb
V2 [110]
V3 [010] VMejπ/3Zero Vectors
VMej2π/3
2 V0 [000]
V7 [111] Vγ
3 1
V4 [011]
VMejπ Vγdγ Va Vγdγ
4 V1 [100] VREF
Vδdδ θv VOUT VMe-j0
0
θv Vδ
5 V0 d0
V5 [001] Vδdδ
VMe-j2π/3 V6 [101]
Vc VMe-jπ/3

Figure 5.7 (a) Space vectors of the FI and (b) sector and duty cycle
allocation

√3
m 'c = m DTMC (5.11)
2

where, mDTMC is the required modulation index of the DTMC. At higher

modulation indices, the FTC reference vector, Iin, lies in any one of the
regions R1, R2, R3 or R4. These regions do not use any zero vectors for the
modulation, as described in section 5.4.1. Simultaneous use of the zero
vectors at the inverter stage would cause the output voltage to become zero.
This is not consistent with the idea of multilevel switching techniques as it
increases the THD at the output. To decrease the THD of the DTMC, zero
vectors are not used at the inverter stage, which does not allow for the change
in modulation index mv. With the elimination of the zero vectors, the duty
cycles for active vectors are recomputed as given in Equation (5.12). This
increases the output voltage vector as given by Equation (5.13).Thus the
reference vector is brought outside the inscribed circle of the space vector
hexagon leading to an over modulation condition.

dγ dδ
d 'γ = & d'δ =
d γ + dδ dγ + dδ
(5.12)
 136

' ' ' V OUT

V OUT = d γ V γ + d δ V δ =
dγ + dδ
(5.13)

The increase in the output voltage vector is compensated by

adjusting the FDCB voltage by modifying the modulation index of the FTC
dynamically, as given by Equation (5.14).

√3
mc= m DTMC ( d γ + dδ ) (5.14)
2

Figure 5.8 shows the allocation of the switching vectors in a

sampling period for a particular inverter sector and for different regions of the
converter sector. The period of the virtual vector is divided into two, during
which the adjacent upper and lower active short vectors of the corresponding
virtual vector is applied. The real-time switching pattern for the DTMC is
computed for each vector combination of the FTC and the FI using
Equation (5.4). Figure 5.8(a) shows the switching pattern for the DTMC for
regions R1 and R2 when only one active virtual vector is used. Figure 5.8(b)
shows the switching pattern for the DTMC for regions R 3, R4 and R5 when two
active virtual vectors are used.

dγ dδ

Vγ Vδ

I3 I1 I2 I3 I3 I1 I2 I3
dδdV1

dδdV3 /2
dδdV2
dγdV3/2

dγdV3/2

dδdV3/2
dγdV1

dγdV2

Figure 5.8 (a) Switching pattern of the DTMC for the regions R1 and R2
 137

dγ dδ

Vγ Vδ

I3 I2 I1 I2 I3 I3 I2 I1 I2 I3

dδdV3 /2
dγdV3 /2

dδdV2 /2
dδdV1
dγdV1
dγdV2 /2

dγdV2 /2

dδdV2 /2

dδdV3 /2
dγdV3 /2
Figure 5.8(b) Switching pattern of the DTMC for the regions R3, R4 and R5

5.5 DTMC OPERATION UNDER ABNORMAL INPUT

CONDITIONS

From Equation (5.14) it can be shown that within a sector, m c

reaches the peak once when (d γ + dδ) =1 and reaches the minimum value twice
when (dγ =0) or (dδ =0), and this repeats for all the six sectors. Hence the
dynamic variation of the m c introduces a sixth harmonic component 6fi at the
FDCB, as shown in Figure 5.9 (a), where f i is the fundamental frequency of
the input voltage.

400
C a lc u la te d F D C V

300

200

100

0
0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Time(s)

Figure 5.9 (a) Calculated FDCV with a balanced input voltage

It was shown in chapter 4 that an input unbalance introduces a

second harmonic component 2fi at the FDCB of the CMC. Hence, the FDCB
voltage of DTMC, as shown in Figure 5.9(b), contains two components 6fi &
2fi during the input unbalance.
 138

400
Calculated FDCV (V)
300

200

100

0
0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095
Time(s)

Figure 5.9 (b) Calculated FDCB voltage with an unbalanced input voltage

The instantaneous variation can be determined by Equation (5.15),

where VR, VS and VT are the FDCB voltage on applying the switching vectors
I1, I2 and I3 respectively.

VDC = d1 ×|V R| + d2 ×|VS|+ d 3 ×|VT| (5.15)

To mitigate the effects of the unbalance at the output, as explained

in chapter 4, the input voltage of the FI must be limited to the minimum of the
FDCB voltage VDC over an input cycle expressed as V DC_Min. This is achieved
by dynamically modifying mc, as given in Equation (5.16). This mitigates the
effect of unbalance and harmonics in the output currents while the input
current harmonics are left uncompensated.

√3
mc= m DTMC ( d γ + dδ ) × VDC_Min / V DCF (5.16)
2

5.6 MODELING OF LOSSES IN THE CMC AND THE DTMC

There are three types of losses in power semiconductor devices

namely the ON, the OFF and the switching losses. The power loss in the
device when it is “OFF” is negligible compared to its power loss when it is
either “ON” or when it is undergoing transition. The power loss in the device
during its ‘ON’ state is called the conduction loss while the power losses in
 139

the device during its transition (‘ON’ to ‘OFF’ or vice-versa) states is called
the switching loss. Conduction loss is the product of the voltage drop across
the device and the current through the device, when it is in the ‘ON’ state.
Switching loss is proportional to the product of blocking voltage and
conduction current at the instant of switching; and if this is significant, it is
termed as hard switching loss (Bierhoff and Fuchs 2004). If the switching
occurs when either the current through the device or the voltage across the
device is nearly zero, the commutation is referred to as ‘soft switching’ and
the switching loss in the device is negligible. For an IGBT, there are two
types of losses during hard switching: Ton_losses and Toff_losses, associated with the
device turn-ON and turn-OFF process respectively. For a diode, the switching
loss is caused by reverse recovery mechanism that occurs only during the
diode turn-OFF. Hence, the turn-ON loss for a diode is not considered.

5.6.1 Conduction Loss Modeling for the CMC and the DTMC

From Equation (5.3), it can be seen that in each phase only one
switch conducts at any given time. Hence, there is always only one IGBT that
conducts and only one diode that conducts at an output phase of the CMC and
the DTMC. Equations (5.17) and (5.18) give the conduction loss and the
conduction energy of one output phase in each switching cycle

CLosses ( v d , i L ) = v d ( i L ) × i L + vd
IGBT DIODE
( iL ) × i L (5.17)
Ts
Ec ( v d , i L )=∫ CLosses ( v d , i L ) dt (5.18)
0

where, v d ( iL ) is the ON state voltage drop in the IGBT and v d

IGBT DIODE
( iL ) is the
ON state voltage drop in the diode and given by Equations (5.19) and (5.20)

v d ( i L ) =x + y × i Lz
IGBT
(5.19)
 140

vd DIODE
( iL ) =m + n × i Lk (5.20)

where, x, y, z, m, n and k are constants that are obtained from the curve fitting
equation of Vce-Ic characteristics given in the datasheet of the device used.
Then the average conduction loss over an interval T, for the CMC and the
DTMC, is give by Equation (5.21).

T
1
CL_Avg = ∫ CLosses ( t ) dt (5.21)
T 0

5.6.2 Switching Loss Modeling for the CMC and the DTMC

During switching transients, the switching energy is described by

Equation (5.22) (Wang and Venkataramanan 2006, Apap et al 2003)

Esw ( v Block , i L ) = EswR × ( v Block × i L ) / ( V R × i R ¿ (5.22)

where, VR, iR and EswR are respectively the voltage, current and switching
energy of the device at the rated VR and iR. From Figure 1.4, and the four step
commutation procedure, discussed in chapter 1, it can be seen that when
commutation happens between the bidirectional switch S1 to switch S2 under
the condition of Vin >0 and Iout >0, commutation losses do not occur for
switches S1-, S2+ and S2-. This is because the switches S1- and S2- do not block
any voltage and the switch S 2+ does not conduct current. This creates only a
turn OFF loss for the switch S1+. Similarly, S2 to S1 transition creates a turn
ON loss for the switch S1+ and a turn OFF loss for the diode D2-. Table 5.6
summarizes the switching energy losses for commutation between S 1 and S2
evaluated for all conditions of input voltages and output currents.

Table 5.6 Switching energy losses for switch S1 to switch S2 transition

Switch S1  S2 S2  S1 S1  S2 S2  S1
 141

transition
Iout + Iout -
Vin + Eoff Eon + E rr_D Eon + E rr_D Eoff
Vin - Eon + E rr_D Eoff Eoff Eon + E rr_D

From Table 5.6, it can be generalized that two commutation events,

i.e., (i) first phase to second phase transition and (ii) second phase to first
phase transition within a switching cycle produces three switching losses
namely (i) an IGBT ON loss, (ii) an IGBT OFF loss and (iii) a Diode OFF
loss. Hence EswR = Eon + Eoff + Err_D where, Eon and Eoff are the switching energy
for the IGBT ON and IGBT OFF switchings at the rated V R and iR. Err_D is the
DIODE OFF switching energy at the rated V R and iR. In general, for a
particular transition from the input phase x to the input phase y, and vice-
versa the switching loss is given by Equation (5.23).

Esw ( v xy , i L ) = (Eon +Eiff + Err ¿∗(¿ v xy∨¿ i L) /(V R∗i R ¿

D

(5.23)

From the Tdelay-Ic characteristics of the datasheet, Ton, Toff and Tr are
identified. Equation (5.24) gives the switching power loss.

Eon Eoff Err

SLosses ( v xy , i L ) = ( + + ¿∗(¿ v xy∨¿ i L )/(V R∗i R ¿
D

Ton T off T r

(5.24)

5.6.2.1 Switching energy calculation for the CMC

Switching losses depend on the modulation technique. In this work,

a double-sided space vector switching technique is selected for the CMC as
well as the DTMC. It can be seen that the optimized switching technique
(Nielsen et al 1996) leads to eight commutation events over all the three
 142

output phases in a switching cycle Ts. Four of these commutation events occur
in an output phase and two commutation events each occur in the other two
output phases.

VAC VAC VBC VAB VAC VAC VAB

VBC
SAa SAb SAc

SBa SBb SBc

SCa SCb SCc

Ts Ts Ts
Switching Period Switching Period Switching Period

Figure 5.10 Commutation events of the CMC in a switching period for

voltage sector 1 and current sector 1

From Figure 5.10, it can be seen that the total switching energy of
the CMC over a sampling time Ts is given by Equation (5.25)

Esw = K . (|v AC|. i a +|v BC|. i b + (|v AB|+|v AC|) . i c ) (5.25)

where, K= (Eon+ Eoff + Err_D) / (VR × iR). For other voltage and current sectors,
Equation (5.25) can be generalized as Equation (5.26)

Esw = K ( x i a + y i b + z i c ) (5.26)

where, x, y and z take any of the values |v AB|,| vBC |,| vAC |, (|vAB|+| vBC|) or (|vAB|
+| vAC|) depending on the sectors of the current and the voltage.

5.6.2.2 Switching energy calculation for the DTMC

In the DTMC, two types of commutation events occur namely: i)

the line commutation where the blocking voltage is the line voltage and ii) the
phase commutation where the blocking voltage is the phase voltage.
Extending the optimized indirect space vector switchings for the DTMC, as
 143

explained in Appendix II, the number of commutation events for a particular

voltage sector X and different regions of current sector Y is calculated and
given in Table 5.7. Equations (5.27) to (5.31) give the total switching energy
of the DTMC over a sampling time T for the voltage sector 1 and different
regions of the current sector 1.

Table 5.7 Commutation events in a switching cycle Ts

Converter sector - Y & Inverter sector -X

Commutation
events Regions of converter sector
R1 R2 R3 R4 R5
Line voltage
6 6 4/2 2/4 0
commutation
Phase voltage
14 14 22 22 20
commutation
Region 1

Esw 1 = K . (|v AN|. i a +(|v BC|+|v CN|+|v BN|). i b + (|v AB|+|v AC|+2|v AN|+|v BN|+|v CN|) . i c )
R

(5.27)

Region 2

Esw = K . (|v AN| . i a +(|v BC|+ 2|v CN|). i b+ (|v AB|+|v AC|+ 2|v AN|+2|v CN|) . i c )
R2

(5.28)

Region 3

Esw = K . (3|v AN|. i a +(|v BC|+|vCN|+|v BN|). i b+ (|v AB|+ 3|v AN|+|v BN|+ 2|v CN|) . i c )
R3

(5.29)

Region 4
 144

Esw 4 = K . (3|v AN|. i a +(|v CN|+|v BN|). i b+ (|v AC|+ 3|v AN|+|v BN|+ 2|v CN|) . i c )
R

(5.30)

Region 5

Esw = K . (2|v AN|. i a +(|v BN|+2|v CN|). i b + (|v BN|+2|v AN|+2|v CN|) . i c )
R5

(5.31)

The switching and conduction losses for the DTMC were derived
and compared with those for the CMC. A complete loss model was developed
using the Simulink blockset in MATLAB. Through simulations, switching
energy losses for different regions for different sectors of the current and the
voltage are calculated using the above procedure and results obtained are
discussed and presented in the next section.

5.7 SIMULATION

To evaluate the performance of the proposed topology with the

modified space vector technique, simulation with R–L load was performed.
Table 5.8 gives the simulation parameters.

Table 5.8 Simulation parameters for the DTMC topology

Quantity Value
R-L Load R = 20Ω , L = 21mH
Input phase voltage 100 V
Input voltage frequency 50 Hz
Input filter L = 2 mH, C = 35 µF, Rd = 15 Ω
Output Voltage frequency 25 Hz
Switching frequency 6 kHz
Modulation Index 0.72, 0.5, 0.25
 145

√3 √3
For modulation indices between and , the output voltage
4 2
switches between the active long vectors and the active short vectors but for
lower modulation indices, the output voltage switches between the active
short vectors and the zero vectors. Figure 5.11 shows the output phase
voltages, output line voltages, input currents and output currents for the
voltage transfer ratio that is changed from 0.72 to 0.5 at 0.4 s and 0.5 to 0.25
at 0.5 s. The harmonic content of the input and the output currents increase
with decrease in the voltage transfer ratio. In the CMC, the peak of the output
voltage is √ 3 times the input voltage for all values of modulation indices.
However, in the DTMC, the peak of the output voltage is √ 3 times the input

√3
voltage for the modulation indices greater than while the peak of the
4

√3
output voltage is times the input voltage for modulation indices lesser
2

√3
than . This leads to lower switching stress on the power devices in the case
4
of the DTMC.

200

100
Van (V)

-100

-200
0.3 0.35 0.4 0.45 0.5 0.55 0.6
Time(s)

(a)
 146

200

100
Vab (V)

-100

-200
0.3 0.35 0.4 0.45 0.5 0.55 0.6
Time (s)

(b)

2
IABC (A)

-2

-4
0.3 0.35 0.4 0.45 0.5 0.55 0.6
Time (s)

(c)

Figure 5.11 (Continued)

2
Iabc (A)

-2

-4
0.3 0.35 0.4 0.45 0.5 0.55 0.6
Time (s)

(d)

Figure 5.11 Performance of the DTMC with a balanced supply for

different modulation indices (0.72, 0.5, 0.25) (a) output
phase voltage, (b) output line voltage, (c) input phase
current and (d) output phase current
 147

A 20% unbalance in the phase B was introduced. In addition,

second and third harmonics with magnitudes of 4% and 7% of the
fundamental respectively were added to all the three phases as shown in
Figure 5.12(a). By dynamically modifying the modulation index, as explained
in the previous section, the effect of the unbalance and harmonics has been
mitigated in the output voltages and currents, as shown in Figures. 5.12(b)
and 5.12(d). The unbalanced input currents are shown in Figure 5.12(c).

100

50
VABC ( V )

-50

-100
0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time (s)

(a)

Figure 5.12 (Continued)

150
100
50
Van(V)

0
-50
-100
-150
0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time (s)
(b)
 148

IABC (A) 2

-2

-4
0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time (s)
(c)
4

2
Iabc ( A)

-2

-4
0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time (S)
(d)
0.9
Modulation Index (c)M

0.7

0.5

0.3

0
0.06 0.08 0.1 0.12 0.14 0.16 0.18
Time(s)
(e)
Figure 5.12 Performance of the DTMC with an unbalanced supply
(a) output phase voltage, (b) output line voltage, (c) input
phase current and (d) output phase current and
(e) modulation index
Figures 5.13 to 5.15 present a quantitative comparison between the
CMC and the DTMC. Simulation was carried out for the CMC and the
DTMC for a Modulation Index (MI) of 0.866 and the THD of the output
voltage are shown in Figures 5.13(a) and 5.13(b). At the maximum
modulation index of 0.866, the THD for the DTMC reduces by 10% when
compared to the CMC. The THD content of the output voltage for the CMC
and the DTMC, for all modulation indices, is presented in Figure 5.13(c). It
 149

can be seen that the DTMC has a better (lower) THD than the CMC for all
modulation indices. In the DTMC, for modulation indices varying from 0.866
to 0.45, the current vector lies in any of the regions of R 1, R2, R3, or R4 and the
THD is almost constant as zero vectors are not selected. When the current
vector is in the region R5 (MI < 0.4), the THD of the DTMC rises linearly
with modulation index, as in the case of the CMC, because of the use of the
zero vectors.

Fundamental (25Hz) = 345.2 , THD= 59.15%

Mag (% of Fundamental)

25

20

15

10

0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (Hz)

(a)
Fundamental (25Hz) = 345.1 , THD= 53.20%
Mag (% of Fundamental)

20

15

10

0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (Hz)

(b)
Figure 5.13 (Continued)
 150

(c)
Figure 5.13 Output voltage THD for MI of 0.866 (a) CMC, (b) DTMC,
(c) output voltage THD for the CMC and the DTMC with 6
kHz switching frequency for different MI

At very low modulation index, the THD for the DTMC reduces by
approximately 58% as compared to the CMC due to the use of phase vectors.
From Figure 5.14(a), it can be observed that the conduction losses are always
greater than the switching losses in the CMC, for different values of MIs.
Figure 5.14(b) shows that as the input power factor decreases, the output
power of the converter also decreases.

(a)
Figure 5.14 (Continued)
 151

(b)

Figure 5.14 (a) Losses vs. MI and (b) output vs. MI (different IPF)

The conduction losses for the DTMC and the CMC are the same
under all operating conditions. However, the switching losses for the DTMC
are higher than the switching losses of the CMC for all MIs, since the
switching events are more in the DTMC than in the CMC. With a double side
banded SVM, the DTMC exhibits higher switching losses for all values of
MIs. Nevertheless, for the single sided SWM, the DTMC exhibits higher
switching losses for lower values of MIs and lower switching losses for
higher values of MIs. This is because the switching events of the regions R 3,
R4 and R5 are very high compared to the switching events of the regions R 1
and R2, as shown in Figure 5.15.
 152

Figure 5.15 Conduction and switching losses for the DTMC and the
CMC for different values of MI

5.6 HARDWARE IMPLEMENTATION

To validate the proposed switching algorithm, a 3 kVA direct

multilevel matrix converter prototype was developed. The setup consists of a
control circuit, CONCEPT gate driver module (6SD106EI), multilevel matrix
converter module with bidirectional switches (SEMIKRON - SK60GM123).
The control circuit consists of an FPGA (SPARTEN 3A DSP-XC3S1800A) for
generating switching pulses for the DTMC.

The switching information and the current direction information

were processed using the FPGA for generating the DTMC switching pulses
along with the implementation of the four-step commutation. The system
generator toolbox in the MATLAB was used to generate the FPGA code in
VHDL for generating the firing pulses. The experiment was conducted with a
balanced input phase voltage of 100V, switching frequency of 6 kHz, RL=20Ω,
LL=21mH and MI =0.72. The DTMC was used for converting the 50 Hz input
voltage to 25 Hz output voltage. Figure 5.16 shows the laboratory prototype of
 153

the DTMC. Selected waveforms from experimental results shown in Figure

5.17 verify the implementation and the effectiveness of the proposed DTMC
ISVM method. Individual units of the hardware are shown in detail in
Appendix I. Figures 5.17 (a) and 5.17 (b) show the output line voltage and the
output phase voltage of the DTMC respectively. Figure 5.17 (c) shows the
25Hz output current of the DTMC and Figure 5.17 (d) shows the 50Hz filtered
input current of the DTMC.

Figure 5.16 DTMC hardware prototype

(a)

Figure 5.17 (Continued)

 154

(b)

(c)

(d)

Figure 5.17 Hardware output for balanced input condition (a) output
phase voltage, (b) output line voltage, (c) output phase
current and (d) input phase current
 155

5.7 SUMMARY

In this chapter, the space vector PWM technique for the direct
three-level matrix converter has been proposed for synthesizing balanced
sinusoidal three-level output voltages from balanced and unbalanced
non-sinusoidal input voltages. In addition, conduction losses and switching
losses were modelled for the DTMC and a comparative study of the same for
the CMC and the DTMC has been carried out.

MATLAB simulation and hardware results verify the effectiveness

of the proposed technique. The THD of the output voltage is lower for the
DTMC as compared to the CMC. However, the switching losses for the
DTMC are higher than those of the CMC.
 156

CHAPTER 6

DIRECT TORQUE CONTROL OF THE DIRECT THREE

LEVEL MATRIX CONVERTER BASED
INDUCTION MOTOR DRIVE

6.1 INTRODUCTION

The state of the motor shaft of a variable speed drive (VSD)

controls the flow of energy from the mains to the load. The state of the shaft
is described by two physical quantities namely torque and speed, which must
be controlled to control the flow of energy. In practice, either the torque or the
speed is controlled and the control is termed as “torque control” or “speed
control” respectively. Initially, DC motors were used as VSDs for their ease
in achieving the required speed and torque. The evolution of the AC variable
speed drive technology was driven by the desire to have the excellent
performance of the DC motor, such as fast torque response and accuracy in
speed, while using inexpensive and maintenance free AC motors.

The Direct Torque Control (DTC) is a high-dynamic performance

VSD control technique for induction motors (IM) developed in the last two
decades (Takahashi and Noguchi 1986 and Casadei et al 1994). In the DTC
technique, the power converter switches according to the load needs. The
difference between the traditional vector control and the DTC is that the DTC
has no fixed switching pattern, Hence the DTC response is extremely fast for
load changes. In the DTC, the motor torque and flux are the variables that are
directly controlled and hence, the name Direct Torque Control. In spite of its
 157

high dynamic response, sensorless operation, non-requirement of coordinate

transformation, and robustness, the DTC has some disadvantages. These are:
(i) the difficulty in controlling the torque and the flux at low speeds, (ii)
higher current and torque ripples, which result in higher machine losses and
noise. To retain the advantages and eliminate the problems of the DTC, a
hybrid method SVM-DTC was proposed in Casadei et al (2000).

DTC methods were also proposed for the MLI (Escalante et al

2002). Later, the problem of neutral current balancing in the MLI was
addressed with an additional voltage hysteresis comparator (Larijani et al
2010). The DTC procedure for the CMC drive along with the input current
control was developed by Matteini (2001). Later, the MIN-MID-MAX
technique to divide the input voltage path into 12 sectors for reducing the
torque ripple was proposed in (Venkatesh and Reddy 2012). However, the
DTC technique for the multi-level matrix converters has not yet been
reported. This chapter begins with an introduction of the DTC scheme for the
CMC of an IM. Next, the DTC method for a multilevel matrix converter with
unity input power factor is proposed. The performance of the proposed
control method is analyzed based on simulations.

6.2 PROBLEM FORMULATION

The DTC method developed for a Direct Three-Level Matrix

Converter (DTMC) uses the input phase voltage vectors (short vectors) and
the input line voltage vectors (long vectors). In the proposed algorithm, the
large vectors are applied during the torque transition states whereas the short
vectors are applied during the steady state conditions. This results in the
reduction of the torque ripple. However, the short vector causes serious
problem of fluctuations in the voltage at the input filter capacitance. Hence,
we obtain an output voltage from the DTMC that is asymmetric and has a
non-zero average value. In this chapter, a solution to minimize these
 158

fluctuations is presented. An additional voltage hysteresis band is used for

reducing the voltage deviation at the neutral point due to the application of the
short vector. The performance of the DTC scheme for the DTMC is
investigated with MATLAB based simulations over a range of viable speeds
and torques.

6.3 DIRECT TORQUE CONTROL OF INDUCTION

MACHINES USING POWER CONVERTERS

Direct torque control (DTC), proposed by Takahashi (1986), is a

prominent control method that has found broad implementations, especially in
industrial applications. This technique allows for independent control of the
induction motor flux and the electromagnetic torque. Based on the commonly
adopted space phasor dynamic model (Bose 2004 and Novotny 1996),
Equations (6.1) to (6.6) give the dynamic model of an IM

a d ψ as
a a
V =R i +
s s s + j ω a ψs (6.1)
dt

a d ψar a
0 = Rr ir + + j ( ωa - ωr ) ψ s (6.2)
dt

ψas = Ls i as + Lm i ar (6.3)

ψar = Lr i ar + Lm i as (6.4)

3
Te = P ψ as × i as (6.5)
2

d ωm J d ωr
T e - TL = J = (6.6)
dt P dt

where, vs, ψs, ψr, is and ir are the stator voltage, stator flux, rotor flux, stator
current and rotor current vectors respectively; ω r and ωm are the rotor speed in
rad/s and the mechanical speed in rpm respectively; L s, Lr and Lm are the
stator, rotor and magnetizing inductances respectively; T e, TL, J and P are the
 159

electromagnetic torque, load torque, system inertia and the number of pole
pairs respectively. These space phasor quantities are expressed in the arbitrary
reference frame, which rotates at an arbitrary speed. The superscript ‘a’
denotes that the quantities are in the arbitrary reference frame. In the
stationary reference frame, the stator voltage vector given in Equation (6.1) is
replaced by Equation (6.7), where the superscript ‘s’ denotes that the
quantities are in the stationary reference frame.

s s d ψss
V s = Rs i s + (6.7)
dt

Assuming that over a small period of time, the voltage drop across
the stator resistance can be neglected, Equation (6.7) can be rewritten as
Equation (6.8).

Δ ψs
Vs = (6.8)
Δt

From Equation (6.5), the relationship between the stator flux, the
rotor flux and the electromagnetic torque can be expressed by Equation (6.9).

3
Te= P |ψ s| |ψ r|sin θsr (6.9)
2

Equation (6.9) shows that the electromagnetic torque is affected by

changes in the stator flux ψ s, the rotor flux ψr , and θsr which is the angle
between ψs and ψ r.

The fast variation of the stator flux compared to that of the rotor
flux causes the stator flux to lead the rotor flux. Therefore, over a small period
of time, the rotor flux is assumed to have a slower rotation compared to the
stator flux. For this reason, when the appropriate space vector (voltage vector)
is applied to a power converter, the stator flux will change quickly. Hence, the
 160

angle between the flux vectors θsr will increase, which will cause an increase
in the electromagnetic torque Te . In other words, the variation of the stator
voltage will affect both ψs and θsr . This principle is used in the DTC to achieve
the desired torque response and correct the flux trajectory of the IM.

With the input voltages, the line currents and the present switch
position as the inputs, the estimator model (Bose 2004) calculates the actual
flux, torque and speed of the motor. The errors in the flux and the torque are
fed to the two-level flux comparator and the three-level torque comparator
respectively, as shown in Figures 6.1(a) and 6.1(b). In the classical DTC, to
reduce the switching frequency and the torque ripple, the three-level
hysteresis band (Beerten et al 2009) is used.

+1 +1
0 ΔΨs 0 ΔTe
0 0
-1 Ψs_ref -1
Ψs - ΔΨs Ψs + ΔΨs Te – ΔTe TL Te +ΔTe

(a) (b)

Figure 6.1 Hysteresis comparators (a) flux and (b) torque

The stator flux locus is forced to follow a circular path by limiting

the magnitude of its error to within the two-level hysteresis band.
Figures 6.2(a) and 6.2(b) show that when the errors in the stator flux touches
the upper or lower hysteresis band, an appropriate voltage vector is used to
decrease or increase respectively the stator flux magnitude corresponding to
the sector (position) in which the stator flux is present. Similarly, the torque
of the IM is forced to follow the load torque TL by limiting the magnitude of
its error to within the three-level hysteresis band. When the error in
electromagnetic torque touches the upper level or the lower level of the
hysteresis band, an appropriate voltage vector is used to decrease or increase
 161

respectively the torque, based on the sector (position) in which the stator flux
is present. Figure 6.2(c) shows that when the error in the electromagnetic
torque touches the zero level of the hysteresis band, the zero voltage vectors
are applied to maintain the torque constant. Practically the torque does not
remain constant due to the losses in the machine, but still a zero voltage
vector is applied under such condition in order to reduce the switching
frequency and to minimize the torque ripple.

As an example, let us consider that the stator flux vector is lying in

sector 1, as shown in Figure 6.2(a). The voltage vectors V 2 and V6 are used to
increase the flux while the voltage vectors V 3 and V5 are used to decrease the
flux. Among these, voltage vectors V 2 and V3 result in an increase of torque
while the voltage vectors V5 and V6 result in a decrease of torque. Vectors V 0
and V7 are used to maintain the flux and the torque almost constant. The
outputs of these comparators are fed to an optimal switching table (OST). The
switch position corresponding to the selected vector is applied on the power
converter without any modulator. Table 6.1 shows the OST for the VSI.

Vb
γ
V3 [010] V2 [110]

3 1

Va
V4 [011] V1 [100]
4 6

5
V5 [001] V6 [101] V0 [000]
V7 [111]
Vc

Figure 6.2(a) Inverter voltage vectors and corresponding flux variation

 162

qs
V4 . Δt4
E
D V3. Δt3

V2 . Δt2
B

C
V3. Δt1
S(3) S(2) A

π/3

S(1)
S(4) ds

S(6)
S(5)

2HBΨ

Figure 6.2(b) Locus of the stator flux

Te + ΔTe

TL= 3 Nm
Te – ΔTe

TL =0

Figure 6.2(c) Locus of the electromagnetic torque

Table 6.1 Optimal switching table of the VSI for the DTC

Sector HΨ=-1 HΨ=1

of Ψ HT=-1 HT=0 HT=1 HT=-1 HT=0 HT=1
1 V2 V0 V6 V3 V7 V5
2 V3 V7 V1 V4 V0 V6
3 V4 V0 V2 V5 V7 V1
4 V5 V7 V3 V6 V0 V2
5 V6 V0 V4 V1 V7 V3
6 V1 V7 V5 V2 V0 V4
 163

Figure 6.3 shows the space vectors for the MLI. Table 6.2 gives the
extended OST of the MLI for the DTMC. In order to reduce the torque ripple,
the short vectors of the MLI are also used in addition to the large vectors.
Thus, the DTC scheme is modified to have a new torque hysteresis
comparator that will provide five different levels instead of three levels, to
distinguish between the small and the large positive and negative torque
errors, as shown in Figure 6.4.

ΔΨ3L
Vb
ΔΨ2L
V2 L
ΔΨ3S
V3 L ΔΨ4L ΔΨ1S ΔΨ1L
V3 S V2 S ΔΨ5S
2 ΔΨ6L
3 1 ΔΨ5L

Va
V4L V4S 4 6 V1S V1L
5
V5 S V6 S

V5 L V6 L

Vc

Figure 6.3 MLI space vector and the corresponding variation in the
flux
 164

HT
2

1
-LEr -SEr ET
SEr LEr
-1

-2

Figure 6.4 Five-level torque hysteresis comparator

Table 6.2 Extended optimal switching table of the MLI for the DTC
Sector of Ψ

HΨ=-1 HΨ=1

HT=-2 HT=-1 HT=0 HT=1 HT=2 HT=-2 HT=-1 HT=0 HT=1 HT=2

1 V2L V 2S V0 V6S V6L V3L V3S V0 V5S V5L

2 V3L V 3S V7 V1S V1L V4L V4S V7 V6S V6L
3 V4L V 4S V0 V2S V2L V5L V5S V0 V1S V1L
4 V5L V 5S V7 V3S V3L V6L V6S V7 V2S V2L
5 V6L V 6S V0 V4S V4L V1L V1S V0 V3S V3L
6 V1L V 1S V7 V5S V5L V2L V2S V7 V4S V4L

6.3.1 Modified DTC Scheme for the CMC

As in the VSI, the CMC DTC scheme uses the same reference
quantities such as the flux and the torque that are controlled by selecting the
appropriate output voltage vectors. In addition, the control of the input current
that is essential in the CMC is initiated by selecting the appropriate input
 165

current vector. Hence, the choice of the switching configuration for the OST
is made on a different basis as described next (Matteini 2001).

Once the classical DTC scheme of the inverter has selected the
optimum vector to be applied to the machine, it is a matter of determining the
corresponding matrix converter switching configuration. For example, if the
VSI output vector V1 has been chosen, from Table 6.1, Figure 6.2(a) and
Figure 6.5(a), it can be seen that the CMC can generate the same vector by
means of the switching configurations ±1, ±2, and ±3. Keeping in mind the
input current control we can see that not all of them can be usefully employed
to provide an equivalent of the vector V1.

Vb VB
±4, ±5, ±6 ±2, ±5, ±8
2 2
3
3 1 ±1, ±2, ±3 1
4 VA
4 Va
6
5 6
5 ±1, ±4, ±7
±3, ±6, ±9
±7, ±8, ±9 VC
Vc (a) (b)

Figure 6.5 (a) CMC output voltage vectors and (b) input current vectors

For simplicity, it is considered that the input power factor is to be

controlled at unity. Then the sector information of the input voltage vector e i
indicates the sector in which the reference current is present. If the e i is in the
sector 1, from Figure 6.5(b), it can be seen that the switching configurations
to be used are +1 and –3 as these CMC vectors maintain the current in the
same direction. It has been verified that whatever is the sector that the vector
is in, the matrix converter has always two switching configurations for each
 166

VSI output vector chosen by the classical DTC scheme without affecting the
current direction. This redundancy can be used to control the input power
factor in addition to the control of the stator flux and the electromagnetic
torque.

The average value of the sine of the displacement angle ψ between

the actual input current vector (filtered input current) and the corresponding
input phase voltage vector ei is chosen as the third control variable. This
results in an additional sine-hysteresis comparator, as shown in Figure 6.6(a),
which employs the finally selected two CMC vectors (leading vector and
lagging vector) as the error reaches the band limit. Representation of the
control of the input power factor with the leading and the lagging vectors are
shown in Figure 6.6(b). The modified OST for the matrix converter with
current control is presented in Table 6.3. When the zero vectors V 0 or V7 are
selected by the inverter stage, an appropriate zero vector of the CMC is
selected based on the minimum input phase voltage at the time of selection
(Ortega et al 2008). This is done to reduce the CMV in the IM.

±2, ±5, ±8
+1
0 Sin (α)
0 -3
-1 ei
Ψ=0
Sin (ψ - θ) Sin ψ Sin (ψ + θ)
i
+1
±3, ±6, ±9 ±1, ±4, ±7

(a) (b)
Figure 6.6 (a) Sine-hysteresis comparator and (b) leading and lagging
vectors for the input current control
 167

Table 6.3 Optimal switching table of the CMC for the DTC

Input current sector number

1 2 3 4 5 6
Bψ +1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1
V1 -3 1 2 -3 -1 2 3 -1 -2 3 1 -2
V2 9 -7 -8 9 7 -8 -9 7 8 -9 -7 8
V3 -6 4 5 -6 -4 5 6 -4 -5 6 4 -5
V4 3 -1 -2 3 1 -2 -3 1 2 -3 -1 2
V5 -9 7 8 -9 -7 8 9 -7 -8 9 7 -8
V6 6 -4 -5 6 4 -5 -6 4 5 -6 -4 5

6.4 DIRECT SPACE VECTORS OF THE DTMC

The control method that is proposed relies on the space vector

representation of the DTMC switching configurations. The direct space
vectors of the DTMC can be classified as i) Rotating space vector consisting
of (a) circular rotating space vectors (6) and (b) elliptical rotating space
vectors (18), ii) Zero vectors (4) and iii) Stationary (or) pulsating space
vectors consisting of (a) long vectors (line vectors 18) and short vectors
(phase vectors 18). This control method makes use of the stationary space
vectors (long and short) configurations only. Figure 6.7 and Table 6.4 show
the space vector distribution of the stationary vectors and the zero vectors.

Table 6.4 Stationary space vector distribution table of the DTMC

Switching

Abc Vab Vbc Vca iA iB iC iN e0 α0 ii βi

 168

+1 ABB VAB 0 -VAB ia -ia 0 0 2 0 2 π

V i -
3 AB √3 a 6
-1 BAA -VAB 0 VAB - ia ia 0 0 2 0 2 π
- VAB - ia -
3 √3 6
+2 BCC VBC 0 - VBC 0 ia -ia 0 2 0 2 π
V i
3 BC √3 a 2
-2 CBB -VBC 0 VBC 0 -ia ia 0 2 0 2 π
- VBC - ia
3 √3 2
+3 CAA VCA 0 - VCA -ia 0 ia 0 2 0 2 7π
V i
3 CA √3 a 6
-3 ACC - VCA 0 VCA ia 0 -ia 0 2 0 2 7π
- VCA - ia
3 √3 6
+4 BAB -VAB VAB 0 ib -ib 0 0 2 2π 2 π
V i -
3 AB 3 √3 b 6
-4 ABA VAB -VAB 0 -ib ib 0 0 2 2π 2 π
- VAB - ib -
3 3 √3 6
+5 CBC -VBC VBC 0 0 ib -ib 0 2 2π 2 π
V i
3 BC 3 √3 b 2
-5 BCB VBC -VBC 0 0 -ib ib 0 2 2π 2 π
- VBC - ib
3 3 √3 2
+6 ACA - VCA VCA 0 -ib 0 ib 0 2 2π 2 7π
V i
3 CA 3 √3 b 6
-6 CAC VCA -VCA 0 ib 0 -ib 0 2 2π 2 7π
- VCA - ib
3 3 √3 6
+7 BBA 0 -VAB VAB ic -ic 0 0 2 4π 2 π
V i -
3 AB 3 √3 c 6
-7 AAB 0 VAB -VAB -ic ic 0 0 2 4π 2 π
- VAB - ic -
3 3 √3 6
+8 CCB 0 -VBC VBC 0 ic -ic 0 2 4π 2 π
V i
3 BC 3 √3 c 2
-8 BBC 0 VBC -VBC 0 - ic ic 0 2 4π 2 π
- VBC - ic
3 3 √3 2
+9 AAC 0 -VCA VCA -ic 0 ic 0 2 4π 2 7π
V i
3 CA 3 √3 c 6
-9 CCA 0 VCA -VCA ic 0 -ic 0 2 4π 2 7π
- VCA - ic
3 3 √3 6
+10 ANN VAN 0 -VAN ia 0 0 -ia 2 0 2 0
V i
3 AN 3 a
 169

Table 6.4 (Continued)

Switching

Abc Vab Vbc Vca iA iB iC iN e0 α0 ii βi

-10 NAA -VAN 0 VAN -ia 0 0 ia 2 0 2 0

- VAN - ia
3 3
+11 BNN VBN 0 -VBN 0 ia 0 -ia 2 0 2 2π
V i
3 BN 3 a 3
-11 NBB -VBN 0 VBN 0 -ia 0 ia 2 0 2 2π
- VBN - ia
3 3 3
+12 CNN VCN 0 -VCN 0 0 ia -ia 2 0 2 4π
V i
3 CN 3 a 3
-12 NCC -VCN 0 VCN 0 0 -ia ia 2 0 2 4π
- VCN - ia
3 3 3
+13 NAN -VAN VAN 0 ib 0 0 -ib 2 2π 2 0
V i
3 AN 3 3 b
-13 ANA VAN -VAN 0 -ib 0 0 ib 2 2π 2 0
- VAN - ib
3 3 3
+14 NBN -VBN VBN 0 0 ib 0 -ib 2 2π 2 2π
V i
3 BN 3 3 b 3
-14 BNB VBN -VBN 0 0 -ib 0 ib 2 2π 2 2π
- VBN - ib
3 3 3 3
+15 NCN -VCN VCN 0 0 0 ib -ib 2 2π 2 4π
V i
3 CN 3 3 b 3
-15 CNC VCN -VCN 0 0 0 - ib ib 2 2π 2 4π
- VCN - ib
3 3 3 3
+16 NNA 0 -VAN VAN ic 0 0 -ic 2 4π 2 0
V i
3 AN 3 3 c
-16 AAN 0 VAN -VAN -ic 0 0 ic 2 4π 2 0
- VAN - ic
3 3 3
+17 NNB 0 -VBN VBN 0 ic 0 -ic 2 4π 2 2π
V i
3 BN 3 3 c 3
-17 BBN 0 VBN -VBN 0 -ic 0 ic 2 4π 2 2π
- VBN - ic
3 3 3 3
+18 NNC 0 -VCN VCN 0 0 ic -ic 2 4π 2 4π
V i
3 CN 3 3 c 3
-18 CCN 0 VCN -VCN 0 0 -ic ic 2 4π 2 4π
- VCN - ic
3 3 3 3
 170

±4, ±5, ±6
2

±13, ±14, ±15

1
3

±10, ±11, ±12

±1, ±2, ±3
4 6

±16, ±17, ±18

5
±7, ±8, ±9

Figure 6.7 (a) DTMC direct voltage space vectors

±2, ±5, ±8
3 2

±11, ±14, ±17

4 1
±10, ±13, ±16

±3, ±6, ±9 ±1, ±4, ±7

±12, ±15, ±18

5 6

Figure 6.7 (b) DTMC direct current space vectors

The 18 long vectors are numbered as ±1, ±2, ±3, ±4, ±5, ±6, ±7, ±8
and ±9. Similarly, the 18 short vectors are numbered as ±10, ±11, ±12, ±13,
±14,±15, ±16, ±17 and ±18.
 171

6.5 DIRECT TORQUE CONTROL OF AN INDUCTION

MACHINE USING THE DTMC

The classical DTC scheme of the MLI is used as the basis for the
DTMC DTC scheme. Once the optimum vector to be applied to the IM is
selected from Table 6.2, it is only a matter of determining the corresponding
DTMC switching configuration. If the selected MLI vector is a long
vector VL, then the equivalent long vector of the DTMC is selected from
Table 6.3. Table 6.4 shows that the long vectors of the DTMC do not
contribute to the neutral current and this allows the use of the same procedure
of the CMC for selecting the equivalent DTMC long vector.

If the selected MLI vector is a short vector V S, then for selecting

the equivalent short vector for the DTMC, a modified procedure is adopted
and is as explained in the next section.

6.5.1 Modified Optimal Switching Table for the Short Vectors VS

The short vectors of the DTMC contribute to neutral current that

creates asymmetric voltages at the input filter capacitance with an average
value different from zero. Hence, an additional voltage hysteresis comparator
for reducing the voltage deviation at the neutral point is used.

6.5.1.1 Neutral current balancing with the voltage hysteresis

comparator

One of the problems in the use of the DTMC is the input filter
capacitor voltage imbalance. To understand this issue, we have to study the
effect of each type of short voltage vectors on the deviation of neutral point
voltage VN and current IN. Let us analyze the deviation of V N due to the two
short vectors, +10(ann) and -11(nbb). As illustrated in Figure 6.8, the sign of
the neutral point current (IN) determines the sign of the neutral point voltage
deviation (Δv) given by Equation (6.10).
 172

Δv = V cA + V cB + V cC (6.10)

It is observed from Figure 6.8 that every short vector V S has

another short vector VS having the same direction of the voltage but opposite
direction of the current.

A A
B
Ia B Ia
C C a
a
VcB
VAN VNB
VcA VcC VcA VcC
VcB
IN IN b c
b c

-Ia -Ia
(a) (b)
Figure 6.8 Neutral current (IN) for (a) space vector +10 (ann) and (b)
space vector -11 (nbb)

This provides us with the possibility of reducing the voltage

imbalance at the neutral point through the application of this vector pair. To
keep the deviation of the neutral point voltage Δv within a specified limit
(-V0, +V0), a two-level voltage hysteresis controller is defined, as shown in
Figure 6.9. For the short vectors VS, the appropriate DTMC vectors are
selected from the OST given in Table 6.5.

+1
0 Δv
-1
-V0 0 +V0

Figure 6.9 Voltage hysteresis comparator

It can be concluded that once the classical DTC scheme of the MLI
selects the voltage vectors to be applied to the IM, it is only a matter of
 173

selecting the corresponding DTMC vector. When VL is selected, Table 6.3 is

used to obtain the equivalent DTMC vector. Similarly, when V S is selected,
Table 6.5 is used to obtain the equivalent DTMC vector.

Table 6.5 Optimal switching table of the DTMC short vectors Vs for the
DTC

Input current sector number

1 2 3 4 5 6
Bψ
+1 -1 +1 -1 +1 -1 +1 -1 +1 -1 +1 -1
BV
V1S +1 +10 +10 -12 -12 +11 +11 -10 -10 +12 +12 -11 -11
-1 -12 -11 +11 +10 -10 -12 +12 +11 -11 -10 +10 +12
S
V2 +1 -16 -16 +18 +18 -17 -17 +16 +16 -18 -18 +17 +17
-1 +18 +17 -17 -16 +16 +18 -18 -17 +17 +16 -16 -18
S
V3 +1 +13 +13 -15 -15 +14 +14 -13 -13 +15 +15 -14 -14
-1 -15 -14 +14 +13 -13 -15 +15 +14 -14 -13 +13 +15
S
V4 +1 -10 -10 +12 +12 -11 -11 +10 +10 -12 -12 +11 +11
-1 +12 +11 -11 -10 +10 +12 -12 -11 +11 +10 -10 -12
S
V5 +1 +16 +16 -18 -18 +17 +17 -16 -16 +18 +18 -17 -17
-1 -18 -17 +17 +16 -16 -18 +18 +17 -17 -16 +16 +18
S
V6 +1 -13 -13 +15 +15 -14 -14 +13 +13 -15 -15 +14 +14
-1 +15 +14 -14 -13 +13 +15 -15 -14 +14 +13 -13 -15

Figure 6.10 shows the block diagram of the proposed DTC scheme
for the DTMC. The estimators shown in Figure 6.10 require the knowledge of
the input and the output voltages and currents. However, only the input
voltages and the output currents are measured in each cycle period, because
the other quantities can be calculated from the actual switching configuration
of the DTMC.
 174

Vin Vin

Vin
Vin_Sector

Vin_Sector

Vector selection Vector

Test

Classical DTC vector Selection of the 3 level VSI {MLI}

DTMC POWER
CONVERTER
CT VL
Tref T
CΨ
OR

T Cφ Vin_Sector

Table 6.3
φref
VS
φest

selection Table 6.5

CΨ
sin Ψest φSect
sin Ψref
T CΨ
Iout

T CV
ΔV ref
Test φest Sin Ψest ΔV
ΔV
Torque , Flux, sinΨ Estimators & {ΔV}-Generator
Induction Motor

Vin Iout Switching States

Figure 6.10 Block diagram of the proposed DTC scheme for the DTMC

It is well known that we can express the electromagnetic torque in

Park’s frame with the stator and rotor currents given in Equation (6.11).

3
Te= L (i i - i i ) (6.11)
2 m ds qr qs dr

Since the frequency of the rotor current is very lower than the stator
current, it can be concluded that the dynamics of the torque is directly
affected by the dynamics of the stator current and vice-versa. Hence, the
harmonic content in the stator current can be taken as a measure of the ripple
content in the torque of the IM.
 175

6.6 SIMULATION

Figure 6.11 shows the simulation results of the DTMC connected to

a 3-phase, 400 V, 50 Hz, 1430 rpm, 4 KW induction motor. The reference
speed of the IM is increased from zero to its rated value and is operated under
no-load till 0.6 s. From 0.6 s onwards the IM is operated with a load of 7
N-m. At 1s the reference speed is slowly decreased and is set to 54% of its
rated speed, as shown in Figure 6.11(a). Figure 6.11(c) indicates the variation
of current in the IM. It can be seen from Figure 6.11(d) that the input power
factor is controlled under all dynamic and steady state conditions for the
proposed DTC technique. Figure 6.11(b) illustrates the variation of the
electromagnetic torque of the IM for load disturbances and set point
variations. Figure 6.11(e) shows the capacitor voltage deviation in the
DTMC-DTC scheme when the IM is operated under load disturbances and set
point variations. Figure 6.12 shows the variations in the stator flux and the
rotor flux magnitudes for the DTMC- DTC scheme at a sampling frequency
of 2.5 kHz.

The analysis has shown that the proposed control scheme can
provide good performance for the IM at unity input power factor. The input
line current can be significantly distorted if the input power factor is not
closer to unity and the line currents also get distorted even if the sampling
frequency is not sufficiently high.

150
Sp eed (rad /sec)

100

50

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time(s)

(a)

Figure 6.11 (Continued)

 176

10

Torq ue (N -m ) 5

-5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s)

(b)

10

5
Ia (A)

-5

-10
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s)

(c)

40
VA (V) , IA (A)

20

-20

-40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s)

40 40

20 20
VA (V) , IA (A)

VA (V) , IA (A)

0 0

-20 -20

-40 -40
0.8 0.81 0.82 0.83 0.84 0.85 0.86 0.87 0.88 0.89 0.9 1.3 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.4
Time (s) Time (s)

(d)

Figure 6.11 (Continued)

 177

Voltage Deviation (V)

2

-2

-4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (s)

4
Voltage Deviation ( V)

-2

-4
0.5 0.51 0.52 0.53 0.54 0.55 0.56 0.57 0.58 0.59 0.6
Time (s)

(e)

Figure 6.11 (a) Speed of the IM, (b) torque of the IM (c) input current of
the IM, (d) scaled input voltage (230/6) and input current of
the DTMC, (e) filter capacitor voltage deviation

(a) (b)

Figure 6.12 (a) Variation of flux (a) stator and (b) rotor
 178

The torque ripple of a machine Tripple is given by (Tmax–Tmin)/ TAvg.

However, an alternative method to find the ripple content of the torque is to
examine the harmonic content of the machine’s input currents. It can be seen
from Figures 6.13(a) and 6.13(b) that the harmonic spectrum has a higher
magnitude around the average switching frequency of 2.5 kHz for both the
CMC-DTC and DTMC-DTC switching scheme. In both the cases, the lower
order harmonics are less than 5% which is well within the acceptable limits.
When comparing the magnitude of the lower order harmonics it can be seen
from Figure 6.14 that the current pulsations and magnitude of the 5 th and 7th
harmonics are reduced considerably in DTMC-DTC as compared to the
CMC-DTC. Hence, there is a considerable reduction in the torque pulsations
in the DTMC-DTC. Figure 6.15 shows the dynamic response for a step
command in torque for both the CMC-DTC and the DTMC-DTC. In both the
cases, the response of the system is found to be identical.

Fundamental (30Hz) = 8.762 , THD= 8.74%

Mag (% of Fundamental)

0
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Frequency (Hz)

(a)

Figure 6.13 (Continued)

 179

Fundamental (30Hz) = 9.41 , THD= 7.12%

Mag (% of Fundamental) 3

0
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Frequency (Hz)

(b)

Figure 6.13 Harmonic spectrum of the motor current waveform

(a) CMC-DTC and (b) DTMC-DTC

Figure 6.14 Output current harmonics comparison of DTMC-DTC and

CMC-DTC
10

8
Torque (N -m )

0
0.95 1 1.05 1.1 1.15 1.2 1.25
Times (s)

(a)
Figure 6.15 (Continued)
 180

10
T o rq u e (N -m )
8

0
0.95 1 1.05 1.1 1.15 1.2 1.25
Time (s)

(b)
Figure 6.15 Response to a step torque command (a) CMC-DTC
and (b) DTMC-DTC

As expected from the simulation, the performance of the drive

system based on the DTMC-DTC technique is satisfactory, showing an
acceptable level of torque and current ripple. In addition, the dynamic
response of the system is not affected in the DTC scheme for the DTMC.

6.7 SUMMARY

This chapter discusses the modified DTC to deliver fast and

superior torque response using the DTMC. An optimized switching table
(OST) is formulated considering the effects of the load and the velocity of the
motor on the torque changes. Moreover, the selection of vectors is based on
having the least torque ripple. A closed-loop control strategy is presented for
regulating the voltage deviations of the capacitors and restricting them to
specified limits along with the input power factor control. Simulation results
demonstrate that the proposed technique fulfils this objective, even in the
presence of a pulsating torque. The results obtained demonstrate that the
torque ripple is substantially reduced in the DTMC-DTC scheme as compared
to the CMC-DTC scheme.
 181

CHAPTER 7

CONCLUSION AND SCOPE FOR FUTURE WORK

7.1 CONCLUSION

The matrix converter is an array of 3×3 bidirectional switches

functioning as a direct AC–AC converter. It directly interconnects two
independent multi-phase voltage systems at different frequencies. The matrix
converter, known for more than thirty years, achieves bi-directional power
flow, independent control of the input power factor, buck operation and
frequency conversion. Since then it has appeared as an alternative solution for
adjustable speed AC drive applications. In the conventional VSI, the
multi-phase rectification stage, bulky DC link and the associated input filter
add weight and unreliability to the system. The role of the matrix converter as
an all silicon solution (except for the need of storage elements for the input
current filter), high power density converter and an alternative to conventional
AC-to-DC-to-AC converters has attracted researchers to find solutions for
problems that prevents it from appearing in the industry. The delay was
mainly due to several practical obstacles related to the complex switching
methods, problems related to commutation of bi-directional switches and
much more to the stability study of the converter along with its input filter.

This thesis presented easier methods for implementing complex

switching strategies, studying and mitigating the effects of unbalance, and
topological changes to increase the performance indices. The thesis also
suggests modulation techniques to eliminate the common mode voltage and a
new direct torque control procedure for controlling an induction motor fed by
the modified matrix converter topology. In all cases, the direction of the
 182

research work is to focus on the development and analysis of the PWM

techniques for different control objectives.

Since the switching strategies play an important role in obtaining

the desired performance, this work focused on the details of the PWM
techniques. In this regard, a PWM control algorithm has been developed that
offers a switching strategy, termed as the Minimum Error Switching Strategy
(MESS), suitable for matrix converters operating under high switching
frequencies. Its superiority lies in the ease of implementation, simplicity,
reduced switching losses and its suitability at high switching frequencies.

The work also introduces a simple carrier based modulation

technique, termed as the DIDC PWM technique, as an alternative way of
implementing the space vector technique for the matrix converter. Based on
the analysis carried out on the original DIDC PWM technique, the thesis
proposes a modified control algorithm. This modified algorithm reduces the
input current harmonic distortion without affecting the output side
performance. The performance of this algorithm has been verified through
numerical simulations. An experimental setup of the DIDC PWM technique
was developed and tested for the suitability of its implementation.

The thesis also presents techniques to eliminate and reduce the

common mode voltage in matrix converter fed induction motor. For
eliminating the common mode voltage in the matrix converter, an SVPWM
technique based on the rotating space vectors was proposed. Based on the
analysis of the technique, the thesis proposed the use of a six-phase matrix
converter and a modified rotating space vector technique. These modifications
result in the increase of the voltage transfer ratio without introducing the
common mode voltage. In addition, the work also brings out the conditions
under which the approach fails to eliminate the common mode voltage. The
proposed technique and the simulation results portray the usefulness and
limitations of the scheme.
 183

Real-time systems are unbalanced to a certain extent and distorted

by nonlinear loads. The capability to compensate for input voltage
disturbances is a mandatory feature for reliable and efficient control
algorithms. For improving the performance of the matrix converter under
non-ideal input conditions, a harmonic tracking algorithm based on the
oscillations of the Fictitious DC Bus(FDCB) was proposed. Simulation results
prove that the tracking control algorithm can successfully cope with the
unbalance and the non-sinusoidal input conditions and mitigate the effects of
the unbalance at the output. However, the unbalance at the input causes
degradation of the input current quality.

The proposed Direct Three-Level Matrix Converter (DTMC)

topology with the indirect space vector modulation reduces the THD at the
output of the matrix converter. The technique makes available the capacitor
neutral point to the load through three additional switches and ensures the
reduction of the THD based on the idea of the nearest three-vector selection.
In addition, it addresses the problem of neutral current balancing using the
concept of virtual vectors. Finally, the analytical loss modeling of the DTMC
involves deriving the mathematical relations based on the behavioral model of
the semiconductor devices. An experimental setup for the DTMC was
developed and tested for the suitability of its implementation.

Finally, the formulation of the Direct Torque Control (DTC), for

the DTMC, for reducing the torque ripple in the matrix converter based
system is illustrated. The DTC control method for the DTMC uses the phase
voltage vectors (short vectors) and the line voltage vectors (long vectors).
Using long vectors during the torque transition states and using short vectors
during the steady state results in the reduction of torque ripples. However,
short vectors result in the serious problem of voltage fluctuations at the input
filter capacitance. Because of this, we obtain an output voltage from the
DTMC that is asymmetric and having a non-zero average value. An additional
voltage hysteresis band reduces the voltage deviation at the neutral point
 184

during the application of the short vectors and minimizes these fluctuations.
Simulation results portray the improved performance of the DTC scheme for
the DTMC.

7.2 SCOPE FOR FUTURE WORK

The following specific areas are suggested for further research.

(i) To investigate further the effects of system faults such as

single-phase, short-circuit fault etc. on the matrix converter.

(ii) To study and implement the three-phase to single-phase

matrix converters for high frequency transformers to bring
out the importance of the matrix converter for such
applications.

(iii) To further investigate the proposed DTMC configuration for its

common mode effects, over modulation operation and study its
control capability in closed-loop systems for real-time
applications.

(iv) To investigate the application of the matrix converters in the

wind energy conversion systems using direct power control
methods for the Doubly Fed Induction Generators (DFIG).

(v) To validate in real-time the direct torque control technique by

integrating the electric machine, DTMC and the controller.
In addition, to investigate and implement Artificial
Intelligence (AI) techniques in the vector control of the
DTMC based system.

(vi) To investigate the hybrid DTC-SVM technique for DTMC

for further improving the performance of torque ripple in the
induction motor drives.

(vii) To investigate in details the stability of matrix converters.

 185

APPENDIX 1

PHOTOGRAPHS OF THE INDIVIDUAL HARDWARE UNITS

Figure A1.1 Current and voltage sensors used for the DTMC topology

Figure A1.2 Analog data acquisition board used for the DIDC PWM
technique
 186

Figure A1.3 Matrix converter power module used for the DIDC – PWM
technique

Figure A1.4 Direct three level matrix converter (DTMC) power module
 187

Figure A1.5 Concept 6SD 106 EI driver board

Figure A1.6 FPGA Spartan 3A DSP board

 188

Figure A1.7 FPGA Spartan 3E board

 189

APPENDIX 2

PROCEDURE FOR OPTIMUM INDIRECT

SVM FOR THE DTMC

Vectors to be applied in a sampling period T s and their

corresponding duty cycles are calculated for a DTMC as explained in chapter
5. The next step is to decide how the active vectors are to be ordered within
the sampling period Ts and which zero vector is to be used among [aaa],
[bbb], [ccc] and [nnn]. Among the possible combination of switching
sequence between the Fictitious Three-Level Converter (FTC) and the
Fictitious Inverter (FI) stage of the DTMC, a criterion which restricts the
switching transition to be only once during each vector change is used to
minimize the switching losses. Aalburg university proposed the four rules that
assure the minimum number of switching transitions which is called as the
optimum indirect SVM for CMC.

With the same rules the modified optimum indirect SVM for the
DTMC is formulated which ensured that the switching transitions are
minimum.

For Region-1 or Region -2 of input current sector

1) The input vector sequence is γδQ1Q2 – Q2Q1δγ

where, γ and δ indicates the duty cycles of the active line vectors and Q 1and
Q2 indicates the duty cycles of the active phase vectors.
 190

(i.e.,) Q1 = Q2 = Q/2 where, Q is the duty cycle of the virtual

vector.

2) If the sum of the current and voltage hexagon sectors is odd,

the output vector sequence must be (αβ) (βα) (αβ) (βα) - (αβ)
(βα) (αβ) (βα).

3) If the sum of the current and voltage hexagon sectors is even,

the output vector sequence must be (βα) (αβ) (βα) (αβ) - (βα)
(αβ) (βα) (αβ).

Table A2.1 gives the optimized SVM switching sequence for

region-1 of the input current sector and Table A2.2 and Table A2.3 gives the
switch transitions of each leg of the DTMC.

Table A2.1 Switching sequence for current sector-1, region-1 and

voltage sector-1

βγ αγ αδ βδ Θ βδ αδ αγ βγ
abb aba aca acc acc aca aba abb
Tβγ/2 Tαγ/2 Tαδ/2 Tβδ/2 Tθ Tβδ/2 Tαδ /2 Tαγ/2 Tβγ/2
V1 – IL1 V6 - IL1 V6-IL2 V1-IL2 V1-IL1 V6-IL2 V6-IL1 V1-IL1

βQ1 αQ1 αQ2 βQ2 αQ2 αQ1 βQ1

ann ana nbn nbb nbn ana ann
Tβ01/2 Tα01/2 Tα02/2 Tβ02 Tα02/2 Tα01/2 Tβ01/2
V1 - IP1 V6 - IP1 V6 - IP6 V1 - IP6 V6 - IP6 V6 - IP1 V1 - IP1
 191

Table A2.2 Switching transitions for current sector-1, region-1 and

voltage sector-1
Switches ON
Vector pair
Leg 1 Leg 2 Leg 3
V1 - IL1 SAa SBb SBc L
V6 - IL1 SAa SBb L SAc
V6 – IL2 SAa SCb SAc
V1 - IL2 SAa SCb SCc L
P
V1 - IP1 SAa SNb P SNc
P
V6 - IP1 SAa SNb SAc
P P
V6 - IP6 SNa SBb SNc
V1 - IP6 SNa SBb P SBc P
V6 - IP6 SNa SBb SNc P
P
V6 - IP1 SAa SNb SAc
V1 - IP1 SAa SNb SNc P
P
V1 - IL2 SAa SCb SCc P
V6 - IL2 SAa SCb P SAc L
L
V6 - IL1 SAa SBb SAc
L
V1 - IL1 SAa SBb SBc
P

Table A2.3 Number of transitions of each leg for region-1 of input

current sector
Leg No. Phase event Line event
1 2 0
2 4 2
3 8 4
Total 14 6
Total events 20

Figure A2.1shows the commutation events of the DTMC for current

sector-1, region -1 and voltage sector-1.

SAa SAc
SAb
SBb
SBc
SBa
SCb
SCa SCc

SNa SNb SNc

 192

Figure A2.1 Commutation events of DTMC in a switching period for

current sector-1, region-1 and voltage sector-1

The energy lost in switching in input current sector -1, region -1and
voltage sector-1 is given by the Equation (A2.1)

Esw 1 = K . (|v AN|. i a +(|v BC|+|v CN|+|v BN|). i b + (|v AB|+|v AC|+2|v AN|+|v BN|+|v CN|) . i c )
R

(A2.1)

Eon + EOff + Err

where, K=
V r Ir

In a similar procedure, the switching sequence for Region-3,

Region-4 and Region-5 can be formulated and the total switching events can
be determined. Table A2.4 gives the total switching events for Region 3 and
Table A2.5 gives the total switching events for Region 5.

Table A2.4 Number of transitions of each leg for region-3 of input

current sector

Arm No. Phase event Line event

1 6 0
2 4 2
3 12 4
Total 22 4
Total events 26

The energy lost in switching in input current sector-1, region -3 and

voltage sector-1 is given by the Equation (A2.2).
 193

Esw = K . (3|v AN|. i a +(|v BC|+|vCN|+|v BN|). i b+ (|v AB|+ 3|v AN|+|v BN|+ 2|v CN|) . i c )
R3

(A2.2)

Table A2.5 Number of transitions of each leg for region-5 of input

current sector

Arm No. Phase event Line event

1 4 0
2 6 0
3 10 0
Total 20 0
Total events 20

The energy lost in switching in input current sector -1, region -5 and
voltage sector-1 is given by the Equation (A2.3).

Esw = K . (2|v AN|. i a +(|v BN|+2|v CN|). i b + (|v BN|+2|v AN|+2|v CN|) . i c )
R5

(A2.3)
 194

APPENDIX 3

CIRCUIT DIAGRAM FOR EACH MODULE OF THE DIDC

PWM HARDWARE UNIT

Figure A3.1 Zero crossing detector circuit

Figure A3.2 Triangular wave generator circuit

 195

Figure A3.3 Precision rectifier circuit

Figure A3.4 Concept 6SD 106 EI driver circuit

 196

Figure A3.5 Complete DIDCPWM pulse generator circuit

 197

Figure A3.6 PCB Layout of the complete circuit

 198

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LIST OF PUBLICATIONS

International Journals

1. Senthil Kumaran, M., Siddharth, R., Stalin, M., Divakhar, A. and

Ranganath Muthu.“Constant Pulse Width Switching Strategy for
Matrix Converter”, International Review on Modeling and Simulations
(IREMOS), Vol. 4, No. 6, pp. 2954 - 2960, 2011.

2. Senthil Kumaran, M., Siddharth, R. and Ranganath Muthu. “Matrix

Converter Switching Strategy for Abnormal Voltage Conditions using
Selective Harmonic Tracking Algorithm”, International Journal of
Modeling and Simulation, Vol. 32, No. 1, pp. 57 -64, 2012.

3. Bhanuchandar, M., Adwaith, V., Senthil Kumaran, M. and Ranganath

Muthu. “Fuzzy logic methodologies for torque ripple frequency
reduction in direct torque control of an induction motor drive”, ARPN
Journal of Engineering and Applied Sciences, Vol. 7, No. 7, pp. 890-
899, 2012.

4. Bhanuchandar, M., Adwaith, V., Senthil Kumaran, M. and Ranganath

Muthu. “Twelve sector methodology for direct torque control of
induction motor with fuzzy logic”, International Review of Automatic
Control, (IREACO), Vol. 5, No. 4, pp. 516-522, 2012.

5. Senthil Kumaran, M., Siddharth, R. and Ranganath Muthu. “Minimum

Error Switching Strategy for Matrix Converter with Input Current
Control”, International Review of Electrical Engineering (IREE), Vol.
7, No. 4, pp. 4768 – 4775, 2012.

6. Senthil Kumaran, M., Siddharth, R. and Ranganath Muthu. “Elimination

of Common Mode Voltage using Rotating Space Vectors and Phase
Shifted Dual Source Matrix Converter,” accepted for publication in
The International Journal for Computation and Mathematics in
Electrical and Electronic Engineering (COMPEL).
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International Conferences

7. Senthil Kumaran, M., Pandikumar, M. and Ranganath Muthu.

“Simplified Control of Matrix Converter Represented as a Three-level
Inverter”, Proceedings of the International Conference on Trends in
Industrial Measurements and Automation (TIMA), pp. 110-113, 2009.

8. Senthil Kumaran, M., Siddharth, R. and Ranganath Muthu. “Real-Time

Controller Design for Matrix Converter for Load and Input
Variations”, Proceedings of the Third International Conference on
Emerging Trends in Engineering and Technology (ICTETET),
pp. 396-400, 2010.

9. Abishek Rajaraman, L. A., Ganesh, P., Geeth Prajwal Reddy, P. and

Senthil Kumaran, M. “FPGA Triggered Space Vector Modulated
Voltage Source Inverter Using MATLAB/ System Generator®”,
Proceedings of the Third International Conference on Trends in
Information, Telecommunication and Computing, Lecture Notes in
Electrical Engineering, Vol. 150, pp. 505-514, 2013.
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CURRILUM VITAE

Mr. M.Senthil Kumaran was born on 23 November 1977 at

Tamilnadu in India. He did his schooling at the S.B.O.A Higher Secondary

School, Chennai, Tamilnadu. He obtained his bachelor’s degree in Electrical

and Electronics Engineering from the Madras University, Chennai in the year

1999 and master’s degree in Electrical and Electronics Engineering with

specialization in Applied Electronics from Madras University, Chennai in

2001. At present, he is working as Assistant Professor in the Department of

Electrical and Electronics Engineering, Sri Sivasubramania Nadar College of

Engineering, Kalavakkam, Tamilnadu, India. He has been pursuing his

research work since January 2007 under the supervision of

Dr. Ranganath Muthu.

He is a life member of the Indian Society for Technical Education

and a Member of IEEE.

He has 12 years of teaching experience and has published 9

technical papers in various international and national, journals and

conferences. His research areas of interest include power electronics and

control for wind energy conversion systems.