Bits in RN point of Logic Solver:

Bit Description Set Reset Alarmed Details

0 Configured OK NCONF No The Logic Solver is configured.
The Logic Solver has been
1 Commissioned OK DECOMD No
recognized by Ovation.
The logic Solver is being
2 Calibration ACTIVE NACT No
calibrated.
The Logic Solver is being
3 Configuring State ACTIVE NACT No
configured.
There is an error in the
Communication
4 ERROR OK Yes communication with the Logic
Error
Solver.
There is an error in the Logic
5 IO Channel Error ERROR OK Yes
Solver's I/O channels.
The primary Logic Solver is in
6 Primary in Control PRIM BCKP No
control.
The Logic Solver is locked and
7 Locked LOCKED UNLCKD No
cannot be loaded.
The configured scan rate for
Scan Rate the Logic Solver is exceeded
8 OVRLD NOVRLD Yes
Overloaded by the estimated execution
time.
Any Module in At least one of the control
9 DEBUG NORMAL Yes
Debug Mode modules is in debug mode.
At least one Hardware Alert
10 Failed Alert FAILAL NORMAL Yes Condition from Failed
category is active.
At least one Hardware Alert
11 Maintenance Alert MTNCAL NORMAL Yes Condition from Maintenance
category is active.
At least one Hardware Alert
12 Advisory Alert ADVSAL NORMAL Yes Condition from Advisory
category is active.
No communication with Logic
13 Communication Alert COMMAL NORMAL Yes Solver. No other conditions
can be detected.
At least one of the control
Register CtrlMod for
14 UNREG NORMAL No modules is not configured for
SIF data
SIF data.
There is no communication
Logic Solver
15 RLOST OK Yes with one of the Logic Solvers
Redundancy Lost
from redundant pair.
Bit 10 is set if one of the Failed Hardware Alert Conditions is active. Logic Solver is communicating
but important functions are not operable or there is a loss of control functions. Table below lists
possible Failed Hardware Alert Conditions:

Condition Description

Program Assertion Unspecified internal software error.

System software could not obtain a hardware or software

Resource Error
resource.

Failure detected in periodic main processor RAM test or powerup

Memory Test Failure
test of RAM and NVM.

Active logic solver has gone through reset (becoming Standby)

Uncommanded Switchover
because it was not communicating with controller.

Control Subsystem Compare The main processors detected a mismatch in outputs or secure
Error parameter data.

Timeout on Inter-Processor Link

Number of scans exceeded for a main processor to respond to
Between Main Processor 1 and
the other.
Main Processor 2

Timeout Between Main Number of scans exceeded for IOP to respond to MP2. Fatal
Processor 2 and I/O Processor errors detected by IOP are revealed by this condition

Main Processor 2 Compare of MP2 validates the calculations being done by IOP. A mismatch in
I/O Processor Data Failed the results of the calculations causes this condition.

Main Processor 2 Compare of

MP2 has detected that IOP is communicating at an improper rate.
I/O Processor Frequency Failed

A control or communications task did not have a timely or proper

Task Checkpoint Error
completion.

Control Subsystem Scheduling MP2 is unable to complete writing of output values prior to
Error beginning new control execution.

One logic solver of a pair has gone through reset because both
Dual Active Logic Solvers
logic solvers were in the active role.

A powerup test failed on a watchdog timer or a processor did not

Hardware Watchdog Failure
arm its watchdog within the window during operation.

Both SIS Net Connections on

Neither main processor can communicate on the peer bus.
Logic Solver are Bad
Bit 11 is set if one of the Maintenance Hardware Alert Conditions is active. All functions are working
but attention is required. Table below lists possible Maintenance Hardware Alert Conditions:

Condition Description

One or more calibration values outside of valid range or no

Calibration Data Questionable
manufacturing calibration data is present.

The logic solver has set the actual scan rate longer than the
Modules Not Executing at
configured scan rate based on the estimate of execution time at
Configured Scan Rate
download.

NVM battery or chip failure has been detected during periodic

Non-Volatile Memory Battery or test, or not able to restore saved parameter records after
Chip Failure powerup or reset, or a CRC error occurred when writing a
parameter record.

Channel Error Status of one of the channels is bad.

Any condition other than 'high error rate' is active in Peer to

SIS Net Error
Peer Subsystem.

Partner card is not responding to heartbeat messages or is

Partner Not Available
responding but is not configured.

Partner Not Present Partner card is not responding to heartbeat messages.

One card of a redundant pair is not communicating with the

Card Not Communicating
controller. Not applicable to a simplex logic solver.

Card Not Fully Operational The same condition was present on back-to-back resets.

Bit 12 is set one of Advisory Hardware Alert Conditions is active. A single condition on the hardware
is detected. Attention is required. Table below lists possible Advisory Hardware Alert Conditions:

Condition Description

SIS Net High Error Rate High peer bus error rate detected by MP1 or MP2.

I/O Processor Communication MP2 sees a high percentage error rate in communications with
Error the I/O processor.

Non-volatile Memory availability for parameter change records

Non-Volatile Memory Alert
is low or exhausted.

High Railbus Error Rate MP1 sees a high percentage error rate in communications with
 the controller.

MP1 sees a high percentage communications error rate on the

High Redundancy Link Error Rate
redundancy link.

I/O Processor Integrity Error The I/O Processor is reporting a calibration or self-test error.

Self-Test Incomplete A periodic memory test did not complete in the allotted time.

Configuration Mismatch Between

Controller sees mismatch between configured and reported CRC.
Logic Solver and Controller

There is a high percentage error rate in communications

Internal Communications Error
between the main processors.

Non-Critical Mismatch Between The main processors have determined a mismatch in dynamic
Main Processor Data data other than outputs and secure parameter values.

The number of days since the last proof test is approaching the
Proof Test Reminder is Active
required proof test interval.

The number of days since the last proof test has exceeded the
Proof Test is Overdue
required proof test interval.

The idle time on one or both of the main processors is less than
CPU Free Time Low <20
20% of the total task time.

A non-critical task has not completed properly in one of the

Task Checkpoint Alarm
subsystems.

Hardware Alert Condition events are sent to Sis Events Viewer application. By using Sis Events Viewer
client it can be checked which Hardware Alert Condition caused that bit is set.
Bits in RN point of SIS Data Server:

Bit Description Set Reset Alarmed Details

Configured in SISIO
0 OK NCONF No SIS Data Server is configured.
driver
The primary SIS Data Server is
1 Primary In Control CTLR NCTLR No in
control.
There is an error in the SIS
Railbus Data
2 Communication ERROR OK Yes Server communication over
Error the
backplane.
There is a timeout in the
SIS LAN
communication between a SIS
3 Communication ERROR OK Yes
Data Server and an Ovation
Timeout
Controller.
There is no communication
Communication With
4 COMM NCOMM Yes with primary SIS Data
Primary
Server.
There is no communication
Communication With
5 COMM NCOMM Yes with secondary SIS Data
Secondary
Server.
The secondary SIS Data Server
6 Secondary In Control CTLR NCTLR No
is in control.
There is no communication
7 Redundancy Lost RLOST OK Yes with one of the SIS Data
Servers from redundant pair.
There is no communication
between SIS Data Server and
Left Repeater
8 COMERR OK Yes left SIS Net Repeater or error
Communication
occurred in repeater’s
Communication subsystem.
There is an error in Local Peer
Left Repeater Local
9 LOCERR OK Yes subsystem of left SIS Net
Peer
Repeater.
There is an error in Remote
Left Repeater
10 REMERR OK Yes Peer subsystem of left SIS Net
Remote Peer
Repeater.
There is no communication
between SIS Data Server and
Right Repeater
11 COMERR OK Yes right SIS Net Repeater or error
Communication
occurred in repeater’s
Communication subsystem.
There is an error in Local Peer
Right Repeater Local
12 LOCERR OK Yes subsystem of right SIS Net
Peer
Repeater indicates an error).
There is an error in Remote
Right Repeater
13 REMERR OK Yes Peer subsystem of right SIS
Remote Peer
Net Repeater.
14
15

In case of configuration with simplex SDS bit 5 is set all the time.

Bit 9 (bit 12 in case of secondary SIS Net repeater) is set if one of the following conditions occurred:

- The local peer bus is not terminated or is improperly terminated.

- The local peer bus receiver or transmitter hardware indicates an error.

Bit 10 (bit 13 in case of secondary SIS Net repeater) is set if one of the following conditions occurred:

- The remote fiber-optic ring is not connected to both the transmit and receive ports.

- Another SISNet Repeater in the ring is powered down, causing a broken ring condition.

- The fiber is crossed such that a primary SIS Net Repeater is receiving messages from a
secondary SIS Net Repeater.

- Remote fiber-optic ring hardware indicates a transmitter or receiver error.

Bits 8 – 13 can be set if there is more than one SIS Data Server in the system.
Bits in RN point of Control Module:

Bit Description Set Reset Alarmed Details

Module Not
0 NREG OK Yes The module is not registered
Registered
Control Module is in Debug
Mode. The Debug Mode is
where you can
perform functional testing of
1 Debug mode DEBUG NORM Yes
safety
logic by forcing input values
for
algorithms.
2 - 10 Not used
There is active SIF Error
11 Active SIF Error SIFERR NOERR Yes
condition in Control Module.
There is active SIF Alert
12 Active SIF Alert SIFALT NOALRT Yes
condition in Control Module.

SIF Error condition is caused by one of below:

- 'Memory Failure' or 'Config Error' bit set in BLOCK_ERR in a Calc/Logic block

- An input block or parameter reference has Bad status on its output
- An output block or secure parameter has Bad status on its output
- 'Failed to Confirm Following a Command to Trip' bit set in DO_ALERTS in an output
block
- 'Fault State Active' bit set in BLOCK_ERR in an output block
- A wired block input is not able to update due to write-check fail or error on source
read
- 'Output Failure' bit set in BLOCK_ERR in a Calc/Logic block
- A parameter path is unresolved
- Module not executing at configured scan rate
- The last partial stroke test failed

SIFAlert condition is caused by one of below:

- A wired input to a block or secure parameter is being forced in Debug

- An AVTR or DVTR block has a bypassed input
- An AVTR or DVTR block has an active startup override
- A bypass or startup override is about to expire in an AVTR or DVTR block
- Trip consensus in an AVTR or DVTR block
- Pre-trip consensus in an AVTR block
- Deviation limit exceeded in an AVTR or MID block
- A CEM block has a non-zero FIRST_OUT
- A CEM block Effect is being forced
- A DO or DVC block is in an Off state
- Debug View Active
SIF Errors and SIF Alerts are sent to Sis Events Viewer application. By using Sis Events Viewer client it
can be checked which condition caused that one of bits is set.