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    106 views18 pages

    ANIC-15S Instruction Manual

    Uploaded by

    Muhamad Priyatna

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    © All Rights Reserved
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    RS MANUAL ONE-BOARD ANNUNCIATORS TYPE ANIC-15S INSTRUCTION MANUAL EES IDE IZUMI Corporation CONTENTS 3. SPECEFTCATIONS 2 3-1 Specifications and Ratings 3 3-2 Contained Sequence Patterns List ‘ 5-3. Sequence Pattern Chart 5 3-4 Dimensions and Mounting Holes 10 4, SESTEN EstoN n 41 Operation Mode Preset Sxttchee au 42 ‘Terminal Arrangement and Taput/Outpue Cheeast 15 43 moose Wiring Depron v 4-4 Input Deley Tie and First Out Circutt Resolution 2 45 Manttor Chreutt « 22 46 Installation « 2 UT other totes 2% 5. PANEL mnstALLATION Sel Wire Size and Wiring . 7. TERM EXPLANATION .. 8. APPLEGATION CIRCUIT 81 Solid State Alarm Input. 1. GENERAL anufacturing processes. In highly automated and robotized plants Sophisticated control technology 1a employed co enoure safe operation. Tn the event of accidental control cireutt breakdown, hovevery an stouncsneor plays great role in aonieoring process condition eth have a good "human interface" to fulfill ite task of alarm and super: syatem Incorporating 1t: high reliability im the event of emergency, fand. a good hunan iacerfacs ‘iso, there are other requirenents which an sanuneLator must eatiaty The one-board annunciator ANIC-15S has performance and reliability as high ab those of the conventional solid state tard nodule type, wacediy taproved! in fasilstating operation a yscen con Processing, encbling various types of operation by presetting opera Fon condsvions. [2 FEATURES AND PART NAMES 2-1. Features (1) Many circuits and sequence patterns quence patterna. It mainly conforas to J1S/ISA standards end tncor~ orates many first-out operations. As all signals necessary for a (2) Markedly facilitated design & wiring Coaplicated viring between modules and auxiliary céreuit design for ach syeten are conspiccousiy simplifted in ehe annunciaeor. In de- Haningy you have only eo write down preset avitch conditions refer Ting £0’ che baste wiring diagrans (3) One or two alare systems can be constructed using one unit Syrten construction 4s executed Via operation node selection suftehen on the board, For construction of two aystes, different sequence patterns can be used for Light and he fons, a bell and 2 buzzer can be employed or eifferent purpore (4) Programming via preset switches No instruction vora or gramar te necessary for programing. Thus, to power failure or noise ir elininaced: * (5) Highty retiable design, environnent- and noise-resistant Aavthe input/output edveuit 4s feolaced fron the contral (CPU) circuit, cust 12 under supervision at all tines due to the original eelé-diag nostic function. 22 Part Manes ‘Output & power supply roser ovitehes $2 Pee tts’ | TSE vows + Mintetiocaautn ene | | [HOME svitebes ana) re election switches/ PLASHER * indicated vis this | (SEEESTSES.) Lyset fsa i Mounting piece \low MaDe 1 JAPA” Fig. 21 -2- 3,_ SPECIFICATIONS 3-2 Contained Sequence Patterns List Del Speciftntions and Ratings i Toa ne Seria a + recfornance specications an satinge j Tex [are] Se" | ma wins — =a = Hen ee oe ces et one [Bema t vwpefools [2 [a [a] [o se Vfwcormuew Pret —ar ]-|-[-[-l- l= PF a SEES fom rm cman | act | awa fon] |= fowl =f [=] = nie ane | a sou 2 | mer one Maa = Jon] - | - fox} - =| -|- ea 1 ie mt oe nar foxfonl - fowler] ~| =] fe Aen eee setae Seems Hew o e [5 [reece ere =] - Jon} — | - fox} —]- [= =e Sra 6 | net on] - fon} ox} ~ fox] — | - [nest 1 sone = Jon ox] Jon] on] | ~ |= ee a 1 faa te oe . ono ono os] os| — | ~|- ES SS 10 | eran ne on| | — Jos] ~ |- rc fox} - fox} -|- © [somone ee eae escent ftow i. on} om} — Jon] — | cee eee ow =| = Joon] = Fis mere [Be ete i amma [rn toe 14 seta atee ce cov} ~ Jon] on} — | oe ° uno ~ sf] St" [ese or 15 |p ee oo eon] = > oe serene fin et a Wore See Section 4-1 (3) "Sequence Pattern Setting". 1 apecftenttone Note 2 TSte A1ST/1540516.1 1981 sas oetscion? = ae ote 5: Circuits 1 £0 3 and 4 6 of the ip avitcher axe set on GROUEL =a Stent SF hones Side fesectivey ne eee — 3-3 Sequence Pattern Chart (Fig. 3-1) Mos $_ ISA Nos FACIL quence patter: No. 1_ISA Woe acl, & EF one ps squance pattert Wo. 2164 to Seer TI be por eae ai 5 oO © Sequence pattern: Wo. 6 184 No. P21 gk B quence pattern No. 318A Ho. HL 8 | rom Oo «@ ose -6- Sequence pattern: No, & ISA No. 8 i squence pattern: No ~ee Sequence pattern: No. 14 3-4 Dimensions and Mount ing Hotes factactes) latte 25 poles ise U3T6 [Ceanteres Ta) poe tar | so/ae & operation ° ed + Nount ng ypitcable cetptng reies cage 1 7 t FREI 5 et cue 7.380 4 | | Pitas se] ihe ia Fi aa rite -9- - we SYSTEM DESIGN ‘This section describes how to design an amunctator aystea sing the ANIC-I58 (operation mode and preset evitehes in particular). 4-1 Operation Mode Preset Switches Firstly, set the operation mode corresponding to the specifications fof the danuaciator systen to be designed. Uhether the 15 ansuneintor Circuits in board are used as one aysten of divided into to #ys~ fous te decided vie operation mode. Set the "aoritor output node’ {Gas Note) in the case of ope aystem and the "E22 outout mode" in the case of tvo syeteus. Suitehing ie performed at the first clr cule of SW2..” (See Pigs 4-1.) Represents the Firat circuit of SW. Set the dip sviteh to left aide {in the care Of soaitor output rode, and to right side in che Cees of 822 ouepvt mode. wow/az2 Fig. G1 u Monitor output mode ‘he buile-fa 15 annunciator circusta operate in the same sequence pattern, constituting @ single alarm ayaten, The monitor output se Note 1) £5 allocated eo the MOS/B22 OUTPUT terminal - (2) 822 output mode The built-in 15 annunetetor efreuits are divided into two groups, for anmuneiator systems for erg. Light and heavy malfunctions. The Firat Sroup conaints of the first to fifth eLreuite, the second of the sixth fo fiteeanch circuits. Different sequence patterns can be selected for the two groups (eee Note 2). To this wode, the buzzer output on foup 2 (aalfunction vecuzvence side) ix allocated to MON/B22. OUEPUE ferminal. Accordingly, exgcuce viring es tilustrated in Pig. 4-2 to allocate bell to Reavy malfunction side and busser to Light malfunction side. ote It See 4-5 Monitor Cixeuse. Note 2: See 4-7 Other Notes (2). -ne i urput terminals SE I xo busser esreutt Celghe pet fune~ ‘ifs side) | to vert etveute Cease Base Gx.) croup It croup 2 Ayye and Byst Relays fo7 bell and busser drive Heavy malfunction side AUZZERL ovTPUT Tra To bell ciresie Light ‘naituneeton side MON/B22 OUTPUT tisseey To buster efreutt Fig. 2 2 (3) Sequence pattern setting ‘The AMIC-ISS containg 16 asqvence patterns. The sequesce pattern can be selected via avitches Sil. ‘hen operation mode is set £2 the “aonstor output mode", one of the 16 patterns ix selected by combinating the dip svitches of swl's First to Eoures circuits. ‘then operation node és set to the "B22 output mode", one of eéght petterns is aelected as the sequence pattern of group 1 or 2 by com Dinating the dip switcher of SWi"s first to third or fourth to sixth circuits respectively (See Fig. &-3) ‘Ae for sequence putters that Can be aelected in each operation node, find the positions of dip awitcher, ses the sequence peteerns list te Section 3-2. For setting the sequence Select by conbinating pateern of group 1 these _euteches: For setting the sequence earn of group 2 bép aviteh ctreute to. a Ce) aRGR ER age Monit : od ea nde is selected. (Be ‘gure to turn off the Fifth end sixth cirenttes) Fig. 4-3 (4) No/NG switenes Switches from $2"s second clrcuft to US's eighth circuit are used to set each contact of alarm inpute to the anunciator eircule to NO (ornaily Open) of NC (loraally Closed). An example of setting {8 shown in Fig. fo =e Dip avigch postetone vhen the contacts of faze set £0 NO (black pare) Aterm input MOAN fe] fi: SH is nae F Foor art wow axe ated using a flow chert ‘Tats setting procedure can be repre: follows! saiece a Feisgs Se maps eee -u 4-2 Terminal Arrangement and Input/Output Circuit (2) Output terminals 4m the AVIO-I5S"s terminal arrangoneat, the signal input sfde ts rata] —yercinai Wane Operation [Eqetvatene cireuid separaved from the signal ouepue side.” For witing of each terninal oe pares ee ind Bante Uiriag Dicer ~ | oie | woven » oorrur [maser () output 3 E | cu | netoaw wz ovrpur |#eture aterm buzzer 2 (1) Input terminals 3 esa | woware ovteve |tooteer ovepur or q 3 BaeEes ay BAe E sat maT] Terainal None ‘Operation Bautvatent Circuie| | cas | eeasuen ovrevr — |rtasher output 2 BE yer [ae Busser stop input \ 2 | ore | @. russes oorrur [quick flasher output OES e| ee face AcRNOALEDGE Anpue ! B | cas | s. vuasnan oureur |siov flasher output a 2 Zles last Reset Seput 5 8 | cre | rinse sic. ovnrur [river atenat ootnue g 25 ] ce | etasuen smeur | asker énpoe £ " Hamp output 1 zB Re ee 77 © Cc va lane oosput 2 a q | oe |. muasmen anvur |stow eraser inner | §, & a lane ovtpue 9 Hyon | evase sto. ior [ricee stg sone | 22g se le cutmt 4 co | uw tse agp teat Input | 0 luse output 6 ma farm anpoe 1 =| er lamp output 7 : wo Atsem input 2 B] as leap output 8 3 Ma aterm Snowe 4 2 EWG loerp ourpuc 20 i ga as sare input 5 A : a | ssp ouepue 11 ey 3 pr Alara input 7 . . © Go ara output 13 ae @ Z| as nace tape 8 at a lamp output 26 al as jAlarm input 9 aa was (Lamp output 15 A) a0 lnare tapue 10 u 1 | ar a re 2) an Alarm input 11 ae } i cin pew J supp aa lave Sapa 12 Bay al ow ro Frame ground an arm Soput 13 aa wae sare sepa 1 aus tare tapue 15 Tle vermin -15- = 16. a3 Basie Wiring Dfagram Fig. 4-5 iilustrates the basic wiring diagram for connecting to oF ore ANICM15S units. The fleaher output signal of bourd Now I ie ‘ent noe only to thet board, but elso to other beards, so that Lenpe Flash in syachrontsn shen au alara Lemp flashes on board No. 1, 2, wee orn (530) ‘The pover upply chreule 1s divided into pover supplies for control ‘The control pover supply requires moothing capacitor Gl, but the ‘lanp power supply does Sot. Soy only s eaali capacitor for noise absorption is: installed, wifecting fill-vave rectificetion pulsating voteage. Determine the values of smoothing capacitor Cl and protective re sistor # from the following equstions! Ch = 660:F xm (The No. of boards) (the dielectric etrongth aust be SOV oF ire.) ReMax. 19 Hattager WE 4% (0.48)? C2 = 0.01uF to Oty (rhe dielectric serength must be 100V oF more.) Yoke? Use a power transformer whose prinary side 49 completely in- spulated from the secondary aide, 9 gecure aufety and prevent sen only one ANIC-15S untt {9 used, execute wiring of board No. 1 only. -u- a ‘ i a] ES eS i i el ; Es oF BEE 4 rt is Eo 4 es i + t t a 1 pee rmtorne Fig. 45 Explanation of wiring dtagras (1) Wiring Ltustraced vith contiquous Lines Represents the wiring alvays required regardless of che type of opera ‘tion mode or sequence pattern. Q Wiring dIlustrated vith dashed Tines Represents the wiring required depending on he type of operation role, syoron construction, and sequence pattern (9) Aare tapot Wo or NC con be selectod for each ctzeuit. Set according £0 the field conditions via preset evitches SW2 and 3 on the boar Note: Loup output No. Bn corresponds to slarm input terminsl No. dn. Get to 15) (6) Buzzer stop input and reset tnput Tis wiring 18 required vhen @ sequence pettern with » buzzer stop oF reset function ig selected. The buzzer atop input may be omitted for sequence patterns inwhich ACK input has a buzzer step function, as well as priority. ote: den the buster atop input fs connected to a sequence pattern vithoue a Buzzer stop input function, borser stop ie effected only while the input ia on. (5) Fuscefon test input and lamp test Soput ‘This wiring 2 necessary shan eh = ayaten: Tuncetons are required for @) wy Ry de the relay for buszer (1) drive (24V0C). A bell or burser 18 aceivated through the contact of this relay via external power supply. Connect a diode for surge voltage absorption (Vg 100Y, Ip 1A) seroes the relay coil. oD Bye This viring ie required vhon © sequonce pettern with @ return elar= funetion ts selected. Connect a diode as explained shove. @ ‘This relay works for onitor output vhen operation mode is set to oHTTOR This wiring 4s unnecessary when monitor output Sa: not required for a eyeten, Thie Pelay works for burzer (2) drive when operation node i= aet to BLL, “Connect a dioce a9 explained sbov sae ©) Quick flasher Line and slow flasher Line ‘Thia wiring 12 necessary when chess functions are included in the selected sequence pattern. In the baste wiring diagrax, bosré Wo. 1 is che mater unit, provid= ing flasher signal to subsequent boards. In such a wiring method, an orderly indication wieh the same flasher period for ail boards can be obtained by designating one board as master unit. (10) Fieee 1/0 tne hen the first-out operation is selected as sequence pattern, first signal input ie vired to first signal output for each bosrdy desig ating this connection, ax the Firat 1/0 Line. To divide first-out ‘nto groups, set up a ftzae 1/0 Line for each group a2 silustested An Pig, 46 ro Groep HT sow 0.+ ||] some m2 oe = _ First 1/0 Line = c ‘of aroup A. Group || somemes |I[ ove me toro mn iret 1/0 ine of group 8 Fig. 4-6 (11) The total of control and lanp currents fe concentrated to DO(~) of each board. Accordingly, use s wire with o proger diameter and counect DC(-) of each beard dérectly vo DC(-) of the pover supply, or toa 00(~) bus with a sufficteatly large current carrying capacity fe Secure safety. (See Fig. 7.) word Board rant Eee — (12) Power supply efreutt Alchough the control power supply {6 seperated from the lamp power Supply in che baste viving dtagran, they may be one single pover ‘supply. In such 8 case, se power supply Lines with a proper thick= fess, as the current on the lanp Line ts considerably larger ehan hae ‘on ehe control Line -20- (03) PG terminal Terainal No. O19 {9 FO (frane ground). This terminal is electrically Gonncted to the aetsl pare of the chaseis- Tt ts connected £0 the over supply in the form of AC via capacitors with some inpedanco, Stiustraeed in Pigs 4-8 = Be Jomesmer Fig. 4-8 FO terminal nay not be connected during norms! operation. If malfune~ Sons or electrostatic shocks are enussd by noise, ground © (1002) sasiaun)- Input Delay Time and First Out Circutt Resolution a Input delay tire ‘The input delay tine is the tine between reception of snpue signal and ending of output in the ANIC-I9§ internal eiveuie. Measures are takes {in both software and hardware to eliminate chatter and noise of input signal. "(See Fig. 4-9.) Signals of Idnsec or Jess... Not accepted Signats of 30nece or more... Accepted a6 si Signats of between 10 and JOnsec sre unsteady. signal aL le! Signal @ 42 not accepted a2 signal due to ste ov level, Signal ® ia not accepted due to ita short duration (lesa than 10mrce) Signal © ts sccopted. Fig. 49 2 First-out cireuit resolution ‘This Ls applied to sequence patterns vith a first-out Function (ss Note 1)." The resolution is a capacity to électiminate between the First aad subsequent clara inputs represented in tine difference. See Fig. S10, - ae © ec tara sapue A Alara input 8 hon Tz 4Oasec: Input A te accapted 5 the frst input, and input B as the subsequent. Hoth dnputs A and Bare accepted inpue. Jhon 7. 30maee the facet Fig. 4-10 Note: Sea section 7 Explanation of Terns. 4-5 Monitor Ctreuit ) Alarm trput monitor ‘The regult of OR operation of all alarm inpute sent into the boatd te ‘outputted co cerminel MON/322.. This signal beconer effective only shen operation mode 1s set to the "monitor output nede", ‘This output signal cen de connected to a relay, whose contact output Ss connected to an external circuit if necenasty, aa Allusttated fa Hig. fell. 9 external efreust fps a t Fig. ty (2) First-out circuit monitor Whether the voltage level of the fire¢ 1/0 Line te at "KY ox * detected vie chia elreult. By this, it can be determined whether first-out ts executed for the alarm dapat. Woon ftrst 1/0 Line ts at "x The alarm input 4s accepted sa a ftret inputs Te sara input 8 accepted subsequent input. shen first 1/0 Line te at "1" = 46 a The efreuse construction fo tllustrated ta Fig. 4-12, To (max) must bet mex, 250nA, aot Db Board (1) Board (2) Board (2) Ld wD se) hh Firet 1/0 Line ® (yeas oes In ea) Wore: In this figure, only the first output (Germinal No. C16) of board No. 1 15, surned OX, and all current flows there. +t zee Fig. 4-12 Instat lation Installation Install ANIO-15S untes waing the attaches mounting pieces. These ‘nouneing pieces con be installed oa the borrd either afdewaye of Tengthvise, Whon tvo or gore boards are instelled side by aide, make sprees for ventilation a@ {illustrated in fig. 4-13 #0 let Off heats BF wl z ca ease lea: S ea — | I sosce tor vetttatton Distesce between units Fig. 4-13 -Be (2) The open construction (ai) Dusty installation in panels ts adopted. Avoid ‘the following conditions: (A) An anbiene tonperature of Lees thon -10°C or more chan 450°C GS) Ainumidity of tees than 4st or more than 65% BE 1, meval powder Gy) Direce sunitghe (i) Vibrations oF shocks directly applied to the unit (Ex) Corrosive oF conbusesble passe (Wid) Vieiniey of high-voltage devices or motors 4-7 Other Notes (2) sen an 120 lamp Se used ae a Lemp output, conect 4e in a correct polarity so illuatrated t0 Pig. tele. cc+) | potarsey of 120 — a ap catpae Fig. 4-1 (2) At turning on power then power {9 turned on, output ia turned ON for an axtewuely short Eine (40 to 200 wee) until the internal voltage 4s eeabilisad.— than Internal voltage 1s stabilized, sll outpute are forcibly torned OFF for approx. 0.3 sec, causing buster stop, ACK and east dnpute to be Accoréingly, when an alarm input has elready been applied at curaing fom powers the eequence partera is settled after 0.5 seo upon under fgotmg transteion with besser top, ACK and reset inputs applied. (3) te ds possible to execute two different sequence patterns using one ‘IG=138 until by Setting the operation node to MZ? output node: However, ae ehe buzzer output fs comon co ftret 1/0 and retura alarm ines, independent {iret~out for each group cannot be executed when the firat-out operation type is selected Lor both groupe 1 and 2 Similarly, independent return alarm for each group cannot be executed ‘hen the return alarm operation type is selected for both groups 1 -- 5. PANEL INSTALLATION 5-1 Mire Size and Wiring Current flowing {nto the input elreutt fron the ANIG-138 £9 approx. Tay and leap output current ie 250ak max. So, the wire need not eo be Gxtrenely etek (0.75 to 1.25m¢ or Leas). Contral current per unit te nex. 008A. S0, a vite ap chick as char for lamp output can be used. Tn DC(=), the total of lamp output current, relay load Current and control current of the ANIG-I3S fesel! #lovs. So, use a'vize ar thick ae possible, although current varies greatly wlth the eating of the Iaep. See Fig. te? Execute wicing {nthe cane way as for conventional solid-state card nodules: Do not lay vires parallel to high-voltage or notor Lines. 5-2 Recessories and User's Space (1) tie Foltoving eccossories are attached to the ANIC-138. Indtcating plate (I pe) + ater the board umber and the nunber ‘of the selected sequence pattern in it and affix it on cover. (Fig. 2-1) See Mig. 5-1. Nouneing piece (4 pes) + See Section 4-6, Preset axitch cover (2 poss, Protects switches after setting against ‘seail and large) inadvertent operation, Use then 1€ ecezeary. Tdenetfseation No. shen two oF more ‘sequence pattern to, of each group vhen operation, ode. is set to the "322 output moce" The sequence pattern Nos. are entered according te Section 3-3. Fig. 5-1 Entry Example =~ (2) User's space A space in which uoers can urite freely 4a left open on the terminal rocks on the board (only alare input and Ianp output parte). Wrste vith a felt-tip pen using ol] paint, ete. Characters can be erased Using alechol or thinner, (Do not ub too hard.) 5-3. Notes (1) te etgheentng toraue of the terninal block cover suse be Sheen (2) the cetmping terminal contact size is apecified in Section 34 Dinen= ‘Hons and Mounting Holes: (3) do aot remove the cover. 2 6, MAINTENANCE AND CHECK [As the internal circuit of the AVIC-15S {9 composed of solid-state lenenes, components need not be replaced. However, melntenence land check of peripherai devices te necessary, as relays for busaer drive, indicating lemps, etc. are ured in the syste 6-1 Insulation Resistance and Dielectric Strength Test (1) Insulation resistance test Use a megger with a rating of SOOVDC or Less. Upon completion of testing, be sure to execute discharge vis short-etrculting, ea the internal capacitors for noise protection are charged. (See Figs 8.) @ Dielectric strength test As a Leakage current ie allowed through the interns] capacitor for eine provection, set the gensitivicy current (1)S00VAC” SOK=/60HE per fone board, approx. 2-54 at application). 6-2 check Execute chock at the completion of syaten construction, and periodic checks thereafter. "Alsoy check at any tine if necessary. The tens fo be checked are 1iated’ below. (2) At the comptetion of system construction (Prior to turning on power} (1) check polarity of power eupoly. 1 : Line tr 0G(-)- (4A) Check operation mode, sequence pattern and setting of NO/NC. (iA) chock for shorted Lamp load. See Fig. 6 (Gv) Contivn that the DC(-) line of each board hae @ sufficient current Confira that the conson stay actty. (2) At the completion of systen construction (After turming on power) (2) confirm char the voltage dz within 24¥DC 2 20%. GD Contten that the Funsing flasher on the bonré 4s flashing with « period of approx. 2 seconde (414) Confirm that’ the Lanp and function teste operate. (Gy) Gheck the Lamp output for each alae input aad the eequence pattorn. Limp power supply Check for ebse wrong witing (shore). Lamp output Fig. 6-1 - ar © Go Ce Cc 6-3 Troubleshooting (1) 1£ the error Lamp on the board Lighte, refer te the table below. ack teem caus Sear ep) Si otenge deep ore’ than328)" eptacenene Bomeged conetant Frewceract notee”" | eeansonner tn the 100/ (2) Notse voltage te induced at alarm input Line. Use an oscifloscope or a VON with a high input {apedance, although it is difficult to ascertsin co which extent noise voltage 1s induce AAs & counteruessure, install s capacitor and a resistor in the Yi ity of the alarm input terninai, ar illustrated in Pig. 6-2. reer am 6-4 Other Hotes (1) te atere co shorting caused by che Lamp base during Laup replacenent. (2) check always for enviromental stresses (voltage, temperature, dust, ete.) on the board or system, (3) 2£ any matfunceion occurs, note down the date of occurrence, the con 4icions at occurrence, the contents of the malfunction, tho tine ‘ince starting operation, ete. =m ze TERM EXPLANATION a Q a) o (5 (6) ‘this section explains terse important for understanding ANEC-15S operation. (ap Snciestes » synonya.) Lamp test Js executed to check for Lamp disconnection. One or several push- button avitches are generally provided for a eyaten and Lana, Leghe only then these ave turned OX.” Aa the test haw no Anfluence on ae~ {quence teaneieion, the origincl condition 1a restored whes input {2 tormed OFF. Function test Operation test 4s executed to check the operation of the aain circuit, generally vis one or seversl pushbutton switches on a ayaten- In this test, 4 preseribed sequence pattern fe executed in the came condseion 2@ fin'alera foput application. Accordingly, the buzzer of the systen ss activated. In a streutt ¢o which an slam input bas already be Applied, fonction test input tx ignored, but any cireust to which ‘lara input has aot been applied operates via this input. Soy note that ins etrete to slick en alarm input has already becn applied ‘via ACK or reset operation, soquence transition Se effected under Bis influence. Buzzer stop op Buzzer cancel, audible silence Stops only tho buszer ctreuit. Te does not operate n a coquence pattern without buzzer stop Function, except during buzzer stop input Ack. Is executed ues the operator acknowledges an alarm condition, gen rally effecting sequence transition savelving flasher or bareer Reset =p Manual reset ‘hen sequence transition has proceeded to the final stage, sequence returna to the initial condition vis reset~ Interlock with ACK. 15 provided tn nany cases: First-out (Operation) A malfunction occurring at first Se dtserininated from malfunctions feccurring subsequently in indleation via this function. This func~ ion 1s utetul for locating the cause of malfmetions when one mal= Function triggers others in a chain retction- ‘The AVICW158 containe eight sequence patterns with a firat-out func ‘elon, each having a different indication mode. For allocation of ftret-oue function co groupe, see Section 4-3-(10) ~ 2 (7) Return atarm (Operation) => Ringback (Operation) Alarm te given when the norael condition ts restored via this opera Clog. Tn sequence pattern t vitch thie clarm con be discrininsted from’ chae given io the event of malfunction, the buzzer outpue at Festofation is sent to terminal RETURN BZ OUTPUT. (8) First-out circuit release op First-out reset Returns the first-out cireuit of the eysten to the taftial condition. dn alnen dnput seat subsequent to this operation 4s accepted and i= Gieaced ae = first input Az this operation {2 used togecher with ACK. and reset in ANTC-15S Sequence patterns, conditions for first-out Tenet are specified. In ANIOW1S5 oF ANIC annuneistors, first-out reset Le effected vien the firee 1/0 Line is in level "i", (9) Alarm input op Malfunction signal, fietd contact Is the signal inputted from Field to the annunctator mein circuit. In general, {ets 2 NO or NC nechanicel-concact sight) from « seneing devicey But a solid-state signal can aloo be uaed. (20) Sequence pattern op Sequence table, sequence diagram operation chart Is the representatfon of lazp or buszer output operation corresponding to alare input using tables and figures. Tor the ANIC-I3S, conven Tonal timing charts vith the axis of absciaea as a tine axis are sed. Tough another representation called sequence table 1s used in ISA standeras, timtag charts, the sore common representation ‘mathod, re used here =». 8. APPLICATION CIRCUIT 2-1 Solid State Alarm Input (2) NPW transistor output (Including open collector output) Alarm signs source cies output e Alors snput terminal Fig. Bel Note 1: Ve of alere signal source mist be 50¥ or tess. Note 2: When "ALARM" ie set with ROW teanetstor "ON", set SWZ and Son the AKIC-158 for NO/NC swstening to NO. Note 3: lise a transiacor for alerm signal source with a dislectric strength of 5V of wore and Te of 209A or more. (2) PNP transistar output (Including open collector output) Alara tnpet terminal, Ato Aye Fig. &2 Note 1: Ve of alarm signal source mist be more then 20Y and Lese than 50V- Rimust be from, 470 to 6802, The wattage mist be nore han 2 (Ve/B)2 «Re Sihea "ALARM" ie set with PNP transistor "ON", set SWZ find 3 on the ANIC-ISS for switching HO/NC to" Nc. Use @ tranetstor for alace signal source with Te of 100a8 or pore, Reverse vithatand voltage of diods D mist be Sov oF more.

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