Features

• High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 8K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1K Byte Internal SRAM – Programming Lock for Software Security Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and MLF package Eight Channels 10-bit Accuracy – 6-channel ADC in PDIP package Eight Channels 10-bit Accuracy – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad MLF Operating Voltages – 2.7 - 5.5V (ATmega8L) – 4.5 - 5.5V (ATmega8) Speed Grades – 0 - 8 MHz (ATmega8L) – 0 - 16 MHz (ATmega8) Power Consumption at 4 Mhz, 3V, 25°C – Active: 3.6 mA – Idle Mode: 1.0 mA – Power-down Mode: 0.5 µA

8-bit with 8K Bytes In-System Programmable Flash ATmega8 ATmega8L Summary

• • • •

2486OS–AVR–10/04

Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.

Pin Configurations
PDIP
(RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A)

TQFP Top View
PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16

(INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7

1 2 3 4 5 6 7 8

PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)

32 31 30 29 28 27 26 25

PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2)

(T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4

MLF Top View

(INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

24 23 22 21 20 19 18 17

PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK)

2

ATmega8(L)
2486OS–AVR–10/04

(T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4

NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.

INTERFACE PORTD DIGITAL INTERFACE PORTD DRIVERS/BUFFERS PD0 . Block Diagram XTAL1 RESET PC0 .PB7 Block Diagram PORTC DRIVERS/BUFFERS PORTB DRIVERS/BUFFERS GND PORTC DIGITAL INTERFACE PORTB DIGITAL INTERFACE MUX & ADC AGND AREF PROGRAM COUNTER ADC INTERFACE TWI STACK POINTER TIMERS/ COUNTERS OSCILLATOR PROGRAM FLASH SRAM INTERNAL OSCILLATOR INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X WATCHDOG TIMER OSCILLATOR INSTRUCTION DECODER Y Z MCU CTRL. & TIMING CONTROL LINES ALU INTERRUPT UNIT AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - COMP.PC6 VCC XTAL2 PB0 .PD7 3 2486OS–AVR–10/04 . the ATmega8 achieves throughputs approaching 1 MIPS per MHz. allowing the system designer to optimize power consumption versus processing speed. Figure 1.ATmega8(L) Overview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle.

23 general purpose I/O lines. including C compilers. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. to minimize switching noise during ADC conversions. Timer/Counters. In-Circuit Emulators. The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities. The boot program can use any interface to download the application program in the Application Flash memory. the asynchronous timer continues to run. a programmable Watchdog Timer with Internal Oscillator. The Power-down mode saves the register contents but freezes the Oscillator. program debugger/simulators. disabling all other chip functions until the next Interrupt or Hardware Reset.The AVR core combines a rich instruction set with 32 general purpose working registers. and interrupt system to continue functioning. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU). Software in the Boot Flash Section will continue to run while the Application Flash Section is updated. the crystal/resonator Oscillator is running while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC. providing true Read-While-Write operation. 32 general purpose working registers. This allows very fast start-up combined with low-power consumption. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 AVR is supported with a full suite of program and system development tools. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip. three flexible Timer/Counters with compare modes. The device is manufactured using Atmel’s high density non-volatile memory technology. by a conventional non-volatile memory programmer. 512 bytes of EEPROM. a 6-channel ADC (eight channels in TQFP and MLF packages) with 10-bit accuracy. The Flash Program memory can be reprogrammed In-System through an SPI serial interface. and evaluation kits. internal and external interrupts. an SPI serial port. a byte oriented Two-wire Serial Interface. macro assemblers. and five software selectable power saving modes. In Standby mode. a serial programmable USART. allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. 1K byte of SRAM. The Idle mode stops the CPU while allowing the SRAM. 4 ATmega8(L) 2486OS–AVR–10/04 . allowing the user to maintain a timer base while the rest of the device is sleeping. or by an On-chip boot program running on the AVR core. Min and Max values will be available after the device is characterized. In Power-save mode. SPI port.

even if the clock is not running.6 is used as TOSC2. If the RSTDISBL Fuse is programmed. The Port D pins are tri-stated when a reset condition becomes active. PB7 can be used as output from the inverting Oscillator amplifier.. even if the clock is not running. RESET Reset input. If the Internal Calibrated RC Oscillator is used as chip clock source.. The Port B pins are tri-stated when a reset condition becomes active. Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System Clock and Clock Options” on page 23. The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. Port D also serves the functions of various special features of the ATmega8 as listed on page 61. Port D (PD7. Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The minimum pulse length is given in Table 15 on page 36. A low level on this pin for longer than the minimum pulse length will generate a reset. Shorter pulses are not guaranteed to generate a Reset.PB0) XTAL1/XTAL2/TOSC1/TOSC2 Digital supply voltage. Ground. PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Port C (PC5. A low level on this pin for longer than the minimum pulse length will generate a Reset. PC6 is used as an I/O pin.PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). If the RSTDISBL Fuse is unprogrammed... PC6 is used as a Reset input. The minimum pulse length is given in Table 15 on page 36. Depending on the clock selection fuse settings. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. PB7. The Port C output buffers have symmetrical drive characteristics with both high sink and source capability.1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. PC6/RESET 5 2486OS–AVR–10/04 . The various special features of Port C are elaborated on page 59. As inputs. The Port C pins are tri-stated when a reset condition becomes active.ATmega8(L) Pin Descriptions VCC GND Port B (PB7.. Port D pins that are externally pulled low will source current if the pull-up resistors are activated. As inputs. As inputs. even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. even if the clock is not running.PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). Depending on the clock selection fuse settings. even if the clock is not running. The Port B output buffers have symmetrical drive characteristics with both high sink and source capability.

it should be connected to VCC through a low-pass filter. Note that Port C (5.6). AREF is the analog reference pin for the A/D Converter. even if the ADC is not used.0).AVCC AVCC is the supply voltage pin for the A/D Converter. and ADC (7.6 serve as analog inputs to the A/D converter..4) use digital supply voltage. VCC.6 (TQFP and MLF Package Only) 6 ATmega8(L) 2486OS–AVR–10/04 . It should be externally connected to VCC. If the ADC is used. ADC7... Port C (3. In the TQFP and MLF package. AREF ADC7... These pins are powered from the analog supply and serve as 10-bit ADC channels.

121. 120 210 168 31. 190 95 98 99 99 99 99 99 99 100 100 Timer/Counter1 – Counter Register High byte Timer/Counter1 – Counter Register Low byte Timer/Counter1 – Output Compare Register A High byte Timer/Counter1 – Output Compare Register A Low byte Timer/Counter1 – Output Compare Register B High byte Timer/Counter1 – Output Compare Register B Low byte Timer/Counter1 – Input Capture Register High byte Timer/Counter1 – Input Capture Register Low byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – URSEL URSEL – EEAR7 – – – – UMSEL – EEAR6 – – – – UPM1 – EEAR5 – – WDCE – UPM0 – EEAR4 – USBS – EEAR3 EERIE – EEAR2 EEMWE AS2 WDE TCN2UB WDP2 UCSZ1 OCR2UB WDP1 UBRR[11:8] UCSZ0 – EEAR1 EEWE UCPOL EEAR8 EEAR0 EERE TCR2UB WDP0 115 117 117 117 41 155 153 18 18 18 18 EEPROM Data Register PORTB7 DDB7 PINB7 – – – PORTD7 DDD7 PIND7 SPIF SPIE RXC RXCIE ACD REFS1 ADEN PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC TXCIE ACBG REFS0 ADSC PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – DORD UDRE UDRIE ACO ADLAR ADFR PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 – MSTR FE RXEN ACI – ADIF PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 – CPOL DOR TXEN ACIE MUX3 ADIE PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 – CPHA PE UCSZ2 ACIC MUX2 ADPS2 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 – SPR1 U2X RXB8 ACIS1 MUX1 ADPS1 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM TXB8 ACIS0 MUX0 ADPS0 63 63 63 63 63 63 63 63 63 128 128 126 150 151 152 155 191 202 204 205 205 170 SPI Data Register USART I/O Data Register USART Baud Rate Register Low byte ADC Data Register High byte ADC Data Register Low byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 170 7 2486OS–AVR–10/04 .ATmega8(L) Register Summary Address 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20(1) (0x40)(1) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) Name SREG SPH SPL Reserved GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR Bit 7 I – SP7 INT1 INTF1 OCIE2 OCF2 SPMIE TWINT SE – – Bit 6 T – SP6 INT0 INTF0 TOIE2 TOV2 RWWSB TWEA SM2 – – Bit 5 H – SP5 – – TICIE1 ICF1 – TWSTA SM1 – – Bit 4 S – SP4 – – OCIE1A OCF1A RWWSRE TWSTO SM0 – – Bit 3 V – SP3 – – OCIE1B OCF1B BLBSET TWWC ISC11 WDRF – Bit 2 N SP10 SP2 – – TOIE1 TOV1 PGWRT TWEN ISC10 BORF CS02 Bit 1 Z SP9 SP1 IVSEL – – – PGERS – ISC01 EXTRF CS01 Bit 0 C SP8 SP0 IVCE – TOIE0 TOV0 SPMEN TWIE ISC00 PORF CS00 Page 9 11 11 47. 101. 65 66 70. 64 39 70 70 29 Timer/Counter0 (8 Bits) Oscillator Calibration Register – COM1A1 ICNC1 – COM1A0 ICES1 – COM1B1 – – COM1B0 WGM13 ACME FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR10 WGM10 CS10 56. 100. 120 71. 73.

3. 2. writing a one back into any flag read as set. thus clearing the flag. Note that the CBI and SBI instructions will operate on all bits in the I/O Register. 8 ATmega8(L) 2486OS–AVR–10/04 . Some of the Status Flags are cleared by writing a logical one to them. Refer to the USART description for details on how to access UBRRH and UCSRC. reserved bits should be written to zero if accessed. For compatibility with future devices.Register Summary (Continued) Address 0x01 (0x21) 0x00 (0x20) Name TWSR TWBR Bit 7 TWS7 Bit 6 TWS6 Bit 5 TWS5 Bit 4 TWS4 Bit 3 TWS3 Bit 2 – Bit 1 TWPS1 Bit 0 TWPS0 Page 170 168 Two-wire Serial Interface Bit Rate Register Notes: 1. The CBI and SBI instructions work with registers 0x00 to 0x1F only. Reserved I/O memory addresses should never be written.

N.N.H Z.C Z.V None Z.N.C.V. Rr Rd.C Z.N.C.ATmega8(L) Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd.K Rr.V.V.C None None None None None I None Z.C.K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF .N.H Z.V Z.N.C.Rr .N.H Z.C Z. Rr Rd Rd Rd.H Z.N.H Z. k s.Rr Rd. K Rd.V Z. Rr Rd.N. b P.K Rd. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare.N.V Z.V Z.V Z.V.V Z.H Z.C Z.V Z.H Z.H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg.C.V. Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal.K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr 1 R1:R0 ← (Rd x Rr) << 1 R1:R0 ← (Rd x Rr) << 1 PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 R1:R0 ← (Rd x Rr) << BRANCH INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks 9 2486OS–AVR–10/04 .C.C.V.C Z.V. k k k k k k k k k k k k k k k k k k Operands Rd.Rr Rd. Rr Rd.K Rd ← Rd .N.C Rdh:Rdl ← Rdh:Rdl . Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z.N. K Rd.V Z. b s.N.S Z. K Rdl.K Rd.K Rd.V. N.Rr Rd ← Rd . Rr Rd. Rr Rd. b Rr.K .N. Rr Rd.N.V.N.H Z.V Z.K Rd Rd Rd Rd Rd Rd.N. N.V. K Rd.C.S Z.N.C. Rr Rd. Signed Branch if Less Than Zero. Rr Rd.V.C.C. Rr Rdl.C Rd ← Rd .C. Rr Rd.N.C. N.N.Rr Rd.N. Rr Rd.H Z.V Z. b P. Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd .V.V Z.

X Rd.1. Rr Rr Rd P. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow.Rr k.X.C←Rd(7) Rd(7)←C. b Rd. Load Indirect Load Indirect and Post-Inc.b) ← 1 I/O(P.N. X ← X + 1 X ← X . Rr -Z. Y Rd. K Rd.Instruction Set Summary (Continued) BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET Rd. Rr Z+. Load Indirect and Pre-Dec.1.b P. Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr.. Rd ← (X) Rd ← (Y) Rd ← (Y).Y. Z ← Z + 1 Z ← Z . Rd(0) ← 0 Rd(n) ← Rd(n+1). Store Indirect and Pre-Dec. b Rd.0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z. Rr Rd.Rd(n+1)← Rd(n). k X. Z Rd. Y+ Rd. Rr Y. X ← X + 1 X ← X . Z Rd. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Rd(7) ← 0 Rd(0)←C.V Z. Z+ k k Rd.N.b Rd Rd Rd Rd Rd Rd s s Rr.Y+q Rd.4). -Z Rd.N.0)←Rd(7.4)←Rd(3.C. (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr. Rr Y+q. Rr Z+q. Z+q Rd. (X) ← Rr (Y) ← Rr (Y) ← Rr.Rd(7.. Rr X+. Rr . n=0.Rd(n)← Rd(n+1).C.V Z. Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK I/O(P. . Rr Rd.6 Rd(3.1.N. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Y ← Y + 1 Y ← Y .Y Rd. Load Indirect and Pre-Dec.C.1.. Store Indirect Store Indirect and Post-Inc. P P. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc.V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T 1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DATA TRANSFER INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS Mnemonics Operands Description Operation Flags #Clocks 10 ATmega8(L) 2486OS–AVR–10/04 .C.. (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z).Rr Z.N.C←Rd(0) Rd(n) ← Rd(n+1).V Z.1. Rr Y+.C. Clear Twos Complement Overflow Set T in SREG if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X). Y ← Y + 1 Y ← Y . Rr . Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z)..b) ← 0 Rd(n+1) ← Rd(n). Rr Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Z+ Rd. Z ← Z+1 Z ← Z .X Rd. Store Indirect and Pre-Dec.1. .V Z. X+ Rd.

for WDR/timer) None None None 1 1 1 11 2486OS–AVR–10/04 .ATmega8(L) Instruction Set Summary (Continued) CLT SEH CLH Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG T←0 H←1 H←0 T H H 1 1 1 MCU CONTROL INSTRUCTIONS NOP SLEEP WDR No Operation Sleep Watchdog Reset (see specific descr. for Sleep function) (see specific descr.

Pb-free packaging alternative. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). 0.5 ATmega8-16AI ATmega8-16AU(2) ATmega8-16PI ATmega8-16PU(2) ATmega8-16MI ATmega8-16MU(2) Package(1) 32A 28P3 32M1-A 32A 32A 28P3 28P3 32M1-A 32M1-A 32A 28P3 32M1-A 32A 32A 28P3 28P3 32M1-A 32M1-A Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Notes: 1. This device can also be supplied in wafer form.5.0 mm) Plastic Quad Flat Package (TQFP) 28-lead.5. Plastic Dual Inline Package (PDIP) 32-pad.0 body.7 .5 .300” Wide. Package Type 32A 28P3 32M1-A 32-lead.5 ATmega8L-8AI ATmega8L-8AU(2) ATmega8L-8PI ATmega8L-8PU(2) ATmega8L-8MI ATmega8L-8MU(2) ATmega8-16AC ATmega8-16PC ATmega8-16MC 16 4. 5 x 5 x 1. 2. Lead Pitch 0. Thin (1.Ordering Information Speed (MHz) Power Supply Ordering Code ATmega8L-8AC ATmega8L-8PC ATmega8L-8MC 8 2. Also Halide free and fully Green.50 mm Micro Lead Frame Package (MLF) 12 ATmega8(L) 2486OS–AVR–10/04 .

25 7. Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV.00 7.30 0.25 7.80 TYP MAX 1.20 0.ATmega8(L) Packaging Information 32A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0. Lead coplanarity is 0. B R 13 2486OS–AVR–10/04 .45 NOM – – 1.05 0.45 0.10 mm maximum. Allowable protrusion is 0.15 1.00 – – – 0.90 0. 0.75 6.00 9. 3.10 9.20 0. Dimensions D1 and E1 do not include mold protrusion.00 7. 32-lead.90 8.05 9.95 8.8 mm Lead Pitch. 1. This package conforms to JEDEC reference MS-026.0 mm Body Thickness. 2. 7 x 7 mm Body Size.75 6.00 9. Variation ABA.25 mm per side.10 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.09 0. CA 95131 TITLE 32A. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose.

5724 – 34.620 7.160 Note 1 Note 1 NOTE Note: 1.112 0.175 0. Mold Flash or Protrusion shall not exceed 0. 28-lead (0.798 8.493 0.762 3. B R 14 ATmega8(L) 2486OS–AVR–10/04 .508 34. 28P3 REV.143 0.010").544 7.356 10.25 mm (0.300"/7.28P3 D PIN 1 E1 A SEATING PLANE L B1 e E B B2 A1 (4 PLACES) C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.143 3.255 7.540 TYP 09/28/01 2325 Orchard Parkway San Jose.429 0. B1 B2 L C eB e 2. CA 95131 TITLE 28P3.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO.381 1.397 1.533 1. Dimensions D and E1 do not include mold Flash or Protrusion.203 – NOM – – – – – – – – – – – MAX 4.

02 0.05 1. Lead Pitch 0. Fig.30 – – 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.10 5.ATmega8(L) 32M1-A D D1 1 2 3 0 Pin 1 ID E1 E SIDE VIEW TOP VIEW A2 A3 A1 K P D2 A 0. 3. 5 x 5 x 1.00 NOTE SYMBOL A P Pin #1 Notch (0.60 12o – 3.50 BSC 0.00 BSC 4.65 0.20 – 0. Micro Lead Frame Package (MLF) DRAWING NO.00 0.75BSC 2. 2 (Anvil Singulation). VHHD-2.23 5.18 0.10 0.40 – – 0.50 0.25 0. D R 15 2486OS–AVR–10/04 .50 mm.80 – – NOM 0.75 BSC 2.00 BSC 4.25 3. 32M1-A REV.95 3.95 3.10 mm Exposed Pad.30 MAX 1.20 REF 0.20 R) 1 2 3 A1 A2 A3 E2 b K D D1 D2 E b e L E1 E2 e L P BOTTOM VIEW 0 Note: JEDEC Standard MO-220.90 0. K 8/19/04 2325 Orchard Parkway San Jose. 32-pad. CA 95131 TITLE 32M1-A.0 mm Body.

D. For ATmega8 Rev. Customers who want compatibility between Rev. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 When the internal RC Oscillator is used as the main clock source.Erratas ATmega8 Rev. E. safe operation of the Oscillator is not guaranteed. This will be fixed in ATmega8 Rev. F.36 pF on XTAL1/TOSC1 and XTAL2/TOSC2. must ensure that CKOPT is unprogrammed (CKOPT = 1). and G The revision letter in this section refers to the revision of the ATmega8 device. it is possible to run the Timer/Counter2 asynchronously by connecting a 32 KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. But when the internal RC Oscillator is selected as the main clock source. Problem fix/Workaround Use external capacitors in the range of 20 . G. 16 ATmega8(L) 2486OS–AVR–10/04 . • CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32 KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 1. As long as there are no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2. G and older revisions. the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2.

6. Updated “Calibrated Internal RC Oscillator” on page 28. Removed to instances of “analog ground”. Removed reference to “External RC Oscillator application note” from “External RC Oscillator” on page 27. 1. 3. Added note to MLF package in “Pin Configurations” on page 2. 2. Document updated to reflect this. 2486L-10/03 1. Updated Watchdog Timer code examples in “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 43. 2486K-08/03 to Rev. 5. Table 15 on page 36. Updated “Calibrated Internal RC Oscillator” on page 28 with the 1 MHz default value. 5. Updated tRST in Table 15 on page 36. 17 2486OS–AVR–10/04 . 2486M-12/03 Changes from Rev. 2486M-12/03 to Rev. Table 89 on page 222 and Table 90 on page 222 moved to new section “Page Size” on page 222. 6. 3. Table 100 on page 241 and Table 102 on page 243. Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page 30. and Table 100 on page 241. Updated “Internal Voltage Reference Characteristics” on page 40. Updated “DC Characteristics” on page 239. Updated “Ordering Information” on page 12. Removed instructions CALL and JMP from the datasheet. Replaced by “ground”. 2. 2. 1. Updated features in “Analog-to-Digital Converter” on page 193. Updated Table 7 on page 27. Renamed ICP to ICP1 in the datasheet. 4. ADC4 and ADC5 support 10-bit accuracy. VBG in Table 16 on page 40. 2486N-09/04 to Rev. 4. Changes from Rev. Removed “Preliminary” and TBDs from the datasheet. Updated “ADC Characteristics” on page 245. Updated descripton for bit 4 in “Store Program Memory Control Register – SPMCR” on page 210. 2486N-09/04 1. 2486L-10/03 to Rev. 3. 4.ATmega8(L) Datasheet Revision History Changes from Rev. 5. 2486O-10/04 Please note that the referring page numbers in this section are referred to this document. Changes from Rev. The referring revision in this section are referring to the document revision. Replaced text “XTAL1 and XTAL2 should be left unconnected (NC)” after Table 9 in “Calibrated Internal RC Oscillator” on page 28.

which do not exist. Added note under “Filling the Temporary Buffer (Page Loading)” on page 213 about writing to the EEPROM during an SPM Page load. 2486J-02/03 1. Updated item 4 in the “Serial Programming Algorithm” on page 235. Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B (PB7. Changes from Rev. Updated “ADC Characteristics” on page 245. 9.7. 7. 11. 8. from “Special Function IO Register – SFIOR” on page 56. Updated “Erratas” on page 16. Improved the table under “SPI Timing Characteristics” on page 243 and removed the table under “SPI Serial Programming Characteristics” on page 238. Removed ADHSM completely. Updated “ATmega8 Typical Characteristics” on page 246. Changes from Rev.PB0) XTAL1/XTAL2/TOSC1/TOSC2” on page 5. 9. Removed bit 4. 8. Added note 2 to Figure 103 on page 212. ADHSM. Added section “EEPROM Write during Power-down Sleep Mode” on page 21. 2. 12. in Table 98 on page 237. Corrected PC6 in “Alternate Functions of Port C” on page 59. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz Crystal Oscillator” application note. 10. 4.. 2486J-02/03 to Rev. Corrected PB6 and PB7 in “Alternate Functions of Port B” on page 56. Byte 3. 5. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page 239. Corrected OCn waveforms in Figure 38 on page 88. 3. 2. Updated VBOT values in Table 15 on page 36. Various minor TWI corrections. 2486I-12/02 to Rev. 3. 2486K-08/03 1. 11. 4. 10. 18 ATmega8(L) 2486OS–AVR–10/04 . 6. Various minor Timer 1 corrections. Added tWD_FUSE to Table 97 on page 236 and updated Read Calibration Byte. Improved the description of “Asynchronous Timer Clock – clkASY” on page 24.

” on page 155. 2486F-07/02 to Rev. 2486G-09/02 to Rev. “UCPOL Bit Settings. Changes from Rev. 2486H-09/02 to Rev. and F on page 16. “CPOL and CPHA Functionality. 6 Corrected Errors in Cross References.” on page 218. 1 2 3 Changes in “Digital Input Enable and Sleep Modes” on page 53. 18. Bit 3” on page 57. “Analog Comparator Multiplexed Input(1).” on page 245. Table 72. 2486E-06/02 to Rev.” on page 192. “Reset Characteristics. “Explanation of Different Variables used in Figure 103 and the Mapping to the Z-pointer. DC Characteristics on page 239.Updated drawings in “Packaging Information” on page 13. Added period changing data in Table 99. Added thick lines around accessible registers in Figure 76 on page 166. 2486D-03/02 to Rev.” on page 197.Added errata for Rev D. 2486E-06/02 1 Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated: Table 15. 2 Changes in External Clock Frequency Added the description at the end of “External Clock” on page 30.” on page 203. 15. 19 2486OS–AVR–10/04 . Table 59. 1. and Table 84.4 kbps under “Examples of Baud Rate Setting” on page 156. 2486F-07/02 1. 2486H-09/02 Changes from Rev.4 Mbps to 230. Addition of OCS2 in “MOSI/OC2 – Port B. The following tables has been updated: Table 51.000 Write/Erase Cycles. 5 Changes in “Reading the Calibration Byte” on page 231. “External Clock Drive. Table 73. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page 213. E. “ADC Characteristics. 14.” on page 245. “Input Channel Selections.” on page 241.” on page 36.Changed the Endurance on the Flash to 10. Added note for RSTDISBL Fuse in Table 87 on page 220. “ADC Characteristics. Corrected 230. 2486G-09/02 Changes from Rev. 2486I-12/02 Changes from Rev. 17. “Internal Voltage Reference Characteristics. “ADC Conversion Time. Table 75. Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page 111. 1 Updated Table 103.” on page 40. Changes from Rev.ATmega8(L) 13. Table .” on page 129. Table 16. 16.

“TA = -40×C to 85×C. 20 ATmega8(L) 2486OS–AVR–10/04 . Table 15 on page 36. Table 8.3 Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65. Table 16 on page 40. Changes from Rev. This is now added in the following sections: Improved description of “Oscillator Calibration Register – OSCCAL” on page 29 and “Calibration Byte” on page 222. Removed some of the TBD’s in the following tables and pages: Table 3 on page 24. “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection. and 8 MHz Oscillator selections. Table 17 on page 42. 2486C-03/02 to Rev. 2486C-03/02 1 Updated TWI Chapter. 3 Added Some Preliminary Test Limits and Characterization Data. “TWI Bit Rate Prescaler. Added a note in section “Enter Programming Mode” on page 225. Added the note at the end of the “Bit Rate Generator Unit” on page 167.” on page 26. More details regarding use of the TWI Power-down operation and using the TWI as Master with low TWBRR values are added into the datasheet.5V (unless otherwise noted)” on page 239. Figure 104 on page 223 and Figure 112 on page 234 are updated to also reflect that AVCC must be connected during Programming mode. 2486D-03/02 1 Updated Typical Start-up Times. “Start-up Times for the External Clock Selection. 2 Updated Description of OSCCAL Calibration Byte. Table 6.” on page 26. 4. The following tables has been updated: Table 5.” on page 27. Changes from Rev.” on page 30. “Start-up Times for the External RC Oscillator Clock Selection. and Table 102 on page 243. Added the description at the end of “Address Match Unit” on page 167. VCC = 2.” on page 170.7V to 5. 2 Added “ATmega8 Typical Characteristics” on page 246. Table 99 on page 241. 2486B-12/01 to Rev. In the datasheet. 5 Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected. it was not explained how to take advantage of the calibration bytes for 2. and Table 12. “Start-up Times for the Crystal Oscillator Clock Selection. 4 Updated Programming Figures.

USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose. Atmel does not make any commitment to update the information contained herein. Other terms and product names may be trademarks of others. Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www. SPECIAL OR INCIDENTAL DAMAGES (INCLUDING. PUNITIVE. Printed on recycled paper. CA 95131. Blvd. OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT. USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn. to any intellectual property right is granted by this document or in connection with the sale of Atmel products.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 2486OS–AVR–10/04 . CO 80906. USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3. DAMAGES FOR LOSS OF PROFITS. USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR. CA 95131. EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. and Everywhere You Are ™ are the trademarks of Atmel Corporation or its subsidiaries. ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS. INDIRECT. by estoppel or otherwise. © Atmel Corporation 2004. Colorado Springs. CA 95131. express or implied. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. No license. BUSINESS INTERRUPTION. FITNESS FOR A PARTICULAR PURPOSE. France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex. 1-24-8 Shinkawa Chuo-ku. THE IMPLIED WARRANTY OF MERCHANTABILITY. AVR ®. CONSEQUENTIAL. Colorado Springs. France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Atmel’s products are not intended. Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F.atmel. All rights reserved. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT. authorized. USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose. IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING. Tonetsu Shinkawa Bldg. Blvd. Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. OR NON-INFRINGEMENT. BUT NOT LIMITED TO. Atmel ®. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE. WITHOUT LIMITATION. France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex. CO 80906. or warranted for use as components in applications intended to support or sustain life. logo and combinations thereof. and AVR Studio ® are registered trademarks.Atmel Corporation 2325 Orchard Parkway San Jose.