Today: The TMS320F28335 Microcontroller. Code Composer Studio v4. C As Implemented For The F28355

Today: The TMS320F28335 microcontroller.
Code Composer Studio v4.

C as implemented for the F28355.
Handouts: Printed copy of today’s lecture slides.
References: TBD
Last one out should close the lab door!!!!

Please keep the lab clean and organized.
The modern computer hovers between the obsolescent and the nonexistent.
— Sydney Brenner, attributed in Science, 5 January 1990.
CampCAEN Wireless – Summer 2010 Page 1/71 Tuesday – June 29, 2010
TMS320F28335 Experimenter Kit
Wirewrap pins and connectors added for CampCAEN summer 2010.
Two components
Docking board.
◮ Supports various processor control cards.
◮ Connects to PC via USB cable.
◮ Powered via the USB cable.
◮ Hole pattern to be used for user circuits.
◮ We’ve added wire wrap pins and sockets to allow access to signals
and to support future additions.
F28335 control stick.

◮ Holds a 150 MHz F28335, a crystal oscillator and interface logic.
◮ Provides user access to most of the general purpose I/O (GPIO) pins.
◮ Contains three LEDs. One to show power status and two user
controllable.
◮ Control cards are available for several other F28xxx family
members.
Why the F28335?
◮ Fast, 150 MHz clock/instruction cycle.

◮ High speed A/D converter, 12.5 MHz max sample rate, 16 channels,
12-bits.
◮ A/D includes two parallel sample and hold circuits. This makes it
ideal for use in IQ signal processing.
◮ Floating point.
◮ Nominally a 32-bit machine.
◮ 34 K words (16-bit) of on-chip static random access memory (RAM).
◮ 256 K words (16-bit) of flash read only memory (ROM).
◮ 6 high resolution (150 picosecond) pulse width modulators. Can
readily be used to implement D/A converters.
◮ Possesses a rich set of peripheral interface devices.
◮ Low cost, $99 list. Less with a university discount.
Documentation on USB drives
◮ I’ve put my collection of TI documents relative to to F28335 on the

class USB drives.
◮ Collection in the folder named experimenter_kit.
◮ Files were downloaded from the TI web site.
◮ Links to the file can be found in the index.html file. Click on it to
access using browser.
◮ Complex devices map to lots of documentation.
◮ I’ve incorrectly used the Piccolo name.
The index list
Poking around
Let’s look at the F28335 data manual.
◮ First entry, TMS320F28335, TMS320F28334, ..., Digital Signal

Controllers ...
◮ Name of the actual file is tms320f28335.pdf.
◮ Contains 199 pages.
Let’s look at the F28335 CPU manual.
◮ TMS320C28x CPU and Instruction Set Reference Guide.

◮ Name of the actual file is spru430e.pdf.
◮ Contains 693 pages.
F28335 Peripherals
◮ 6 high resolution pulse width modulator outputs

◮ 3 32-bit timers
◮ Serial port peripherals
◮ 2 CAN
◮ 3 SCI (UART)
◮ 2 McBSP (configurable as SPI)
◮ 1 SPI
◮ 1 I2C bus
◮ 12-bit, 16-channel A/D converter
◮ 80-ns conversion rate (12.5 MHz)
◮ 2×8 channel multiplexer
◮ 2 sample and holds
◮ 88 configurable general purpose I/O (GPIO) pins
F28335 block diagram
M0 SARAM 1Kx16 L0 SARAM 4K x 16 OTP 1K x 16
(0-Wait) (0-Wait, Dual Map)
M1 SARAM 1Kx16 L1 SARAM 4K x 16
Flash
L2 SARAM 4K x 16 256K x 16
(0-Wait, Dual Map) Code 8 Sectors
Security
Memory Bus
L3 SARAM 4K x 16 Module
(0-Wait, Dual Map)
L4 SARAM 4K x 16 TEST2
(0-W Data, 1-W Prog) Pump
TEST1
L5 SARAM 4K x 16 PSWD
Boot ROM (0-W Data, 1-W Prog) Flash
8K x 16 Wrapper
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
Memory Bus
XD31:0
FPU
TCK
XHOLDA
TDI
XHOLD
TMS
XREADY
32-bit CPU
TDO
88 GPIOs GPIO XR/W (150 MHZ @ 1.9 V)
XINTF
MUX (100 MHz @ 1.8 V) TRST
XZCS0
EMU0
XZCS7
EMU1
XZCS6
Memory Bus
XWE0
DMA Bus
XCLKIN
XA0/XWE1 CPU Timer 0
OSC, X1
DMA PLL,
XA19:1 CPU Timer 1
6 Ch LPM, X2
WD
CPU Timer 2 XRS
XCLKOUT
XRD PIE
(Interrupts)
88 GPIOs 8 External Interrupts

GPIO
MUX
A7:0 XINTF
Memory Bus
12-Bit
B7:0
ADC
2-S/H DMA Bus
REFIN
16-bit peripheral bus 32-bit peripheral bus 32-bit peripheral bus

(DMA accessible)
FIFO FIFO FIFO

(16 Levels) (16 Levels) (16 Levels) ePWM-1/../6
CAN-A/B
McBSP-A/B eCAP-1/../6 eQEP-1/2 (32-mbox)
SCI-A/B/C SPI-A I2C HRPWM-1/../6
SPISIMOx
SPISOMIx
EPWMxA
EPWMxB
SCIRXDx
SCITXDx
SPICLKx
ESYNCO
MCLKRx
SPISTEx
MCLKXx
CANRXx
EQEPxA
EQEPxB
EQEPxS
CANTXx
ESYNCI
EQEPxI
MFSRx
MFSXx
ECAPx
MDXx
MRXx
SDAx
SCLx
TZx
GPIO MUX
88 GPIOs
Secure zone
From TMS320F28335 data manual.
Processor and devices
Memory Bus
XD31:0
FPU
TCK
XHOLDA
TDI
XHOLD
TMS
XREADY
32-bit CPU
TDO
88 GPIOs GPIO XR/W (150 MHZ @ 1.9 V)
XINTF
MUX (100 MHz @ 1.8 V) TRST
XZCS0
EMU0
XZCS7
EMU1
XZCS6
Memory Bus
XWE0
DMA Bus
XCLKIN
XA0/XWE1 CPU Timer 0
OSC, X1
DMA PLL,
XA19:1 CPU Timer 1
6 Ch LPM, X2
WD
CPU Timer 2 XRS
XCLKOUT
XRD PIE
(Interrupts)
88 GPIOs 8 External Interrupts

GPIO
MUX
A7:0 XINTF
Memory Bus
12-Bit
B7:0
ADC
2-S/H DMA Bus
REFIN
16-bit peripheral bus 32-bit peripheral bus 32-bit peripheral bus

(DMA accessible)
FIFO FIFO FIFO

(16 Levels) (16 Levels) (16 Levels) ePWM-1/../6
CAN-A/B
McBSP-A/B eCAP-1/../6 eQEP-1/2 (32-mbox)
SCI-A/B/C SPI-A I2C HRPWM-1/../6
SPISIMOx
SPISOMIx
EPWMxA
EPWMxB
SCIRXDx
SCITXDx
SPICLKx
ESYNCO
MCLKRx
SPISTEx
MCLKXx
CANRXx
EQEPxA
EQEPxB
EQEPxS
CANTXx
ESYNCI
EQEPxI
MFSRx
MFSXx
ECAPx
MDXx
MRXx
SDAx
SCLx
TZx
GPIO MUX
88 GPIOs
Secure zone
Comments
◮ Obligatory slide.
◮ Gives an, albeit complex, overview of the device.
◮ Illustrates the structure of the device. How the processor, memory
and peripherals are interconnected.
Memory overview
M0 SARAM 1Kx16 L0 SARAM 4K x 16 OTP 1K x 16

M1 SARAM 1Kx16 L1 SARAM 4K x 16
Flash
L2 SARAM 4K x 16 256K x 16
(0-Wait, Dual Map) Code 8 Sectors
Memory Bus Security
L3 SARAM 4K x 16 Module
(0-Wait, Dual Map)
L4 SARAM 4K x 16 TEST2
(0-W Data, 1-W Prog) Pump
TEST1
L5 SARAM 4K x 16 PSWD
Boot ROM (0-W Data, 1-W Prog) Flash
8K x 16 Wrapper
L6 SARAM 4K x 16
L7 SARAM 4K x 16
Memory Bus
F28335 memory layout
Block
On-Chip Memory External Memory XINTF
Start Address
Data Space Prog Space Data Space Prog Space
0x00 0000
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040 M0 SARAM (1K x 16)

0x00 0400 M1 SARAM (1K x 16)
0x00 0800 Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if Reserved
VMAP = 1,
ENPIE = 1)
0x00 0E00
(24x/240x Equivalent Data Space)

Peripheral Frame 0
0x00 2000
0x00 4000
Reserved XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA-Accessible
0x00 5000 0x00 5000
Low 64K
Peripheral Frame 3
(Protected) DMA-Accessible
0x00 6000
Peripheral Frame 1
(Protected) Reserved
0x00 7000
Peripheral Frame 2
(Protected)
0x00 8000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
0x00 9000 L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
Reserved
0x00 A000
0x00 B000
0x00 C000
L4 SARAM (4K x 16, DMA-Accessible)
0x00 D000
0x00 E000
0x00 F000
0x01 0000
0x10 0000
Reserved XINTF Zone 6 (1M x 16, XZCS6) (DMA-Accessible)
0x20 0000
XINTF Zone 7 (1M x 16, XZCS7) (DMA-Accessible)
0x30 0000
0x30 0000 FLASH (256K x 16, Secure Zone)
0x33 FFF8
128-bit Password
0x34 0000 Reserved
0x38 0080
ADC Calibration Data
0x38 0090
Reserved
0x38 0400
User OTP (1K x 16, Secure Zone)
0x38 0800
Reserved
0x3F 8000
(24x/240x Equivalent
0x3F 9000
Program Space)
Reserved
0x3F A000
High 64K

0x3F B000
0x3F C000
Reserved
0x3F E000
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector- should be enabled at a time.

Why is the memory so complicated?
◮ Another obligatory slide.

◮ Addressed as 16-bit words. Can access 32-bit values using even
addresses.
◮ Memory is divided into sections in order to allow simultaneous
read/write accesses to sections.
◮ Multiple memory accesses are of importance to programmers who
are trying to maximize performance.
◮ We are at the novice level. We will be more interested in getting a
program to work much more that in squeezing out performance.
However, we do have to deal with what exists.
How does it do that?
Operations involved in executing an instruction:

◮ Fetch instruction from memory.
◮ Decode instruction.
◮ Read values from memory or from CPU register(s).
◮ Execute instruction.
◮ Write result into memory or CPU register(s).
From spru430e.pdf
The F28335 can (in effect) accomplish this every clock cycle. How?
By using an instruction pipeline.
Executes in separate phases
Divides execution into eight phases:

◮ Fetch 1 (F1), drive address onto program memory lines.
◮ Fetch 2 (F2), read instruction into fetch queue.
◮ Decode 1 (D1), identifies instruction size, sets up for next
instruction, checks for valid instruction.
◮ Decode 1 (D2), if data is to be read or written, generates address;
does any needed modification to stack pointer or aux register
contents; if branch (of some sort), take it.
◮ Read 1 (R1), if read instruction drive the memory address lines.
◮ Read 2 (R2), fetch data value from memory.
◮ Execute (E), do arithmetic, logic operation.
◮ Write (W), write result (if needed).
Simplified pipeline activity
Example 4−3. Simplified Diagram of Pipeline Activity
F1 F2 D1 D2 R1 R2 E W Cycle
I1 1
I2 I1 2
I3 I2 I1 3
I4 I3 I2 I1 4
I5 I4 I3 I2 I1 5
I6 I5 I4 I3 I2 I1 6
I7 I6 I5 I4 I3 I2 I1 7
I8 I7 I6 I5 I4 I3 I2 I1 8
I8 I7 I6 I5 I4 I3 I2 9
I8 I7 I6 I5 I4 I3 10
I8 I7 I6 I5 I4 11
I8 I7 I6 I5 12
I8 I7 I6 13
I8 I7 14
I8 15
Do I need to get involved?
◮ Not really. Unless performance has become an issue.

◮ Transfers of control either by branches or interrupts slow down the
pipeline.
◮ It is VERY hard to predict precise timings of a segment of code.
◮ TI has put in a lot effort to make getting performance available with
little or no effort on the user’s part.
Composer Studio v4
◮ Used across all of TI’s microcomputer/controller lines.

◮ Highly flexible and configurable.
◮ Major change going from V3 to V4. V4 is about one year old.
◮ We will limit our focus to just what is needed to create and run
simple programs.
◮ Based on the open source Eclipse GUI.
◮ Generates scillions of xml files.
◮ Uses Java.
◮ Works in terms of a workspace.
◮ Only recognizes workspace structures that it creates.
C/C++ screen
Comments
◮ Left panel shows the (current) workspace directory structure.

◮ Make sure the project that you are working on is Active.
◮ Only projects and directories made by CCS will be visible!
◮ Top right panel is the editor window.
◮ Leading asterisk in file name tab indicates text has been
modified and not yet saved.
◮ Bottom center is the console (stdout) window. Also used by the code
generation tools to display information about the progress of the
program generation process.
◮ Bottom right summarizes error and warning statements. Can click
on errors to make the editor go to specific statements that are in
error.
Debug screen
Comments
◮ CCS is reasonably reliable. Can crash on occasion.

◮ Probably should use the default configuration, at least initially.
◮ We will be working with our workspace contained on a USB drive.
◮ The USB drives are numbered. Leave them behind at the end of the
day so that we can update for tomorrow. Remember the drive
number so you can use the same unit tomorrow.
◮ Today’s workspace is workspace_a.
◮ File, Switch Workspace, browse to USB drive (My Computer,
Removable Disk), workspace_a.
After clicking the bug icon
Comments
◮ Clicking the bug button in the C/C++ mode might not switch to the
debug mode. You can do so manually.
◮ Program execution will actually start at c_int00 and proceed to
main where it will wait.
◮ To start execution click on the green triangle at the top of the debug
panel.
Key concepts
◮ Multiple work spaces can be used to organize projects. For example,

use a different work space per processor types.
◮ active project
◮ active configuration
◮ use of .cmd file to describe memory
◮ bug icon use
Creating a C project
◮ C/C++ mode.
◮ File.
◮ New, CCS Project
◮ Enter the name of the project.
◮ Next. Take the default for the type of project.
◮ Next. No additional project settings are needed.
◮ Next. Make sure the Device Variant is TMS320F28335. Otherwise
don’t make any other changes.
◮ Finish.
Choosing a target configuration
◮ C/C++ mode.
◮ File.
◮ New, Target Configuration File.
◮ I typically specify the name to be the same as the project name.
◮ Finish.
◮ Connection. Texas Instruments XDS100v 1 USB Emulator.
◮ Device. Check the Experimenter’s Kit – Delfino F28335 box.
◮ Save.
◮ Can now clear the configuration window. Click the trailing × in the
tab.
Configuration selection screen
Hello World Exercise
Introduces Code Composer Studio and gives practice in using it to create

and execute programs.
◮ Will do variations on the Hello World theme.

◮ Traditional.
◮ Adding some additional output.
◮ Increasing the output to discover the presence of a watch dog
timer.
◮ Disabling the watch dog timer.
Create your own Hello World
◮ Run Code Composer Studio. Take the default workspace.

◮ Create a hello_world project.
◮ Create a hello_world device configuration file.
◮ Copy a .cmd file from ???.
◮ Create a new source file named hello_world.
◮ Enter the text contained on the next slide into the text editor.
◮ Click the bug icon.
◮ Go to the Debug mode.
◮ Make sure the program has been successfully compiled and loaded.
◮ Click the bug icon.
◮ The program output should be displayed in the console panel.
Some times things get out of sync
◮ Connecting to the target can take a while, be patient.

◮ Make sure that the active project is what you think it is.
◮ Debug mode, Project, Clean.
◮ C/C++ mode, Project, Rebuild Active Project
◮ Avoid Build All!
Basic Hello World code
#include <stdio.h>
void main(void)
{
printf("Hello World!\n");
}
Looping Hello World
Modify your hello world code to be as shown below, compile and run.
#include <stdio.h>
#define N 5
void main(void)
{
int counter;
for(counter = 0; counter < N; counter++) {

printf("%5d hello world!\n", counter);
}
}
Comments
◮ Use of the #define statement to parameterize the code.

◮ Use of capital letters (all) for defined constants to make it clear that
they are not variables.
Increasing the loop size
Define N equal to 20, rebuild and run.
The program stops running properly at about 7 iterations.
Why?
The watchdog timer
◮ Purpose is to provide a means of recovery if/when something goes

wrong in a program.
◮ Unless reset periodically with cause a non-maskable interrupt after
512 carrier cycles. For a 150 MHz clock this approximately 3.4
microseconds.
◮ Program needs to reset the counter on a continuing basis to prevent
this.
◮ The F28335 default is to start up with the watch dog counter
running and the interrupt support enabled.
◮ Can be disabled.
Leashing the watchdog
Add the three lines of code below the declaration of counter,
rebuild and run. All should be well.
#include <stdio.h>
#define N 20
void main(void)
{
int counter;
asm(" eallow");
*(volatile int *)0x007029 = 0x0068;
asm(" edis");

}
}
What have we done?
◮ The watch dog register is protected. Normal writes to it will not

change it’s contents.
◮ This is to prevent accidental changes.
◮ Need to turn protection off. Then change. Then turn the protection
back on.
◮ There are several registers so protected. There is a list.
◮ In today’s world, it is considered bad practice to write code
addresses so explicitly.
Doing more
#include <stdio.h>
#define N 20
#define EALLOW asm(" eallow")
#define EDIS asm(" edis")
#define WDCR *(volatile int *)0x007029
void main(void)
{
int counter;
EALLOW;
WDCR = 0x0068;
EDIS;

}
}
Comments
◮ The WDCR definition allows the watchdog control register to be

accessed as if it were a normal C variable. It allows both reading and
writing of the register.
◮ Defines can be used to allow easy to remember definitions for other
processor registers.
◮ The importance of the use of the volatile keyword will be taken
up later.
◮ Such register definitions can be collected together in an include file.
We might name this file something like RegDefines.h.
End of the Hello World exercise
Conventions
◮ The goal is to develop procedures and habits that it make it difficult

to make mistakes or, at least, to make them easy to spot.
◮ Positioning of { and } and the location of code relative to braces.
◮ Indenting and tabs.
◮ The creative use of white space.
◮ Use of capitals.
◮ Naming conventions.
◮ Defining one’s own data types.
◮ Accepted standards...employer probably will have style guide.
◮ Unfortunately, I’m highly inconsistent. Do as I say, not necessarily
as I do.
Blinking an LED Exercise
◮ A traditional “first” program for a programmer becoming familiar

with a new embedded processor.
◮ If a microcomputer board doesn’t have an LED one often can be
added externally. The F28355 control stick has two that we can use.
Thinking things through
◮ We need to know how the LEDs connect to the F28335. A good place
to determine this is by checking the board documentation provided
by TI. TI provides excellent documentation with all of their
products.
◮ We next need to learn how to control the signals used to turn the
LEDs on and/or off.
◮ Finally we should write a small program to verify that we correctly
understand what we are doing.
F28335 control card schematic
Zooming to the LEDs
◮ Controlled by GPIO (general purpose input output) lines 31 and 34.

◮ Line high means LED is off. Line low means LED is on.
Investigating the GPIO lines
◮ Documented in sprufb0d.pdf, TMS320x2833x, 2823x System

Control and Interrupts Reference Guide, Chapter 6. The overall
document contains 141 pages.
◮ 87 GPIO pins are supported.
◮ Pins can be used as digital I/O (direction settable) or connected to
one of up to three peripherals.
Relevant GPIO control/configuration registers
Table 39. GPIO Control Registers

(1)
Name Address Size (x16) Register Description Bit Description
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0-GPIO31) Figure 53
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0-GPIO15) Figure 55
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16-GPIO31) Figure 56
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0-GPIO15) Figure 47
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16-GPIO31) Figure 48
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0-GPIO31) Figure 59
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0-GPIO31) Figure 62
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32-GPIO63) Figure 54
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32-GPIO47) Figure 57
GPBQSEL2 0x6F94 2 GPIO B Qualifier Select 2 Register (GPIO48 - GPIO63) Figure 58
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32-GPIO47) Figure 49
GPBMUX2 0x6F98 2 GPIO B MUX 2 Register (GPIO48-GPIO63) Figure 50
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32-GPIO63) Figure 60
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32-GPIO63) Figure 63
GPCMUX1 0x6FA6 2 GPIO C MUX 1 Register (GPIO64-GPIO79) Figure 51
GPCMUX2 0x6FA8 2 GPIO C MUX 2 Register (GPIO80-GPIO87) Figure 52
GPCDIR 0x6FAA 2 GPIO C Direction Register (GPIO64-GPIO87) Figure 61
GPCPUD 0x6FAC 2 GPIO C Pull Up Disable Register (GPIO64-GPIO87) Figure 64
(1)
The registers in this table are EALLOW protected. See Section 7.2 for more information.
From sprufb0d.pdf.
What do we see?
◮ The GPIO registers are grouped into three groups, A, B and C.

◮ Group A consists of GPIO pins 0-31. Group consists of GPIO pins
32-63. Group C consists of GPIO pins 64-87.
◮ One LED is in Group A and the other is in Group B. We will
concentrate on the Group A LED (GPIO31).
◮ Each pin in Group A is configured/controlled by five 32 bit registers.
◮ The table lists the register addresses.
Controlling a Group A or B GPIO setting
Name Address Size (x16) Register Description

GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0-GPIO31)
GPASET 0x6FC2 2 GPIO A Set Register (GPIO0-GPIO31)
GPACLEAR 0x6FC4 2 GPIO A Clear Register (GPIO0-GPIO31)
GPATOGGLE 0x6FC6 2 GPIO A Toggle Register (GPIO0-GPIO31)
GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32-GPIO63)
GPBSET 0x6FCA 2 GPIO B Set Register (GPIO32-GPIO63)
GPBCLEAR 0x6FCC 2 GPIO B Clear Register (GPIO32-GPIO63)
GPBTOGGLE 0x6FCE 2 GPIO B Toggle Register (GPIO32-GPIO63)
From sprufb0d.pdf.
Defines that we might want create
#define GPACTRL *(volatile unsigned long *)0x6F80

#define GPAQSEL2 *(volatile unsigned long *)0x6F84
#define GPAMUX2 *(volatile unsigned long *)0x6F88
#define GPADIR *(volatile unsigned long *)0x6F8A
#define GPAPUD *(volatile unsigned long *)0x6F8C
#define GPADAT *(volatile unsigned long *)0x6FC0
#define GPASET *(volatile unsigned long *)0x6FC2
#define GPACLEAR *(volatile unsigned long *)0x6FC4
#define GPATOGGLE *(volatile unsigned long *)0x6FC6
Next, what bits to set/clear?
◮ Pins default to I/O. Need to only set direction.

◮ Internal pullup resistors are enabled by default. Makes sense to
disable for this application.
◮ It probably makes the most sense to simply toggle the GPIO pin
connected to the LED.
There are two mux registers.
◮ Each GPIO pin has several possible functions.

◮ The mux register selects which is to be used.
◮ Two bits are used per GPIO pin.
For example for GIPO pin 2 in group A (or GPIO pin 34 in group B) the
associated MUX1 register bits would be bits
bits: . . . 7 6 5 4 3 2 1 0
GPIO: . . . 03/35 02/34 01/33 00/32
Setting these bits to zero (actually the default setting) results in direct
digital I/O.
Getting down to code
Bits are named increasing from right to left:
31, 30, 29, 28, . . . , 5, 4, 3, 2, 1, 0.
To initialize:
GPAMUX2 = GPAMUX2 & 0x3FFFFFFF; // GPIO31 as IO use

GPADIR = (GPADIR & 0x7FFFFFFF)|0x80000000; // set direction to out
GPAPUD = (GPAPUD & 0x7FFFFFFF)|0x80000000; // disable the pull up
To toggle:
GPATOGGLE = 0x80000000;
Final product
/* File name: BlinkLED.c
*
* 24Jun2010 .. initial version .. km
*
*/
#define EALLOW asm(" eallow")

#define EDIS asm(" edis")
#define WDCR *(volatile int *)0x007029
#define GPAMUX2 *(volatile unsigned long *)0x6F88
#define GPADIR *(volatile unsigned long *)0x6F8A
#define GPAPUD *(volatile unsigned long *)0x6F8C
#define GPATOGGLE *(volatile unsigned long *)0x6FC6
#define FOREVER 1
void main()
{
unsigned long counter=0L;
EALLOW; // disable the watch dog

WDCR = 0x0068;
EDIS;
EALLOW; // configure GPIO pin 31

GPAMUX2 = GPAMUX2&0x3FFFFFFFF; // GPIO31 as IO use
GPADIR = (GPADIR & 0x7FFFFFFF)|0x80000000; // set direction to out
GPAPUD = (GPAPUD & 0x7FFFFFFF)|0x80000000; // disable the pull up
EDIS;
while(FOREVER) {
while (counter++ <200000); //200 thousand
counter = 0L;
EALLOW;
GPATOGGLE = 0x80000000;
EDIS;
}
}
Frosting on the cake
◮ Can we extrapolate the above code to also blink the second LED?
◮ The second LED is driven GPIO line 34 which is in group B.
◮ Using the toggle get the second LED to blink.
◮ Once blinking can we arrange our code so that B is on when is off
and vice versa? Perhaps by directly setting and clearing rather than
toggling.
◮ Give it a go.
Hints:
◮ Use GPBMUX1 (0x6F96), GPBDIR (0x6F9A), GPBPUD (0x6F9C),
◮ Group B least significant bit(s) correspond to GPIO pin 32.
End of the Blinking LED exercise
No one said that things would be easy.
A useful function
// This function disables the watchdog timer.
void DisableDog(void)
{
asm(" EALLOW");
*(unsigned int *)0x007029 = 0x0068; // WDCR
asm(" EDIS");
}
The basic processor
◮ 150 MHz clock, 6.67 ns instruction cycle.

◮ floating point unit
◮ 34K single-access RAM (16-bit 0-wait)
◮ M0 and M1 1K×16.
◮ L0, L1, L2, L3, L4, L5, L6, L7 4K×16.
◮ 256K on-chip flash (16-bit)
Memory basics
◮ Organized as 16-bit words.

◮ Managed via a .cmd file.
◮ Probably have to generate different version for specific applications.
◮ We will try to go with a rather simplistic variant.
Execute from RAM or Flash Memory?
◮ Execute from flash when stand-alone.

◮ Flash is slower than RAM.
◮ Can move flash code to RAM. Might only do then for time critical
routines.
◮ This summer we will likely will only run out of RAM.
C memory organization
◮ The Compiler is independent of target processor’s memory

structure. It is not aware of how memory is present nor where it
resides in address space.
◮ It organizes memory using named sections.
◮ A program termed the linker is used to place a program into
memory.
◮ The linker uses a user supplied command file xxx.cmd which lists
where specific sections are to placed into memory.
◮ One would use one .cmd file version when executing out of RAM
and a second .cmd when executing out of flash memory.
◮ C memory can be thought of as either being initialized or
uninitialized.
Initialized sections
◮ .cinit and .pinit contains tables for intializing variables and

constants. Max of 64K.
◮ .const contains string constants switch tables and data defined
using the const qualifier.
◮ .econst as .const but in far memory.
◮ .switch holds tables for switch statements.
◮ .text holds executable code, string literals and computer generated
constants.
From spru514c.pdf.
Uninitialized sections
◮ .bss reserves space for global and static variables. At startup the
boot routine copies data from the .cinit section to initialize
values. Warning, non-initialized variables are not necessarily set to
0!
◮ .ebss as above using far memory.
◮ .stack allocates space for the execution stack. This is used to pass
arguments to functions and to allocate space for local variables.
◮ .sysmem provides space for dynamic memory allocation. (malloc
and calloc manage this).
◮ .esystem as above in far memory.
From spru514c.pdf.
Comment
Table 7-1. Summary of Sections and Memory Placement

Section Type of Memory Page Section Type of Memory Page
.bss RAM 1 .esysmem RAM 1
.cinit ROM or RAM 0 .pinit ROM or RAM 0
.const ROM or RAM 1 .stack RAM 1
.data ROM or RAM .switch ROM or RAM 0, 1
.ebss RAM .sysmem RAM 1
.econst ROM or RAM 1 .text ROM or RAM 0
Page 0 is program memory.

Page 1 is data memory.
From spru514c.pdf.
The F28335 limits.h
/*****************************************************************************/
/* limits.h v5.2.3 */
/* Copyright (c) 1996-2009 Texas Instruments Incorporated */
/*****************************************************************************/
#ifndef _LIMITS
#define _LIMITS
#define CHAR_BIT 16 /* NUMBER OF BITS IN TYPE CHAR */

#define SCHAR_MAX 32767 /* MAX VALUE FOR SIGNED CHAR */
#define SCHAR_MIN (-SCHAR_MAX-1) /* MIN VALUE FOR SIGNED CHAR */
#define UCHAR_MAX 65535u /* MAX VALUE FOR UNSIGNED CHAR */
#define CHAR_MIN SCHAR_MIN /* MIN VALUE FOR CHAR */
#define CHAR_MAX SCHAR_MAX /* MAX VALUE FOR CHAR */
#define MB_LEN_MAX 1
#define SHRT_MAX 32767 /* MAX VALUE FOR SHORT */

#define SHRT_MIN (-SHRT_MAX-1) /* MIN VALUE FOR SHORT */
#define USHRT_MAX 65535u /* MAX VALUE FOR UNSIGNED SHORT */
#define INT_MAX 32767 /* MAX VALUE FOR INT */

#define INT_MIN (-INT_MAX-1) /* MIN VALUE FOR INT */
#define UINT_MAX 65535u /* MAX VALUE FOR UNSIGNED INT */
#define LONG_MAX 2147483647 /* MAX VALUE FOR LONG */

#define LONG_MIN (-LONG_MAX-1) /* MIN VALUE FOR LONG */
#define ULONG_MAX 4294967295 /* MAX VALUE FOR UNSIGNED LONG */
#if defined(__TMS320C28X__)
#define LLONG_MAX 9223372036854775807 /* MAX VALUE FOR LONG LONG */

#define LLONG_MIN (-LLONG_MAX-1) /* MIN VALUE FOR LONG LONG */
#define ULLONG_MAX 18446744073709551615 /* MAX VALUE FOR UNSIGNED LONG LONG */
#else
#define LLONG_MAX LONG_MAX /* MAX VALUE FOR LONG LONG */

#define LLONG_MIN LONG_MIN /* MIN VALUE FOR LONG LONG */
#define ULLONG_MAX ULONG_MAX /* MAX VALUE FOR UNSIGNED LONG LONG */
#endif
#endif /* _LIMITS */
Hmmm
◮ Note that char has size 16 bits (two 8-bit bytes).

◮ What does sizeof return size in terms of? Eight-bit bytes or chars
or 16-bit bytes?
◮ For that matter is their a standard byte size? We commonly assume
8 bits but often documentation uses the term “8-bit byte”.
◮ Shorts are 16 bits in size.
◮ Ints are also 16 bits in size.
◮ longs are 32 bits.
◮ There is a long long which is 64 bits in size.
How do these sizes compare with those found using Visual Studio?
Exercise
Run the visual studio sizeof check on the Code Composer Studio C
compiler.
Compare the results.
How does cope with the differences between systems?
A TI solution
//---------------------------------------------------------------------------
// For Portability, User Is Recommended To Use Following Data Type Size
// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers:
//
#ifndef DSP28_DATA_TYPES
#define DSP28_DATA_TYPES
typedef int int16;
typedef long int32;
typedef long long int64;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
typedef unsigned long long Uint64;
typedef float float32;
typedef long double float64;
#endif
These can be found in various TI supplied header files. I’ve also placed a
copy in the workspace (our creation) include directory in the file
DSP28_DATA_TYPES.h.
Use of sizeof
To compute the size of a given array. For example: given Array, use
ArraySize = sizeof(Array)/sizeof(Array[0]);
This allows writing code that is essentially able to work with any specific
array size.
For example, to send out an array of sequence bits to the D/A converter,
independent of the size of the array, one might write
N = sizeof(sequence_array)/sizeof(char);
for (i = 0; i < N; i++) {
DacOut0(sequence_array[i]);
}
Changing the size of the sequence array leaves the code unchanged.

Today: The TMS320F28335 Microcontroller. Code Composer Studio v4. C As Implemented For The F28355

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Today: The TMS320F28335 microcontroller.

Code Composer Studio v4.

Handouts: Printed copy of today’s lecture slides.

Last one out should close the lab door!!!!

Wirewrap pins and connectors added for CampCAEN summer 2010.

F28335 control stick.

◮ Fast, 150 MHz clock/instruction cycle.

◮ I’ve put my collection of TI documents relative to to F28335 on the

Let’s look at the F28335 data manual.

◮ First entry, TMS320F28335, TMS320F28334, ..., Digital Signal

Let’s look at the F28335 CPU manual.

◮ TMS320C28x CPU and Instruction Set Reference Guide.

◮ 6 high resolution pulse width modulator outputs

88 GPIOs 8 External Interrupts

16-bit peripheral bus 32-bit peripheral bus 32-bit peripheral bus

FIFO FIFO FIFO

From TMS320F28335 data manual.

88 GPIOs 8 External Interrupts

16-bit peripheral bus 32-bit peripheral bus 32-bit peripheral bus

FIFO FIFO FIFO

From TMS320F28335 data manual.

M0 SARAM 1Kx16 L0 SARAM 4K x 16 OTP 1K x 16

From TMS320F28335 data manual.

Data Space Prog Space Data Space Prog Space

0x00 0040 M0 SARAM (1K x 16)

(24x/240x Equivalent Data Space)

L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)

From TMS320F28335 data manual.

◮ Another obligatory slide.

Operations involved in executing an instruction:

By using an instruction pipeline.

Divides execution into eight phases:

◮ Not really. Unless performance has become an issue.

◮ Used across all of TI’s microcomputer/controller lines.

◮ Left panel shows the (current) workspace directory structure.

◮ CCS is reasonably reliable. Can crash on occasion.

◮ Multiple work spaces can be used to organize projects. For example,

Introduces Code Composer Studio and gives practice in using it to create

◮ Will do variations on the Hello World theme.

◮ Run Code Composer Studio. Take the default workspace.

◮ Connecting to the target can take a while, be patient.

for(counter = 0; counter < N; counter++) {

◮ Use of the #define statement to parameterize the code.

Define N equal to 20, rebuild and run.

The program stops running properly at about 7 iterations.

◮ Purpose is to provide a means of recovery if/when something goes

for(counter = 0; counter < N; counter++) {

◮ The watch dog register is protected. Normal writes to it will not

for(counter = 0; counter < N; counter++) {

◮ The WDCR definition allows the watchdog control register to be

◮ The goal is to develop procedures and habits that it make it difficult

◮ A traditional “first” program for a programmer becoming familiar

◮ Controlled by GPIO (general purpose input output) lines 31 and 34.

◮ Documented in sprufb0d.pdf, TMS320x2833x, 2823x System

Table 39. GPIO Control Registers

◮ The GPIO registers are grouped into three groups, A, B and C.

Name Address Size (x16) Register Description

#define GPACTRL *(volatile unsigned long *)0x6F80

◮ Pins default to I/O. Need to only set direction.

◮ Each GPIO pin has several possible functions.

Bits are named increasing from right to left:

31, 30, 29, 28, . . . , 5, 4, 3, 2, 1, 0.

GPAMUX2 = GPAMUX2 & 0x3FFFFFFF; // GPIO31 as IO use

#define GPACTRL (volatile unsigned long )0x6F80