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NA011

Modbus RTU Protocol User Guide


NA011

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Contents
Contents ........................................................................................................................................................................ 2
1 Introduction ........................................................................................................................................................... 3
2 General ................................................................................................................................................................. 3
2.2 Data type ............................................................................................................................................................. 3
2.1 Data interface in Modbus protocol ............................................................................................................... 4
3 MODBUS .............................................................................................................................................................. 5
3.1 General......................................................................................................................................................... 5
3.2 ModBus communication ............................................................................................................................... 5
3.3 Message format............................................................................................................................................ 6
3.4 CRC: Cyclical Redundancy Check............................................................................................................... 6
3.5 Transmission order of data elements........................................................................................................... 7
3.6 Function 03: Read WREG............................................................................................................................ 7
3.7 Function 04: Read RREG............................................................................................................................. 8
3.8 Function 06: Write single register WREG .................................................................................................... 8
3.9 Function 16: Write single or multiple register WREG................................................................................... 9
3.10 Function 08: loopback diagnostic test .......................................................................................................... 9
3.11 Exception responses .................................................................................................................................. 10
4 DATA STRUCTURE FORMAT ........................................................................................................................... 11
4.1 Format description...................................................................................................................................... 11
4.2 Format description example ....................................................................................................................... 11
5 MODBUS COMMUNICATION EXAMPLE .......................................................................................................... 13
5.1 WREG writing in Modbus communication.................................................................................................. 13
5.2 WREG reading in Modbus communication ................................................................................................ 14
6 RREG STRUCTURES DESCRIPTION .............................................................................................................. 15
7 WREG STRUCTURES DESCRIPTION ............................................................................................................. 23
8 COMMAND MESSAGES INDEX........................................................................................................................ 43

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1 Introduction
The protection implements Modbus RTU protocol in remote RS485 half-duplex or local
RS232 connection.
The following operation are supported:
- data reading
- configuration parameters reading and modifying
- command actuation
- communication network test

2 General
Data are structured in 16-bit-wide REGISTERS.
Two class of registers are provided:
- class RREG: read only registers
- class WREG: read/write registers

2.2 Data type


Five tipologies of basic data are employed:
- WORD Stands for signed numerical values within -32768...32767 range.
ModBus maps it into one register.
- UWORD Stands for unsigned numerical values within 0...65535 range.
ModBus maps it into one register.
- LONG Stands for signed numerical values within -2147483648...2147483647 range.
ModBus maps it into two contiguous registers.
- ULONG Stands for unsigned numerical values within 0...4294967295 range.
ModBus maps it into two contiguous registers.
- ENUM Single selection of one of N elements, inside range 0,1,2 ... 65535 max.
ModBus maps it into one register.
- B16 Multiple selection of some of N elements, with N(max) = 16.
Each bit stands for one element: 0=off, 1=on.
ModBus maps it into one register.
- B32 Multiple selection of some of N elements, with N(max) = 32.
Each bit stands for one element: 0=off, 1=on.
ModBus maps it into two consecutive registers.
Basic data, moreover, are linked into STRUCTURES according to their own utilization:
the structure is a group of basic data organized in a well defined order.
Data structures are univocally defined by a number in the range 1...N.
The ModBus protocol is reported to the data with reference to the number of structure
NUM, that is compared to a sort of virtual address: the ModBus rules foresee that in
the messages the ADR structure address is reported, coincident to NUM minus one (from
0 to N-1).

To approach structure, the following informations are needed:


- the virtual structure address (ADR, corresponding to NUM-1)
- the structure size (DIM)
Reading and/or writing multiple consecutive structures is allowed, the "size" must be
the sum of the single DIM of the contiguous structures of interest up to a max limit
of 246 (DIM=246)
Section 6 collects the read only RREG structures.
Section 7 collects the read/write WREG structures.

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Section 8 collects WREG structures for command activations.

2.1 Data interface in Modbus protocol


The implemented ModBus functions are:
- data reading
- reading and change of configuration parameters
- command actuations
- communication diagnostic test
The protocol introduces standard interface functions to read or write registers and
carry out diagnostic test, identified by a well defined numerical code FUNC.

Data reading is performed through the functions:


- FUNC=04 -> reading RREG registers
- FUNC=03 -> reading WREG registers
The writing of data or the actuation of commands, are performed through the
functions:
- FUNC=06 -> writing of one register WREG
- FUNC=16 -> writing of one or more registers WREG

Commands execution is performed writing the values specified in the command register;
at the end of the execution the register are automatically cleared by the protection.
It is possible to read the command registers as well as any other register.
The diagnostic test of the communication line is performed through the 'loopback
test' ModBus function:

- FUNC=08 -> loopback test

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3 MODBUS

3.1 General
The protection implements a functional subset of the RTU ModBus protocol:
FUNC 04: read input register
FUNC 03: read output register
FUNC 06: preset single register
FUNC 16: preset multiple registers
FUNC 08: loopback diagnostic test

The ModBus protocol allows communication within a master unit (personal computer or
supervisor) and different slave devices (multi point system), in our case a
protection system. Every protection is univocally identified by an address (Slave
address) programmable in the field 1...247.
The 'broadcast addressing" (address=0) allows the dispatching of a message to all the
protections of the system: every protection manages the message but it doesn't send
back response to avoid collision on the bus.
The protection allows the remote connection with interface RS485 half-duplex, or
local with interface RS232, through the ModBus RTU protocol.
In remote mode, the protection is shaped as Slave in a multidrop system and it
answers only if addressed by the master (personal computer or supervisor) with own
address (1...247).
In local mode, the protection results to be in point-to-point connection, or
individual with the master (personal computer), it answers any request ignoring the
address.

3.2 ModBus communication


A ModBus communication consists of dispatching of a 'request' message from the
master unit (personal computer or supervisor) toward the protection, with consequent,
if everything is all right, response from slave; three cases are introduced:
- response ok
- response reports some error (see 'exception response')
- no response returned: a some serious communication error is occured.

It is possible to program the protection so that response to the master with a


settable delay; such delay is composed by two times:
- en_delay: delay to the activation of Slave transmitter
- tx_delay: delay to the transmission of Slave response.
The time <en_delay> allows to overcome the possible one 'tail' (you see A-B) of the
transmitter master that hocks the communication line.
The time <tx_delay> allows the stabilization of the communication line before
activating the transmission of the response.

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A B
driver 485 tx on ----------------+
MASTER trasmission ...XXXXXXXX |
driver 485 tx off +----------------------------------

+-----------+ <- en_delay (A-C)


+--------+ <- tx_delay (C-D)

C D
driver 485 tx on +----------------------------
SLAVE trasmission | XXXXXXXXXXXXXXXXX...
driver 485 tx off ----------------------+

where:
B Master 'request' transmission expiring time
B Master transmitter disable
C Slave transmitter enable
D Slave 'answer' start transmission

For minimum answer time, both timers must be set to zero.

3.3 Message format


The general ModBus RTU frame message is the following:

| ADDR | FUNC | ...BODY... | CRCH | CRCL |


|------|------|----------------|--------|--------|
byte 1 byte 2 ... byte n-1 byte n

where:
ADDR protection relay addressing:
- 0 = broadcast
- 1...247 = slave address
FUNC function code:
- 04 read input RREG register
- 03 read output WREG register
- 06 preset single WREG register
- 16 preset multiple WREG registers
- 08 loopback diagnostic test
BODY data body: contents depends from the FUNC code
CRCH MSB CRC byte
CRCL LSB CRC byte

BODY contents within message depends from FUNC code.


In the following paragraphs only the BODY field is described, for the rest please
refer to the general form of the message.

3.4 CRC: Cyclical Redundancy Check


The CRC (Cyclical Redundancy Check) assures that during transmission no corruptions
of the message are occured.
For information on the computed method, please refer to the ModBus literature.

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3.5 Transmission order of data elements
Every WORD, UWORD, ENUM or B16 data, expressed by one register (2 bytes), is sent
according to the following order (left to right):

... | REG | ...


... | H | L | ...
|--------|--------|
byte n byte n+1 example:
11h 22h --> ENUM == 1122h (4386 dec)

Every LONG, ULONG or B32 data, expressed by two register (4 bytes), is sent according
to the following order (left to right):

... | REG L | REG H | ...


... | H | L | H | L | ...
|--------|--------|--------|--------|
byte n byte n+1 byte n+2 byte n+3 example:
99h AAh 77h 88h --> LONG == 778899AAh (2005440938 dec)

3.6 Function 03: Read WREG


Body field framing:

Request:

| ADR | DIM |
| H | L | H | L |
|------|------|------|------|
byte 1 byte 2 byte 3 byte 4

Response:

|NBYTES| WREG1 | WREG2 | ... | WREG(DIM) |


| | H | L | H | L | ... | H | L |
|------|------|------|------|------| |--------|------|
byte 1 byte 2 byte 3 byte 4 byte 5 ... byte n-1 byte n

where:
ADR reference to the data structure of WREG class:
ADR =0 if NUM=1, ADR =1 if NUM=2, ... etc.
DIM size of the WREG data structure (number of registers)
NBYTES number of bytes from WREG1 to WREG(DIM): double of DIM
WREG1.. registers that have been read

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3.7 Function 04: Read RREG


Body field framing:

Request:

| ADR | DIM |
| H | L | H | L |
|------|------|------|------|
byte 1 byte 2 byte 3 byte 4

Response:

|NBYTES| RREG1 | RREG2 | ... | RREG(DIM) |


| | H | L | H | L | ... | H | L |
|------|------|------|------|------| |--------|------|
byte 1 byte 2 byte 3 byte 4 byte 5 ... byte n-1 byte n

where:
ADR reference to the data structure of RREG class:
ADR=0 if NUM=1, ADR=1 if NUM=2, ... etc.
DIM size of the RREG data structure(number of registers)
NBYTES number of bytes from RREG1 to RREG(DIM): double of DIM
RREG1.. registers that have been read

3.8 Function 06: Write single register WREG


Body field framing:

Request:

This service can be used only for data structures WREG composed by one only register.
Message framing:
Request:

| ADR | VALUE |
| H | L | H | L |
|------|------|------|------|
byte 1 byte 2 byte 3 byte 4

Response: the confirmation response is identical to the request message.

where:
ADR reference to the data structure of WREG:
ADR=0 if NUM=1, ADR=1 if NUM=2, ... etc.
VALUE writing value (only one register)

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3.9 Function 16: Write single or multiple register WREG


Body field framing:

Request:

| ADR | DIM |NBYTES| WREG1 | ... | WREG(DIM) |


| H | L | H | L | | H | L | ... | H | L |
|------|------|------|------|------|------|------| |--------|------|
byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 ... byte n-1 byte n

Response:

| ADR | DIM |
| H | L | H | L |
|------|------|------|------|
byte 1 byte 2 byte 3 byte 4

where:
ADR reference to the data structure of WREG class:
ADR=0 if NUM=1, ADR=1 if NUM=2, ... etc.
DIM size of the WREG data structure(number of registers)
NBYTES number of bytes from WREG1 to WREG(DIM): double of DIM
WREG1.. writing registers

3.10 Function 08: loopback diagnostic test


MODBUS function code 08 provides a test for checking the communication system between
a Master and a Slave. The response message is identical to the request.
The contents of some remote devices diagnostic register are returned in the response;
the diagnostic register are cleared.

Message framing:
Request:

| CODE | DATA |
| H | L | H | L |
|------|------|------|------|
byte 1 byte 2 byte 3 byte 4

Response:

| CODE | INFO |
| H | L | H | L |
|------|------|------|------|
byte 1 byte 2 byte 3 byte 4

where:
CODE diagnostic test code
DATA accessory data for diagnostic function
INFO data returned from diagnostic test

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Here the list of diagnostic codes supported by the serial line devices:

- return query data (loopback) Request: CODE = 0, DATA = 12345


Response: INFO = DATA
- return Diagnostic Register Request: CODE = 2, DATA = 0
Response: INFO = diagnostic register
- clear Diagnostic Register Request: CODE = 10, DATA = 0
Response: INFO = 0
- return Bus Message Count Request: CODE = 11, DATA = 0
Response: INFO = counter
- return Bus Communication Error Count Request: CODE = 12, DATA = 0
Response: INFO = counter
- return Bus Exception Error Count Request: CODE = 13, DATA = 0
Response: INFO = counter
- return Slave Message Count Request: CODE = 14, DATA = 0
Response: INFO = counter
- return Slave No Response Count Request: CODE = 15, DATA = 0
Response: INFO = counter
- return Slave NAK Count Request: CODE = 16, DATA = 0
Response: INFO = counter
- return Slave Busy Count Request: CODE = 17, DATA = 0
Response: INFO = counter

3.11 Exception responses


Any query received that contains a non-existent device address, a framing error, or
CRC error is ignored. No response is transmitted and the CRC counter errors is
incremented. Queries addressed to a protection relay with an unsupported function or
illegal values in the data block result in an error response message with an
exception response code.
The supported exception response codes are provided below.

Exception response message framing:

| ADDR | FUNC | EXCP | CRCH | CRCL |


|------|------|------|------|------|
byte 1 byte 2 byte 3 byte 4 byte 5

where:
ADDR address
FUNC error code (bit 7 = 1):
To mark error, the most significant bit of the request message is set.
EXCP exception code:
- 01: illegal function -> FUNC non implementata
- 02: illegal data address -> invalid address ADR
- 03: illegal data value -> DIM icorrect value
- 04: slave device failure -> not used
- 05: acknowledge -> not used
- 06: slave device busy -> not used
- 07: negative acknowledge -> generic error:
- framing error in the response
- out of range data
- etc.
- 08: memory parity error -> not used
CRCH MSB byte
CRCL LSB byte

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4 DATA STRUCTURE FORMAT

4.1 Format description


The list of data structure RREG and WREG is provided in sections 6 and 7 of this
document.
Following elements are included in the description:
- progressive number
- structure name
- basic data layout
- size expressed in number of 16 bit registers
- synopsis: concise list of data useful for the message building
Standard message format:

NUM Description: STRU_NAME


Framing:
TYPE [NR] DATA_NAME (...comments)
comments
TYPE [NR] DATA_NAME (...comments)
comments
...
Dimension : DIM
Synopsis : SYNOPSIS

where:
NUM data structure number within proper class:
example: RREG NUM=5 (5th structure of RREG class)
WREG NUM=3 (3th structure of WREG class)
STRU_NAME structure name
NR nr. of register: it points position (nr. of 16 bit registers) within
structure (from 1 to n)
TYPE data type identifier related to NR:
it may be WORD, UWORD, LONG, ULONG, ENUM, B32 o B16.
example: UWORD[ 1] (UWORD data type in first position)
ULONG[ 2] (ULONG data type in second position)
ENUM [ 4] (ENUM data type in 4th position)
B32 [ 5] (B32 data type in 5th position)
B16 [ 7] (B16 data type in 7th position)
DATA_NAME name.
DIM Structure global size (nr. of 16 bit registers)
SYNOPSIS concise collection of message package informations.
It shows the form:
class ... -> ADR=... (NUM=...), DIM=...

4.2 Format description example


Following example shows an hypotethetical data framing of WREG class number 5 named
<Protection>, with five basic data:
1) UWORD <Time>
2) ULONG <Range>
3) ENUM <Enable>
4) B32 <Selection>
5) B16 <Configuration>
The structure is made up of seven registers.
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WREG NUM=5 Description : Protection


Framing:
UWORD[ 1] Time (1=10 ms)
1,1000 step 1
ULONG[ 2] Range
1000,1000000000 step 1000
ENUM [ 4] Enable
0 OFF
1 ON
B32 [ 5] Selection
bit 0 RELAY1
bit 1 RELAY2
bit 2 RELAY3
bit 3 RELAY4
bit 4 RELAY5
bit 5 RELAY6
B16 [ 7] Configuration
bit 0 LED1
bit 1 LED2
bit 2 LED3
Dimension : 7 registers
Synopsis : class WREG -> ADR=4 (NUM=5), DIM=7

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5 MODBUS COMMUNICATION EXAMPLE

5.1 WREG writing in Modbus communication


The objective is to write on the protection Slave with address 33 (21 hex), the WREG
structure (NUM=5, DIM=7) introduced in the preceding section, with the following
values:
- Time = 550 0226 hex
- Range = 500885000 1DDAE608 hex
- Enable = ON 0001 hex
- Selection = RELE2+RELE5 00000012 hex
- Configuration = LED1+LED2+LED3 0007 hex

WREG writing requires the FUNC=16 (10 hex) ModBus function.


Remember that the structure NUM=5 must be pointed out with ADR=4 in the message, that
is with NUM-1.

Request (values in hex format):

|--------------------------------------------------------------------|
|ADDR|FUNC| BODY |CRCH|CRCL|
|----|----|----|----|----|-----|--------|----|--------|----|----|----|
|ADR |DIM |NBYT|UWORD| ULONG |ENUM| B32 |B16 |
|----|----|----|-----|--------|----|--------|----|
21 10 0004 0007 0E 0226 E6081DDA 0001 00120000 0007 2C C5

Response (values in hex format):

|-----------------------------|
|ADDR|FUNC| BODY |CRCH|CRCL|
|----|----|----|----|----|----|
|ADR |DIM |
|----|----|
21 10 0004 0007 C7 6A

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5.2 WREG reading in Modbus communication


The purpose is to read the structure introduced in preceding paragraph.
WREG reading requires the ModBus function FUNC=03.
Remember that the structure NUM=5 must be pointed out with ADR=4 in the message, that
is with NUM-1.

Request (values in hex format):

|-----------------------------|
|ADDR|FUNC| BODY |CRCH|CRCL|
|----|----|----|----|----|----|
|ADR |DIM |
|----|----|
21 03 0004 0007 42 A9

Response (values in hex format):

|----------------------------------------------------------|
|ADDR|FUNC| BODY |CRCH|CRCL|
|----|----|----|-----|--------|----|--------|----|----|----|
|NBYT|UWORD| ULONG |ENUM| B32 |B16 |
|----|-----|--------|----|--------|----|
21 03 0E 0226 E6081DDA 0001 00120000 0007 B9 26

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6 RREG STRUCTURES DESCRIPTION


39 RREG structures are defined:

RREG NUM=1 Identification


RREG NUM=2 Information
RREG NUM=3 RESERVED
RREG NUM=4 RESERVED
RREG NUM=5 Self-test diagnostics
RREG NUM=6 Clock
RREG NUM=7 Oscillo info
RREG NUM=8 Oscillo state
RREG NUM=9 Fault info
RREG NUM=10 Fault
RREG NUM=11 Event info
RREG NUM=12 Event
RREG NUM=13 Protections trip
RREG NUM=14 IL1
RREG NUM=15 IL2
RREG NUM=16 IL3
RREG NUM=17 IE
RREG NUM=18 IN1 input
RREG NUM=19 IN2 input
RREG NUM=20 IN3 input
RREG NUM=21 Position
RREG NUM=22 Counter start I>
RREG NUM=23 Counter start I>>
RREG NUM=24 Counter start I>>>
RREG NUM=25 Counter start IE>
RREG NUM=26 Counter start IE>>
RREG NUM=27 Counter trip I>
RREG NUM=28 Counter trip I>>
RREG NUM=29 Counter trip I>>>
RREG NUM=30 Counter trip IE>
RREG NUM=31 Counter trip IE>>
RREG NUM=32 Counter trip EXT
RREG NUM=33 Counter 79 RR
RREG NUM=34 Counter 79 SR
RREG NUM=35 Counter 79 DR
RREG NUM=36 Counter 79 FR P
RREG NUM=37 Counter 79 FR E
RREG NUM=38 Counter 79 FR X
RREG NUM=39 AutoReclose read

Every structure is listed.

RREG NUM=1 Description : Identification


Framing :
UWORD[ 1] Identification (1=SIF; 2=SVF ...)
ULONG[ 2] Serial number
UWORD[ 4] FW release (format: XX.XX hex)
UWORD[ 5] Protocol release (format: XX.XX hex)
Dimension : 5 registers
Synopsis : class RREG -> ADR=0 (NUM=1), DIM=5

RREG NUM=2 Description : Information


Framing :

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ENUM [ 1] Code (NA011-a ...)
0 NA011-CB0-c
ULONG[ 2] Serial
UWORD[ 4] Firmware release (format: XX.XX hex)
UWORD[ 5] Nominal freq.
Dimension : 5 registers
Synopsis : class RREG -> ADR=1 (NUM=2), DIM=5

RREG NUM=3 RESERVED

RREG NUM=4 RESERVED

RREG NUM=5 Description : Self-test diagnostics


Framing :
ENUM [ 1] Self-test
0 None
1 Minor
2 Major
3 Fatal
B16 [ 2] Self-test cause
bit 0 Stack overflow
bit 1 reserved
bit 2 Eeprom overflow
bit 3 Eeprom CAL fail
bit 4 Eeprom PAR fail
bit 5 Eeprom REE fail
bit 6 reserved
bit 7 reserved
bit 8 Breaker Failure
B16 [ 3] Self-test latch
bit 0 Stack overflow
bit 1 reserved
bit 2 Eeprom overflow
bit 3 Eeprom CAL fail
bit 4 Eeprom PAR fail
bit 5 Eeprom REE fail
bit 6 reserved
bit 7 reserved
bit 8 Breaker Failure
Dimension : 3 registers
Synopsis : class RREG -> ADR=4 (NUM=5), DIM=3

RREG NUM=6 Description : Clock


Framing :
UWORD[ 1] Year
2000,2099 step 1
UWORD[ 2] Month
1,12 step 1
UWORD[ 3] Day
1,31 step 1
UWORD[ 4] Hour
0,23 step 1
UWORD[ 5] Minute
0,59 step 1
UWORD[ 6] Second
0,59 step 1
Dimension : 6 registers
Synopsis : class RREG -> ADR=5 (NUM=6), DIM=6

RREG NUM=7 Description : Oscillo info

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Framing :
UWORD[ 1] Records stored
0,2 step 1
UWORD[ 2] Last record
0,2 step 1
Dimension : 2 registers
Synopsis : class RREG -> ADR=6 (NUM=7), DIM=2

RREG NUM=8 Description : Oscillo state


Framing :
ENUM [ 1] Recorder state
0 Init
1 Start
2 Acquire
3 Trigger
4 Store
5 Reset
6 Off
7 Error
Dimension : 1 registers
Synopsis : class RREG -> ADR=7 (NUM=8), DIM=1

RREG NUM=9 Description : Fault info


Framing :
UWORD[ 1] Faults stored
0,20 step 1
UWORD[ 2] Last fault
0,20 step 1
Dimension : 2 registers
Synopsis : class RREG -> ADR=8 (NUM=9), DIM=2

RREG NUM=10 Description : Fault


Framing :
UWORD[ 1] F - Number
0,20 step 1
ENUM [ 2] F - Cause
0 None
1 Start I>
2 Start I>>
3 Start I>>>
4 Start IE>
5 Start IE>>
6 Trip I>
7 Trip I>>
8 Trip I>>>
9 Trip IE>
10 Trip IE>>
11 Trip EXT
B16 [ 3] F - Phases
bit 0 IL1
bit 1 IL2
bit 2 IL3
ULONG[ 4] F - IL1
ULONG[ 6] F - IL2
ULONG[ 8] F - IL3
ULONG[10] F - IE
UWORD[12] F - Year
2000,2099 step 1
UWORD[13] F - Month
1,12 step 1

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UWORD[14] F - Day
1,31 step 1
UWORD[15] F - Hour
0,23 step 1
UWORD[16] F - Minute
0,59 step 1
UWORD[17] F - Second
0,59 step 1
UWORD[18] F - Millisecond
0,999 step 1
Dimension : 18 registers
Synopsis : class RREG -> ADR=9 (NUM=10), DIM=18

RREG NUM=11 Description : Event info


Framing :
UWORD[ 1] Events stored
0,50 step 1
UWORD[ 2] Last event
0,50 step 1
Dimension : 2 registers
Synopsis : class RREG -> ADR=10 (NUM=11), DIM=2

RREG NUM=12 Description : Event


Framing :
UWORD[ 1] E - Number
0,50 step 1
ENUM [ 2] E - Cause
0 None
1 Overflow
2 Power down
3 Power up
4 Start I>
5 Start I>>
6 Start I>>>
7 Start IE>
8 Start IE>>
9 Trip I>
10 Trip I>>
11 Trip I>>>
12 Trip IE>
13 Trip IE>>
14 Trip EXT
15 BF ON
16 BF OFF
17 IN1 ON
18 IN1 OFF
19 IN2 ON
20 IN2 OFF
21 IN3 ON
22 IN3 OFF
23 ALARM CB ON
24 ALARM CB OFF
25 CB open MMI
26 CB close MMI
27 CB open MBUS
28 CB close MBUS
29 CB open P103
30 CB close P103
31 79 disabled
32 79 blocked

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33 79 enabled
34 79 manual close
35 79 start
36 79 rapid close
37 79 slow close
38 79 delayed close
39 79 interrupted
40 79 fail phase
41 79 fail earth
42 79 fail external
43 79 rapid ok
44 79 slow ok
45 79 delayed ok
UWORD[ 3] E - Year
2000,2099 step 1
UWORD[ 4] E - Month
1,12 step 1
UWORD[ 5] E - Day
1,31 step 1
UWORD[ 6] E - Hour
0,23 step 1
UWORD[ 7] E - Minute
0,59 step 1
UWORD[ 8] E - Second
0,59 step 1
UWORD[ 9] E - Millisecond
0,999 step 1
Dimension : 9 registers
Synopsis : class RREG -> ADR=11 (NUM=12), DIM=9

RREG NUM=13 Description : Protections trip


Framing :
B16 [ 1] Protections trip
bit 0 Trip I>
bit 1 Trip I>>
bit 2 Trip I>>>
bit 3 Trip IE>
bit 4 Trip IE>>
bit 5 Trip EXT
default: 0x0000
Dimension : 1 registers
Synopsis : class RREG -> ADR=12 (NUM=13), DIM=1

RREG NUM=14 Description : IL1


Framing :
ULONG[ 1] IL1 (dir: 1000=1 A; rel: 1000=1 In)
Dimension : 2 registers
Synopsis : class RREG -> ADR=13 (NUM=14), DIM=2

RREG NUM=15 Description : IL2


Framing :
ULONG[ 1] IL2 (dir: 1000=1 A; rel: 1000=1 In)
Dimension : 2 registers
Synopsis : class RREG -> ADR=14 (NUM=15), DIM=2

RREG NUM=16 Description : IL3


Framing :
ULONG[ 1] IL3 (dir: 1000=1 A; rel: 1000=1 In)
Dimension : 2 registers
Synopsis : class RREG -> ADR=15 (NUM=16), DIM=2

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RREG NUM=17 Description : IE


Framing :
ULONG[ 1] IE (dir: 100000=1 A; rel: 100000=1 In)
Dimension : 2 registers
Synopsis : class RREG -> ADR=16 (NUM=17), DIM=2

RREG NUM=18 Description : IN1 input


Framing :
ENUM [ 1] IN1 input
0 OFF
1 ON
Dimension : 1 registers
Synopsis : class RREG -> ADR=17 (NUM=18), DIM=1

RREG NUM=19 Description : IN2 input


Framing :
ENUM [ 1] IN2 input
0 OFF
1 ON
Dimension : 1 registers
Synopsis : class RREG -> ADR=18 (NUM=19), DIM=1

RREG NUM=20 Description : IN3 input


Framing :
ENUM [ 1] IN3 input
0 OFF
1 ON
Dimension : 1 registers
Synopsis : class RREG -> ADR=19 (NUM=20), DIM=1

RREG NUM=21 Description : Position


Framing :
ENUM [ 1] Position
0 Unknown
1 Open
2 Closed
3 Alarm
Dimension : 1 registers
Synopsis : class RREG -> ADR=20 (NUM=21), DIM=1

RREG NUM=22 Description : Counter start I>


Framing :
UWORD[ 1] Counter ST I>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=21 (NUM=22), DIM=1

RREG NUM=23 Description : Counter start I>>


Framing :
UWORD[ 1] Counter ST I>>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=22 (NUM=23), DIM=1

RREG NUM=24 Description : Counter start I>>>


Framing :
UWORD[ 1] Counter ST I>>>
0,10000 step 1
Dimension : 1 registers

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Synopsis : class RREG -> ADR=23 (NUM=24), DIM=1

RREG NUM=25 Description : Counter start IE>


Framing :
UWORD[ 1] Counter ST IE>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=24 (NUM=25), DIM=1

RREG NUM=26 Description : Counter start IE>>


Framing :
UWORD[ 1] Counter ST IE>>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=25 (NUM=26), DIM=1

RREG NUM=27 Description : Counter trip I>


Framing :
UWORD[ 1] Counter TR I>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=26 (NUM=27), DIM=1

RREG NUM=28 Description : Counter trip I>>


Framing :
UWORD[ 1] Counter TR I>>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=27 (NUM=28), DIM=1

RREG NUM=29 Description : Counter trip I>>>


Framing :
UWORD[ 1] Counter TR I>>>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=28 (NUM=29), DIM=1

RREG NUM=30 Description : Counter trip IE>


Framing :
UWORD[ 1] Counter TR IE>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=29 (NUM=30), DIM=1

RREG NUM=31 Description : Counter trip IE>>


Framing :
UWORD[ 1] Counter TR IE>>
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=30 (NUM=31), DIM=1

RREG NUM=32 Description : Counter trip EXT


Framing :
UWORD[ 1] Counter TR EXT
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=31 (NUM=32), DIM=1

RREG NUM=33 Description : Counter 79 RR


Framing :

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UWORD[ 1] Counter 79 RR
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=32 (NUM=33), DIM=1

RREG NUM=34 Description : Counter 79 SR


Framing :
UWORD[ 1] Counter 79 SR
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=33 (NUM=34), DIM=1

RREG NUM=35 Description : Counter 79 DR


Framing :
UWORD[ 1] Counter 79 DR
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=34 (NUM=35), DIM=1

RREG NUM=36 Description : Counter 79 FR P


Framing :
UWORD[ 1] Counter 79 FR P
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=35 (NUM=36), DIM=1

RREG NUM=37 Description : Counter 79 FR E


Framing :
UWORD[ 1] Counter 79 FR E
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=36 (NUM=37), DIM=1

RREG NUM=38 Description : Counter 79 FR X


Framing :
UWORD[ 1] Counter 79 FR X
0,10000 step 1
Dimension : 1 registers
Synopsis : class RREG -> ADR=37 (NUM=38), DIM=1

RREG NUM=39 Description : AutoReclose read


Framing :
ENUM [ 1] 79 ActiveMode
0 OFF
1 ON
ENUM [ 2] 79 Run
0 OFF
1 ON
ENUM [ 3] 79 CycleState
0 Reset
1 Disabled
2 Blocked
3 Off
4 Rapid
5 Slow
6 Delayed
7 Discrimination
8 Neutralization
9 Fail
UWORD[ 4] 79 Residual-time (1=0.1 s)

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default: 0
ENUM [ 5] 79 LastEvent
0 None
1 Disable
2 Block
3 Enable
4 Start
5 Manual close
6 Rapid
7 Slow
8 Delayed
9 Rapid OK
10 Slow OK
11 Delayed OK
12 Interrupted
13 Fail phase
14 Fail earth
15 Fail ext
Dimension : 5 registers
Synopsis : class RREG -> ADR=38 (NUM=39), DIM=5

7 WREG STRUCTURES DESCRIPTION


67 WREG structures are defined:

WREG NUM=1 RESERVED


WREG NUM=2 Comando Config PAR
WREG NUM=3 Comando Config REE
WREG NUM=4 Reset commands
WREG NUM=5 Test commands
WREG NUM=6 CB commands
WREG NUM=7 R79 commands
WREG NUM=8 Set clock
WREG NUM=9 Modbus slave address
WREG NUM=10 Protocol RS485
WREG NUM=11 Baudrate RS485
WREG NUM=12 Modbus delay
WREG NUM=13 Oscillo set
WREG NUM=14 Fault read
WREG NUM=15 Event read
WREG NUM=16 IL line data
WREG NUM=17 IE line data
WREG NUM=18 Measures reading
WREG NUM=19 K1 configuration
WREG NUM=20 K2 configuration
WREG NUM=21 K3 configuration
WREG NUM=22 K4 configuration
WREG NUM=23 I> curve
WREG NUM=24 ICLP>
WREG NUM=25 tCLP>
WREG NUM=26 t>RES
WREG NUM=27 I>def
WREG NUM=28 ICLP>def
WREG NUM=29 t>def
WREG NUM=30 I>inv
WREG NUM=31 ICLP>inv
WREG NUM=32 t>inv

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WREG NUM=33 ICLP>>
WREG NUM=34 tCLP>>
WREG NUM=35 t>>RES
WREG NUM=36 I>>def
WREG NUM=37 ICLP>>def
WREG NUM=38 t>>def
WREG NUM=39 ICLP>>>
WREG NUM=40 tCLP>>>
WREG NUM=41 t>>>RES
WREG NUM=42 I>>>def
WREG NUM=43 ICLP>>>def
WREG NUM=44 t>>>def
WREG NUM=45 IE> curve
WREG NUM=46 IECLP>
WREG NUM=47 tECLP>
WREG NUM=48 tE>RES
WREG NUM=49 IE>def
WREG NUM=50 IECLP>def
WREG NUM=51 tE>def
WREG NUM=52 IE>inv
WREG NUM=53 IECLP>inv
WREG NUM=54 tE>inv
WREG NUM=55 IECLP>>
WREG NUM=56 tECLP>>
WREG NUM=57 tE>>RES
WREG NUM=58 IE>>def
WREG NUM=59 IECLP>>def
WREG NUM=60 tE>>def
WREG NUM=61 BF Enable
WREG NUM=62 tBF
WREG NUM=63 IN1 select
WREG NUM=64 IN2 select
WREG NUM=65 IN3 select
WREG NUM=66 AutoReclose set
WREG NUM=67 AutoReclose trigger

Every structure is listed in detail.

WREG NUM=1 RESERVED

WREG NUM=2 Description : Comando Config PAR


Framing :
UWORD[ 1] Command PAR
1 Clear
2 Store
3 PAR default
Dimension : 1 registers
Synopsis : class WREG -> ADR=1 (NUM=2), DIM=1

WREG NUM=3 Description : Comando Config REE


Framing :
UWORD[ 1] Command REE
3 REE default
Dimension : 1 registers
Synopsis : class WREG -> ADR=2 (NUM=3), DIM=1

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WREG NUM=4 Description : Reset commands


Framing :
UWORD[ 1] Reset commands
4 Reset faults
2 Reset events
1 Reset counters
8 Reset led-relay
Dimension : 1 registers
Synopsis : class WREG -> ADR=3 (NUM=4), DIM=1

WREG NUM=5 Description : Test commands


Framing :
UWORD[ 1] Test commands
0 Test off
1 Test I> led
2 Test I>> led
3 Test I>>> led
4 Test IE> led
5 Test IE>> led
4097 Test I> full
4098 Test I>> full
4099 Test I>>> full
4100 Test IE> full
4101 Test IE>> full
Dimension : 1 registers
Synopsis : class WREG -> ADR=4 (NUM=5), DIM=1

WREG NUM=6 Description : CB commands


Framing :
UWORD[ 1] CB commands
1 CB Open
2 CB Close
Dimension : 1 registers
Synopsis : class WREG -> ADR=5 (NUM=6), DIM=1

WREG NUM=7 Description : R79 commands


Framing :
UWORD[ 1] R79 commands
1 AutoReclose off
2 AutoReclose on
Dimension : 1 registers
Synopsis : class WREG -> ADR=6 (NUM=7), DIM=1

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WREG NUM=8 Description : Set clock


Framing :
UWORD[ 1] Set year
2000,2099 step 1
default: 2000
UWORD[ 2] Set month
1,12 step 1
default: 1
UWORD[ 3] Set day
1,31 step 1
default: 1
UWORD[ 4] Set hour
0,23 step 1
default: 0
UWORD[ 5] Set minute
0,59 step 1
default: 0
UWORD[ 6] Set second
0,59 step 1
default: 0
Dimension : 6 registers
Synopsis : class WREG -> ADR=7 (NUM=8), DIM=6

WREG NUM=9 Description : Modbus slave address


Framing :
UWORD[ 1] Address
1,247 step 1
default: 1
Dimension : 1 registers
Synopsis : class WREG -> ADR=8 (NUM=9), DIM=1

WREG NUM=10 Description : Protocol RS485


Framing :
ENUM [ 1] Protocol RS485
0 Modbus
1 IEC60870-5-103
Dimension : 1 registers
Synopsis : class WREG -> ADR=9 (NUM=10), DIM=1

WREG NUM=11 Description : Baudrate RS485


Framing :
ENUM [ 1] Baudrate RS485
0 1200
1 2400
2 4800
3 9600
4 19200
5 38400
6 57600
default: 3
Dimension : 1 registers
Synopsis : class WREG -> ADR=10 (NUM=11), DIM=1

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WREG NUM=12 Description : Modbus delay


Framing :
UWORD[ 1] Enable TX delay (ms)
0,50 step 1
default: 2
UWORD[ 2] Start TX delay (ms)
0,10 step 1
default: 1
Dimension : 2 registers
Synopsis : class WREG -> ADR=11 (NUM=12), DIM=2

WREG NUM=13 Description : Oscillo set


Framing :
UWORD[ 1] Pre-trigger
0,63 step 1
default: 2
B16 [ 2] Trigger
bit 0 Manual
bit 1 General Start
bit 2 General Trip
bit 3 IN1
bit 4 IN2
bit 5 IN3
bit 6 K1
bit 7 K2
bit 8 K3
bit 9 K4
bit 10 Auxiliar
default: 0
B16 [ 3] Trigger aux
bit 0 Start I>
bit 1 Start I>>
bit 2 Start I>>>
bit 3 Start IE>
bit 4 Start IE>>
bit 5 Trip I>
bit 6 Trip I>>
bit 7 Trip I>>>
bit 8 Trip IE>
bit 9 Trip IE>>
default: 0
B16 [ 4] Digital channels
bit 0 General Start
bit 1 General Trip
bit 2 IN1
bit 3 IN2
bit 4 IN3
bit 5 K1
bit 6 K2
bit 7 K3
bit 8 K4
default: 0

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ENUM [ 5] Analog channel 1
0 OFF
1 iL1
2 iL2
3 iL3
4 iE
5 measure IL1
6 measure IL2
7 measure IL3
8 measure IE
default: 0
ENUM [ 6] Analog channel 2
0 OFF
1 iL1
2 iL2
3 iL3
4 iE
5 measure IL1
6 measure IL2
7 measure IL3
8 measure IE
default: 0
ENUM [ 7] Analog channel 3
0 OFF
1 iL1
2 iL2
3 iL3
4 iE
5 measure IL1
6 measure IL2
7 measure IL3
8 measure IE
default: 0
ENUM [ 8] Analog channel 4
0 OFF
1 iL1
2 iL2
3 iL3
4 iE
5 measure IL1
6 measure IL2
7 measure IL3
8 measure IE
default: 0
Dimension : 8 registers
Synopsis : class WREG -> ADR=12 (NUM=13), DIM=8

WREG NUM=14 Description : Fault read


Framing :
UWORD[ 1] Fault read
1,20 step 1
default: 1
Dimension : 1 registers
Synopsis : class WREG -> ADR=13 (NUM=14), DIM=1

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WREG NUM=15 Description : Event read
Framing :
UWORD[ 1] Event read
1,50 step 1
default: 1
Dimension : 1 registers
Synopsis : class WREG -> ADR=14 (NUM=15), DIM=1

WREG NUM=16 Description : IL line data


Framing :
UWORD[ 1] Inp value
1,99 step 1
100,5000 step 5
default: 300
ENUM [ 2] Inp unit
0 A
default: 0
Dimension : 2 registers
Synopsis : class WREG -> ADR=15 (NUM=16), DIM=2

WREG NUM=17 Description : IE line data


Framing :
UWORD[ 1] IEnp value
1,99 step 1
100,5000 step 5
default: 100
ENUM [ 2] IEnp unit
0 A
default: 0
Dimension : 2 registers
Synopsis : class WREG -> ADR=16 (NUM=17), DIM=2

WREG NUM=18 Description : Measures reading


Framing :
ENUM [ 1] Reading
0 Relative
1 Direct
default: 1
Dimension : 1 registers
Synopsis : class WREG -> ADR=17 (NUM=18), DIM=1

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WREG NUM=19 Description : K1 configuration


Framing :
B32 [ 1] K1
bit 0 Self Test
bit 1 Start I>
bit 2 Start I>>
bit 3 Start I>>>
bit 4 Start IE>
bit 5 Start IE>>
bit 6 Trip I>
bit 7 Trip I>>
bit 8 Trip I>>>
bit 9 Trip IE>
bit 10 Trip IE>>
bit 11 Trip EXT
bit 12 Breaker Failure
bit 13 79 Close
bit 14 79 Run
bit 15 79 Fail
bit 16 CB Close
bit 17 CB Open
bit 18 Self Test CB
default: 0
ENUM [ 3] K1 logic
0 De-energized
1 Energized
default: 0
ENUM [ 4] K1 mode
0 No-latched
1 Latched
default: 0
UWORD[ 5] K1 tTR (1=10 ms)
1,50 step 1
default: 20
Dimension : 5 registers
Synopsis : class WREG -> ADR=18 (NUM=19), DIM=5

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WREG NUM=20 Description : K2 configuration


Framing :
B32 [ 1] K2
bit 0 Self Test
bit 1 Start I>
bit 2 Start I>>
bit 3 Start I>>>
bit 4 Start IE>
bit 5 Start IE>>
bit 6 Trip I>
bit 7 Trip I>>
bit 8 Trip I>>>
bit 9 Trip IE>
bit 10 Trip IE>>
bit 11 Trip EXT
bit 12 Breaker Failure
bit 13 79 Close
bit 14 79 Run
bit 15 79 Fail
bit 16 CB Close
bit 17 CB Open
bit 18 Self Test CB
default: 0
ENUM [ 3] K2 logic
0 De-energized
1 Energized
default: 0
ENUM [ 4] K2 mode
0 No-latched
1 Latched
default: 0
UWORD[ 5] K2 tTR (1=10 ms)
1,50 step 1
default: 20
Dimension : 5 registers
Synopsis : class WREG -> ADR=19 (NUM=20), DIM=5

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WREG NUM=21 Description : K3 configuration


Framing :
B32 [ 1] K3
bit 0 Self Test
bit 1 Start I>
bit 2 Start I>>
bit 3 Start I>>>
bit 4 Start IE>
bit 5 Start IE>>
bit 6 Trip I>
bit 7 Trip I>>
bit 8 Trip I>>>
bit 9 Trip IE>
bit 10 Trip IE>>
bit 11 Trip EXT
bit 12 Breaker Failure
bit 13 79 Close
bit 14 79 Run
bit 15 79 Fail
bit 16 CB Close
bit 17 CB Open
bit 18 Self Test CB
default: 0
ENUM [ 3] K3 logic
0 De-energized
1 Energized
default: 0
ENUM [ 4] K3 mode
0 No-latched
1 Latched
default: 0
UWORD[ 5] K3 tTR (1=10 ms)
1,50 step 1
default: 20
Dimension : 5 registers
Synopsis : class WREG -> ADR=20 (NUM=21), DIM=5

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WREG NUM=22 Description : K4 configuration


Framing :
B32 [ 1] K4
bit 0 Self Test
bit 1 Start I>
bit 2 Start I>>
bit 3 Start I>>>
bit 4 Start IE>
bit 5 Start IE>>
bit 6 Trip I>
bit 7 Trip I>>
bit 8 Trip I>>>
bit 9 Trip IE>
bit 10 Trip IE>>
bit 11 Trip EXT
bit 12 Breaker Failure
bit 13 79 Close
bit 14 79 Run
bit 15 79 Fail
bit 16 CB Close
bit 17 CB Open
bit 18 Self Test CB
default: 0
ENUM [ 3] K4 logic
0 De-energized
1 Energized
default: 0
ENUM [ 4] K4 mode
0 No-latched
1 Latched
default: 0
UWORD[ 5] K4 tTR (1=10 ms)
1,50 step 1
default: 20
Dimension : 5 registers
Synopsis : class WREG -> ADR=21 (NUM=22), DIM=5

WREG NUM=23 Description : I> curve


Framing :
ENUM [ 1] I>Curve
0 DEFINITE
1 IEC/BS A
2 IEC/BS B
3 IEC/BS C
4 ANSI/IEEE MI
5 ANSI/IEEE VI
6 ANSI/IEEE EI
default: 2
Dimension : 1 registers
Synopsis : class WREG -> ADR=22 (NUM=23), DIM=1

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WREG NUM=24 Description : ICLP>


Framing :
ENUM [ 1] ICLP>
0 Off
1 On-Blocking
2 On-Changing
Dimension : 1 registers
Synopsis : class WREG -> ADR=23 (NUM=24), DIM=1

WREG NUM=25 Description : tCLP>


Framing :
UWORD[ 1] tCLP> (1=10 ms)
0,999 step 1
1000,10000 step 10
default: 10
Dimension : 1 registers
Synopsis : class WREG -> ADR=24 (NUM=25), DIM=1

WREG NUM=26 Description : t>RES


Framing :
UWORD[ 1] t>RES (1=10 ms)
0,100 step 1
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=25 (NUM=26), DIM=1

WREG NUM=27 Description : I>def


Framing :
UWORD[ 1] I>def (1000=1 In)
100,999 step 1
1000,9990 step 10
10000,20000 step 100
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=26 (NUM=27), DIM=1

WREG NUM=28 Description : ICLP>def


Framing :
UWORD[ 1] ICLP>def (1000=1 In)
100,999 step 1
1000,9990 step 10
10000,20000 step 100
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=27 (NUM=28), DIM=1

WREG NUM=29 Description : t>def


Framing :
UWORD[ 1] t>def (1=10 ms)
3,1000 step 1
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=28 (NUM=29), DIM=1

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WREG NUM=30 Description : I>inv


Framing :
UWORD[ 1] I>inv (1000=1 In)
100,999 step 1
1000,2500 step 10
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=29 (NUM=30), DIM=1

WREG NUM=31 Description : ICLP>inv


Framing :
UWORD[ 1] ICLP>inv (1000=1 In)
100,999 step 1
1000,10000 step 10
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=30 (NUM=31), DIM=1

WREG NUM=32 Description : t>inv


Framing :
UWORD[ 1] t>inv (1=10 ms)
2,999 step 1
1000,6000 step 10
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=31 (NUM=32), DIM=1

WREG NUM=33 Description : ICLP>>


Framing :
ENUM [ 1] ICLP>>
0 Off
1 On-Blocking
2 On-Changing
Dimension : 1 registers
Synopsis : class WREG -> ADR=32 (NUM=33), DIM=1

WREG NUM=34 Description : tCLP>>


Framing :
UWORD[ 1] tCLP>> (1=10 ms)
0,999 step 1
1000,10000 step 10
default: 10
Dimension : 1 registers
Synopsis : class WREG -> ADR=33 (NUM=34), DIM=1

WREG NUM=35 Description : t>>RES


Framing :
UWORD[ 1] t>>RES (1=10 ms)
0,100 step 1
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=34 (NUM=35), DIM=1

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WREG NUM=36 Description : I>>def


Framing :
UWORD[ 1] I>>def (1000=1 In)
100,999 step 1
1000,9990 step 10
10000,20000 step 100
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=35 (NUM=36), DIM=1

WREG NUM=37 Description : ICLP>>def


Framing :
UWORD[ 1] ICLP>>def (1000=1 In)
100,999 step 1
1000,9990 step 10
10000,20000 step 100
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=36 (NUM=37), DIM=1

WREG NUM=38 Description : t>>def


Framing :
UWORD[ 1] t>>def (1=10 ms)
3,1000 step 1
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=37 (NUM=38), DIM=1

WREG NUM=39 Description : ICLP>>>


Framing :
ENUM [ 1] ICLP>>>
0 Off
1 On-Blocking
2 On-Changing
Dimension : 1 registers
Synopsis : class WREG -> ADR=38 (NUM=39), DIM=1

WREG NUM=40 Description : tCLP>>>


Framing :
UWORD[ 1] tCLP>>> (1=10 ms)
0,999 step 1
1000,10000 step 10
default: 10
Dimension : 1 registers
Synopsis : class WREG -> ADR=39 (NUM=40), DIM=1

WREG NUM=41 Description : t>>>RES


Framing :
UWORD[ 1] t>>>RES (1=10 ms)
0,100 step 1
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=40 (NUM=41), DIM=1

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WREG NUM=42 Description : I>>>def
Framing :
UWORD[ 1] I>>>def (1000=1 In)
100,999 step 1
1000,9990 step 10
10000,20000 step 100
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=41 (NUM=42), DIM=1

WREG NUM=43 Description : ICLP>>>def


Framing :
UWORD[ 1] ICLP>>>def (1000=1 In)
100,999 step 1
1000,9990 step 10
10000,20000 step 100
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=42 (NUM=43), DIM=1

WREG NUM=44 Description : t>>>def


Framing :
UWORD[ 1] t>>>def (1=10 ms)
3,1000 step 1
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=43 (NUM=44), DIM=1

WREG NUM=45 Description : IE> curve


Framing :
ENUM [ 1] IE>Curve
0 DEFINITE
1 IEC/BS A
2 IEC/BS B
3 IEC/BS C
4 ANSI/IEEE MI
5 ANSI/IEEE VI
6 ANSI/IEEE EI
default: 2
Dimension : 1 registers
Synopsis : class WREG -> ADR=44 (NUM=45), DIM=1

WREG NUM=46 Description : IECLP>


Framing :
ENUM [ 1] IECLP>
0 Off
1 On-Blocking
2 On-Changing
Dimension : 1 registers
Synopsis : class WREG -> ADR=45 (NUM=46), DIM=1

Version 1.20
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WREG NUM=47 Description : tECLP>


Framing :
UWORD[ 1] tECLP> (1=10 ms)
0,999 step 1
1000,10000 step 10
default: 10
Dimension : 1 registers
Synopsis : class WREG -> ADR=46 (NUM=47), DIM=1

WREG NUM=48 Description : tE>RES


Framing :
UWORD[ 1] tE>RES (1=10 ms)
0,100 step 1
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=47 (NUM=48), DIM=1

WREG NUM=49 Description : IE>def


Framing :
UWORD[ 1] IE>def (1000=1 In)
5,999 step 1
1000,5000 step 10
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=48 (NUM=49), DIM=1

WREG NUM=50 Description : IECLP>def


Framing :
UWORD[ 1] IECLP>def (1000=1 In)
5,999 step 1
1000,5000 step 10
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=49 (NUM=50), DIM=1

WREG NUM=51 Description : tE>def


Framing :
UWORD[ 1] tE>def (1=10 ms)
3,1000 step 1
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=50 (NUM=51), DIM=1

WREG NUM=52 Description : IE>inv


Framing :
UWORD[ 1] IE>inv (1000=1 In)
5,999 step 1
1000,2000 step 10
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=51 (NUM=52), DIM=1

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WREG NUM=53 Description : IECLP>inv
Framing :
UWORD[ 1] IECLP>inv (1000=1 In)
5,999 step 1
1000,2000 step 10
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=52 (NUM=53), DIM=1

WREG NUM=54 Description : tE>inv


Framing :
UWORD[ 1] tE>inv (1=10 ms)
2,999 step 1
1000,6000 step 10
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=53 (NUM=54), DIM=1

WREG NUM=55 Description : IECLP>>


Framing :
ENUM [ 1] IECLP>>
0 Off
1 On-Blocking
2 On-Changing
Dimension : 1 registers
Synopsis : class WREG -> ADR=54 (NUM=55), DIM=1

WREG NUM=56 Description : tECLP>>


Framing :
UWORD[ 1] tECLP>> (1=10 ms)
0,999 step 1
1000,10000 step 10
default: 10
Dimension : 1 registers
Synopsis : class WREG -> ADR=55 (NUM=56), DIM=1

WREG NUM=57 Description : tE>>RES


Framing :
UWORD[ 1] tE>>RES (1=10 ms)
0,100 step 1
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=56 (NUM=57), DIM=1

WREG NUM=58 Description : IE>>def


Framing :
UWORD[ 1] IE>>def (1000=1 In)
5,999 step 1
1000,5000 step 10
default: 1000
Dimension : 1 registers
Synopsis : class WREG -> ADR=57 (NUM=58), DIM=1

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WREG NUM=59 Description : IECLP>>def


Framing :
UWORD[ 1] IECLP>>def (1000=1 In)
5,999 step 1
1000,5000 step 10
default: 2000
Dimension : 1 registers
Synopsis : class WREG -> ADR=58 (NUM=59), DIM=1

WREG NUM=60 Description : tE>>def


Framing :
UWORD[ 1] tE>>def (1=10 ms)
3,1000 step 1
default: 100
Dimension : 1 registers
Synopsis : class WREG -> ADR=59 (NUM=60), DIM=1

WREG NUM=61 Description : BF Enable


Framing :
B16 [ 1] BF Enable
bit 0 Trip I>
bit 1 Trip I>>
bit 2 Trip I>>>
bit 3 Trip IE>
bit 4 Trip IE>>
bit 5 Trip EXT
default: 0x0000
Dimension : 1 registers
Synopsis : class WREG -> ADR=60 (NUM=61), DIM=1

WREG NUM=62 Description : tBF


Framing :
UWORD[ 1] tBF (1=10 ms)
10,99 step 1
100,1000 step 5
default: 50
Dimension : 1 registers
Synopsis : class WREG -> ADR=61 (NUM=62), DIM=1

WREG NUM=63 Description : IN1 select


Framing :
ENUM [ 1] IN1 select
0 None
1 52b
2 Trip EXT
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=62 (NUM=63), DIM=1

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WREG NUM=64 Description : IN2 select


Framing :
ENUM [ 1] IN2 select
0 None
1 52a
2 Trip EXT
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=63 (NUM=64), DIM=1

WREG NUM=65 Description : IN3 select


Framing :
ENUM [ 1] IN3 select
0 None
1 79 Enable
2 79 Remote
3 Trip EXT
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=64 (NUM=65), DIM=1

WREG NUM=66 Description : AutoReclose set


Framing :
ENUM [ 1] 79 Enable
0 OFF
1 ON
ENUM [ 2] 79 Mode
0 Rapid
1 Rapid+Slow
UWORD[ 3] 79 N.DAR
0,5 step 1
UWORD[ 4] 79 trdt
1,199 step 1
200,600 step 10
UWORD[ 5] 79 tsdt
10,2000 step 10
UWORD[ 6] 79 td
0,100 step 10
UWORD[ 7] 79 tr
10,2000 step 10
ENUM [ 8] 79 MC-td-EN
0 OFF
1 ON
ENUM [ 9] 79 MO-RES
0 OFF
1 ON
Dimension : 9 registers
Synopsis : class WREG -> ADR=65 (NUM=66), DIM=9

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WREG NUM=67 Description : AutoReclose trigger


Framing :
B16 [ 1] 79 Trigger
bit 0 Trip I>
bit 1 Trip I>>
bit 2 Trip I>>>
bit 3 Trip IE>
bit 4 Trip IE>>
bit 5 Trip REMOTE
default: 0
Dimension : 1 registers
Synopsis : class WREG -> ADR=66 (NUM=67), DIM=1

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8 COMMAND MESSAGES INDEX


Following WREG structures accomplish command actuation.

WREG NUM=2 Command code:


1 Clear
2 Store
3 PAR default
WREG NUM=3 Command code:
3 REE default
WREG NUM=4 Command code:
4 Reset faults
2 Reset events
1 Reset counters
8 Reset led-relay
WREG NUM=5 Command code:
0 Test off
1 Test I> led
2 Test I>> led
3 Test I>>> led
4 Test IE> led
5 Test IE>> led
4097 Test I> full
4098 Test I>> full
4099 Test I>>> full
4100 Test IE> full
4101 Test IE>> full
WREG NUM=6 Command code:
1 CB Open
2 CB Close
WREG NUM=7 Command code:
1 AutoReclose off
2 AutoReclose on

SECTION 9 DEFAULTS INDEX

This section collects factory default data.

WREG NUM=8 Set year 2000 (2000)


Set month 1 (1)
Set day 1 (1)
Set hour 0 h (0)
Set minute 0 m (0)
Set second 0 s (0)

WREG NUM=9 Address 1 (1)

WREG NUM=11 Baudrate RS485 9600 (3)

WREG NUM=12 Enable TX delay 2 ms (2)


Start TX delay 1 ms (1)

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WREG NUM=13 Pre-trigger 2 T (2)


Trigger 0
Trigger aux 0
Digital channels 0
Analog channel 1 OFF (0)
Analog channel 2 OFF (0)
Analog channel 3 OFF (0)
Analog channel 4 OFF (0)

WREG NUM=14 Fault read 1 [uuu] (1)

WREG NUM=15 Event read 1 [uuu] (1)

WREG NUM=16 Inp value 300 (300)


Inp unit A (0)

WREG NUM=17 IEnp value 100 (100)


IEnp unit A (0)

WREG NUM=18 Reading Direct (1)

WREG NUM=19 K1 0
K1 logic De-energized (0)
K1 mode No-latched (0)
K1 tTR 200 ms (20)

WREG NUM=20 K2 0
K2 logic De-energized (0)
K2 mode No-latched (0)
K2 tTR 200 ms (20)

WREG NUM=21 K3 0
K3 logic De-energized (0)
K3 mode No-latched (0)
K3 tTR 200 ms (20)

WREG NUM=22 K4 0
K4 logic De-energized (0)
K4 mode No-latched (0)
K4 tTR 200 ms (20)

WREG NUM=23 I>Curve IEC/BS B (2)

WREG NUM=25 tCLP> 0.10 s (10)

WREG NUM=26 t>RES 0 ms (0)

WREG NUM=27 I>def 1.00 In (1000)

WREG NUM=28 ICLP>def 2.00 In (2000)

WREG NUM=29 t>def 1.00 s (100)

WREG NUM=30 I>inv 1.00 In (1000)

WREG NUM=31 ICLP>inv 2.00 In (2000)

WREG NUM=32 t>inv 1.00 s (100)

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WREG NUM=34 tCLP>> 0.10 s (10)

WREG NUM=35 t>>RES 0 ms (0)

WREG NUM=36 I>>def 1.00 In (1000)

WREG NUM=37 ICLP>>def 2.00 In (2000)

WREG NUM=38 t>>def 1.00 s (100)

WREG NUM=40 tCLP>>> 0.10 s (10)

WREG NUM=41 t>>>RES 0 ms (0)

WREG NUM=42 I>>>def 1.00 In (1000)

WREG NUM=43 ICLP>>>def 2.00 In (2000)

WREG NUM=44 t>>>def 1.00 s (100)

WREG NUM=45 IE>Curve IEC/BS B (2)

WREG NUM=47 tECLP> 0.10 s (10)

WREG NUM=48 tE>RES 0 ms (0)

WREG NUM=49 IE>def 1.00 IEn (1000)

WREG NUM=50 IECLP>def 2.00 IEn (2000)

WREG NUM=51 tE>def 1.00 s (100)

WREG NUM=52 IE>inv 1.00 In (1000)

WREG NUM=53 IECLP>inv 2.00 In (2000)

WREG NUM=54 tE>inv 1.00 s (100)

WREG NUM=56 tECLP>> 0.10 s (10)

WREG NUM=57 tE>>RES 0 ms (0)

WREG NUM=58 IE>>def 1.00 IEn (1000)

WREG NUM=59 IECLP>>def 2.00 IEn (2000)

WREG NUM=60 tE>>def 1.00 s (100)

WREG NUM=61 BF Enable 0x0000

WREG NUM=62 tBF 0.50 s (50)

WREG NUM=63 IN1 select None (0)

WREG NUM=64 IN2 select None (0)

WREG NUM=65 IN3 select None (0)

WREG NUM=67 79 Trigger 0

Version 1.20
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