Professional Documents
Culture Documents
Microsemi ModelSim Simulation Frequently Asked Questions
Microsemi ModelSim Simulation Frequently Asked Questions
ModelSim Simulation
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
Microsemi Corporate Headquarters rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to
One Enterprise, Aliso Viejo, independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
CA 92656 USA hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
Outside the USA: +1 (949) 380-6100 rights, whether with regard to such information itself or anything described by such information. Information provided in this
Fax: +1 (949) 215-4996 document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
Email: sales.support@microsemi.com
www.microsemi.com About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
© 2017 Microsemi Corporation. All
aerospace & defense, communications, data center and industrial markets. Products include high-performance and
rights reserved. Microsemi and the
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
Microsemi logo are trademarks of timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing
Microsemi Corporation. All other devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and
trademarks and service marks are the scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
property of their respective owners. capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Library Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Where can I find the ModelSim simulation library for standalone users? . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Do I need to add the specific family library statement into the VHDL source code for
functional simulation? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.3 When using ModelSim Standalone as part of the Libero IDE flow, how to fix the following error? . . . . . 5
3.4 How can we use an older version of ModelSim with a newer version of Libero IDE/SoC or vice versa? 5
3.5 How to prevent the error ** Fatal: (vsim-3381) obsolete library format for design unit. . . . . . . . . . . . . . . 5
3.6 Does Microsemi support ProASIC3 libraries for the Eagle EDA tool? . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.7 The simulation file (ProASIC3.v) includes the register notify_reg. Is there any way to use this register?
Also, if +notimingchecks switch with vsim is used in ModelSim, it disables all timing checks. So, can we
mask some timing violations but not all? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.8 When running Libero IDE/SoC on Linux, simulating the design using ModelSim results in the following
error. How do we fix it? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 License Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 How do I get a free Libero License? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 # Microsemi version supports only a single HDL # ** Error: (vsim-3039) / Why doesn’t a mixed HDL
simulation run? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.3 Is mixed language simulation supported in all the license types? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.4 ModelSim license parallel port dongle: I had Libero v8.0 and upgraded to v8.3 but now ModelSim is no
longer working; it throws a license checkout error message. Why? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.5 How to fix the Fatal License Error: Evaluation Error Code: 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.6 How to fix the ModelSim License Error# ** Error: Failure to obtain a VHDL simulation license? . . . . . . 7
4.7 I installed Microsemi Libero. I am able to open the Libero project manager but cannot open ModelSim. It
is not giving any warning or error. But if I click ModelSim from the project manager, it shows the ModelSim
icon and then does not open anything. Why? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 ModelSim Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 How do I set the simulation run time? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2 How do I set the time in ModelSim so it runs 6 ns? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3 How do I turn off the warning message in ModelSim? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 How can I turn off the ModelSim vital glitch warning during the post-layout simulation? . . . . . . . . . . . . . 9
5.5 How can I view the sub module signals in the ModelSim wave window? . . . . . . . . . . . . . . . . . . . . . . . . 9
5.6 How can I retain my radix in the wave window after I manually change them to a desired value for all
simulations in a particular project? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1 When I run ModelSim, my computer hangs, with vsimk.exe at 100% CPU usage. I cannot shut down
ModelSim during this time. I must wait for 10 minutes until vsmik.exe stops running. Why? . . . . . . . . 16
7.2 In PLL simulation (pre-synth, post-synth, and post route) some output frequencies do not show up as
expected. Why? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3 Post-synthesis and post-layout simulation give invalid results for the INOUT bus. INOUT bus with initial
value 'U' within netlist causes unknown in post-synthesis and post-layout simulation. How do I get a valid
result? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 SmartPower does not annotate all pins when the VCD file generated by ModelSim is imported into
designer. Why? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.1 Why does Modelsim exit with error code 211 for all the projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.2 How to fix the ModelSim Simulation Error #**Fatal:(vsim-3881)? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.3 How do I simulate two Microsemi field programmable gate arrays together in a system simulation? . . 18
8.4 Failed to find instance # ERROR: C:/Designs/annotations/interface.sdf(15): Failed to find INSTANCE
'/testbench/ramwrn_1' # ERROR: C:/Designs/annotations/interface.sdf(24): Failed to find INSTANCE
'/testbench/block_1' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.5 How to fix # Error: could not open socket: invalid argument Trouble making server . . . . . . . . . . . . . . . 19
8.6 How to ** Error: (vsim-3174) Package 'D:\Microsemi\Libero_v9.1\Model\std.standard'
requires a body? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.7 Why are the back annotated timing results different from what I can see in SmartTime? . . . . . . . . . . . 19
8.8 In Libero IDE project manager settings there is a way to send extra command line arguments to the VSIM
command. Is there a way to add a command line argument to the vlog command? . . . . . . . . . . . . . . . 20
8.9 What is the solution if the below error is observed ** Fatal: SDF files require Microsemi
primitive library? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
3 Library Issues
4 License Issues
5 ModelSim Features
5.4 How can I turn off the ModelSim vital glitch warning
during the post-layout simulation?
Use the +no_glitch_msg flag for the vsim command. Though it is not always recommended, it is useful to
look at the real problem (setup or hold)
Example:
vsim +no_glitch_msg -L apa -L postlayout -t 1ps -sdfmax
/berkana_0=D:/FA/project_dir/TestVector/designer/impl1/berkana_ba.sdf
postlayout.testbench
5.5 How can I view the sub module signals in the ModelSim
wave window?
You can add sub module signals by browsing through the hierarchy and selecting the sub module from
the ModelSim command window, then select ViewSignals from ModelSim pull down menu.
In the Signal window, you can highlight the signals you want to add in the Wave window, then click,
Add Wave to add the signals in the waveform, as shown in the following figure.
Restart the simulation and run it again. If you want to save the wave format you have added into the
wave window, use the command Save Format inside the Wave window.
7 Known Issues
7.4 SmartPower does not annotate all pins when the VCD file
generated by ModelSim is imported into designer. Why?
Close to 100% annotation can only be expected, if you are importing a post-layout VCD. If you import
pre-synthesis and post-synthesis VCDs, the SmartPower netlist is different from the netlist that was
simulated.
Remove all escaped characters in the VCD file manually. For example, if the VCD file is as follows:
$var wire 1 - \cnt_c[0]\ $end
$var wire 1 . \cnt_c[1]\ $end
$var wire 1 / \cnt_c[2]\ $end
$var wire 1 0 \cnt_c[3]\ $end
Modify the signal as:
$var wire 1 - cnt_c[0] $end
$var wire 1 . cnt_c[1] $end
$var wire 1 / cnt_c[2] $end
$var wire 1 0 cnt_c[3] $end
Re-import the modified VCD file into Designer.
8 Miscellaneous
8.1 Why does Modelsim exit with error code 211 for all the
projects?
It may be related to anti-virus software, blocking the Modelsim. Disable the anti-virus, install the
ModelSim and check if the tool passes the simulation (anti-virus should be disabled for the entire
process).
To specify the region in ModelSim, from the command line type: -sdftyp <region>=<SDF file path/name>
Command line for this example: vsim -sdftyp /testbench/dut=./annotations/interface.sdf testbench
Figure 5 • Add SDF Entry Window
Note: This example uses the C:/Designs directory. The instance hierarchical path would now be
/testbench/dut/ramwrn_1, which is a valid path in the design, and not the default /testbench/ramwrn_1.
If the default path does not work, you must ensure that the region concatenated with the instance path in
the SDF file results in a valid hierarchical path that exists in the loaded design.
8.7 Why are the back annotated timing results different from
what I can see in SmartTime?
Check the timescale defined at the top of the SDF file (usually set as timescale 100 ps). This means that
100 unit delay would actually mean a 10 ns delay.