Cache memory:

each CPU has its cache

very expensive so small
von neuman bottleneck
cache hit: cache has the required piece of memory
cache miss: cache doesnot have the required piece of memory
filling the cache:
1. Data cache:
2. instruction cache: easier to fill, because predictable
OR levels of cache:
level 1
level 2: very large size(in MBs - 4MB,8MB),slower, shared by CPUs
server CPUs have level 3 cache as well, upto 32MB
address in RAM -> Hash Function -> address in Cache
2 way cache, 2 slots per address of cache, there are also 4, 8, etc. but this
decreases performance

DMA(direct memory access)

uses the