C4

DEC 30043
MICROPROCESSOR FUNDAMENTALS

ASSEMBLY LANGUAGE :
PROCESSING DATA
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 ASSEMBLY LANGUAGE : PROCESSING DATA
4.1 Understanding the instruction of data process
4.1.1 Explain Arithmetic operation
4.1.2 Explain Logical operation
4.1.3 Explain Shift and rotate operation
4.1.4 Elaborate reverse data bytes in the register

4.2 Apply assembly language instructions to write program

4.2.1 Draw the flowchart for a processing data problem.

4.2.2 Write assembly programs to perform the arithmetic tasks: ADD,
ADD with carry, SUBTRACT, SUBTRACT with borrow, e.
MULTIPLY and DIVIDE operation.
4.2.3 Examine the changes of status register (flag) when the related
instructions in 4.2.2 are executed
4.2.4 Write assembly programs to perform the logical tasks: AND, OR,
CLEAR, OR NOT and EXCLUSIVE OR operation
4.2.5 Examine the changes of status register (flag) when the related
instructions in section 4.2.4 are executed.
4.2.6 Write assembly programs to perform the shift and rotate tasks:

CHAPTER4
ARITHMATIC SHIFT RIGHT, LOGICAL SHIFT LEFT, LOGICAL
SHIFT RIGHT , ROTATE RIGHT, ROTATE operation.
4.2.7 Examine the changes of status register (flag) when the related
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instructions in section 4.2.6 are executed.
4.1 UNDERSTANDING
THE INSTRUCTION
OF DATA
PROCESS
4.1.1 Arithmetic operation

 Many data operation instructions can have multiple instruction formats.

 Basic symbol for arithmetic operation is:

Operation Instruction
ADD ADD Rd, Rn, Rm ; Rd = Rn + Rm
ADD Rd, Rd, Rm ; Rd = Rd + Rm
ADD Rd, #immed ; Rd = Rd + #immed
ADD Rd, Rn, # immed ; Rd = Rn + #immed
ADD with carry ADC Rd, Rn, Rm ; Rd = Rn + Rm + carry
ADC Rd, Rd, Rm ; Rd = Rd + Rm + carry
ADC Rd, #immed ; Rd = Rd + #immed + carry
SUBTRACT SUB Rd, Rn, Rm ; Rd = Rn − Rm
SUB Rd, #immed ; Rd = Rd − #immed
SUB Rd, Rn,#immed ; Rd = Rn − #immed
SUBTRACT with SBC Rd, Rm ; Rd = Rd − Rm − borrow
borrow (not carry) SBC.W Rd, Rn, #immed ; Rd = Rn − #immed − borrow
SBC.W Rd, Rn, Rm ; Rd = Rn − Rm − borrow

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 Operation Instruction
MULTIPLY MUL Rd, Rm ; Rd = Rd * Rm
MUL.W Rd, Rn, Rm ; Rd = Rn * Rm
DIVIDE UDIV Rd, Rn, Rm ; Rd = Rn/Rm
SDIV Rd, Rn, Rm ; Rd = Rn/Rm

The Cortex-M4 also supports 32-bit multiply instructions and multiply accumulate instructions that
give 64-bit results. These instructions support signed or unsigned values

Operation Instruction
32-bit multiply SMULL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} = Rn * Rm
instructions for signed SMLAL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} += Rn * Rm
values
32-bit multiply UMULL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} = Rn * Rm
instructions for UMLAL RdLo, RdHi, Rn, Rm ; {RdHi,RdLo} += Rn * Rm
unsigned values

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4.1.2 Logical operation

 Another group of data processing instructions are the logical operations instructions.
 These instructions can be used with or without the “S” suffix to determine if the APSR should
be updated.
Operation Instruction
Bitwise AND AND Rd, Rn ; Rd = Rd & Rn
AND.W Rd, Rn,#immed ; Rd = Rn & #immed
AND.W Rd, Rn, Rm ; Rd = Rn & Rd
Bitwise OR ORRRd, Rn ; Rd = Rd | Rn
ORR.W Rd, Rn,#immed ; Rd = Rn | #immed
ORR.W Rd, Rn, Rm ; Rd = Rn | Rd
Bit clear BIC Rd, Rn ; Rd = Rd & (~Rn)
BIC.W Rd, Rn,#immed ; Rd = Rn &(~#immed)
BIC.W Rd, Rn, Rm ; Rd = Rn &(~Rd)
Bitwise OR NOT ORN.W Rd, Rn,#immed ; Rd = Rn | (~#immed)
ORN.W Rd, Rn, Rm ; Rd = Rn | (~Rd)
Bitwise Exclusive OR EOR Rd, Rn ; Rd = Rd ^ Rn
EOR.W Rd, Rn,#immed ; Rd = Rn | #immed
EOR.W Rd, Rn, Rm ; Rd = Rn | Rd
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4.1.3 Shift and rotate operation

 The rotate operation can be combined with other operations (for example, in memory address
offset calculation for load/store instructions).
 A 32-bit version of the instruction is used if “S” suffix is not used and if UAL syntax is used.

Operation Instruction
Arithmetic shift right ASR Rd, Rn,#immed ; Rd = Rn » immed
ASRRd, Rn ; Rd = Rd » Rn
ASR.W Rd, Rn, Rm ; Rd = Rn » Rm
Logical shift left LSLRd, Rn,#immed ; Rd = Rn « immed
LSLRd, Rn ; Rd = Rd « Rn
LSL.W Rd, Rn, Rm ; Rd = Rn « Rm
Logical shift right LSRRd, Rn,#immed ; Rd = Rn » immed
LSRRd, Rn ; Rd = Rd » Rn
LSR.W Rd, Rn, Rm ; Rd = Rn » Rm
Rotate right ROR Rd, Rn ; Rd rot by Rn
ROR.W Rd, Rn,#immed ; Rd = Rn rot by immed
ROR.W Rd, Rn, Rm ; Rd = Rn rot by Rm
Rotate right extended RRX.W Rd, Rn ; {C, Rd} = {Rn, C}
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 Shift and rotate instruction
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4.1.4 Reverse data bytes in the register

 These instructions are usually used for conversion between little endian and big endian data.

Operation Instruction
Reverse bytes in word REV Rd, Rn ; Rd = rev(Rn)

Reverse bytes in each half word REV16 Rd, Rn ; Rd = rev16(Rn)

Reverse bytes in bottom half word and REVSH Rd, Rn ; Rd = revsh(Rn)

sign extend the result

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 4.2 APPLY ASSEMBLY
LANGUAGE
INSTRUCTIONS TO
WRITE PROGRAM

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4.2.1 Flowchart

Graphical method to plan flow of Basic shapes:

our programs.
Terminator.
Shows program’s step-by-step
Process.
operation.
Decision.
Easy to understand and analyze.
Input/Output.
Can be used to write organized
programs. Connectors.

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 Flowchart

BASIC SHAPES – TERMINATOR BASIC SHAPES - PROCESS

 Indicates beginning and end of  Describes actions to be done.

flowchart.  Represented as rectangles. Short
 Once at beginning, once at end. description of process in rectangle.

Examples: Examples:

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 Flowchart BASIC SHAPES - DECISION

BASIC SHAPES – INPUT/OUTPUT  Shows alternative program flow

based on condition.
 Shows the process of inputting or  Represented as diamond shape.
outputting data.  Should have 2 arrows, representing
 Represented using rhombus. TRUE and FALSE program flows.
 Can be used in “if…else”, “while”, and
Examples: “for” situations.
Examples:

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 Flowchart

EXAMPLE: CONNECTOR
BASIC SHAPES - CONNECTORS

 Used to link large process flows

together.
 Represented using circles, with
numbers inside.
 Numbers indicate connection.

Examples:
 Elements of a
flow chart

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 Flowchart
Problem:
Input data of two numbers. These two numbers are added, and the product is stored in a register.

Programming
Based on the flow chart we can now write out a program,
Data 1  R0 as shown below
Data 2  R1

START
MOVS R0, #12
R0 + R1  R0 MOVS R1, #34
ADD R0, R0, R1
MOVS R2, R0
B START
R0  Register R2 END

Flow chart of instructions

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 Flowchart
R1
Example: Calculate Area of Rectangle
R2

START

Input R1 MOVS R1, #0x12

Input R1
R1 = R1 x R2
Input R2 MOVS R2, #0x34

Input R2
R1 = R1 x R2 MULS R2, R1, R2
END

END B START
END

Flow chart of instructions Translation to Assembly

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 Flowchart

Try It Yourself

1. Draw a flowchart and the programming to calculate an area of a circle. The radius is equal to 4.

2. Draw a flowchart and the programming that performs 2’s complement on a number in R0.

3. Draw a flowchart and the programming to inspect the contents R4 and if the contents are greater
than 0x55, divide the value with 0x5 and store the result at register R5. Otherwise, multiply it with 0x3
and store the result in register R6.

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 Flags in ARM Processors
4.2.3 PROGRAM STATUS REGISTER (PSR)

ARM Program Status Register Format

The ARM processor normally contains at least the Z, N, C, and V flags, which are updated by
execution of data processing instructions.

 Z (Zero) flag: This flag is set when the result of an instruction has a zero value or when a
comparison of two data returns an equal result.
 N (Negative) flag: This flag is set when the result of an instruction has a negative value (bit 31
is 1).
 C (Carry) flag: This flag is for unsigned data processing - for example, in add (ADD) it is set
when an overflow occurs; in subtract (SUB) it is set when a borrow did not occur (borrow is the
invert of carry).
 V (Overflow) flag: This flag is for signed data processing; for example, in an add (ADD), when
two positive values added together produce a negative value, or when two negative values
added together produce a positive value.
4.2.3 ARITHMETIC : ADD OPERATION ADD Rd, Rn, Rm ; Rd = Rn + Rm

Examples 1:
If R2 and R3 contain 0x22446688 and 0x77553311, respectively, what are the results of ADDS R1, R2, R3?

Instruction Data Calculation Answer

ADDS R1, R2, R3 R2 = 0x22446688 22446688 + 77553311 R1 = 0x99999999

R3 = 0x77553311 = 99999999 in Hex

V- Overflow Bit
APSR Set during arithmetic/divide overflow.
Z = 0 (result non zero) For ADD, SUB & CMP:
N = 1 (MSB = 1) V=1
 P+P=N
C = 0 (No carry)  N+N=P * P = Positive Number (MSB = 0)
V = 1 (P + P = N)  P–N=N N = Negative Number (MSB = 1)
 N–P=P

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4.2.3 ARITHMETIC : ADD OPERATION
ADD Rd, Rd, Rm ; Rd = Rd + Rm
Examples 2:
What are the result of ADDS R1, R1, R3, if R1 and R3 contain 0x1A2B3C4D and 0x03000030?
Instruction Data Calculation Answer
ADDS R1, R1, R3 R1 = 0x1A2B3C4D 1A2B3C4D + 03000030 R1 = 0x1D2B3C7D
R3 = 0x03000030 = 1D2B3C7D in Hex
APSR
Z=? N=? C=? V=?

Examples 3: ADD Rd, #immed ; Rd = Rd + #immed

What are the difference of ADDS R1, #0xFF and ADDS R2, #100 when R1 and R2 contain 0xFFFFFF01 and 0x7FFFFFAA?
Instruction Data Calculation Answer
ADDS R1, #0xFF R1 = 0xFFFFFF01 0xFFFFFF01 R1 = 0x00000000
+ FF APSR
1 00000000 in Hex Z= N=
C= V=
ADDS R2, #100 R2 = 0x7FFFFFAA 100 dec  hex 64 R2 = 0x8000000E
0x7FFFFFAA APSR
+ 64 Z= N=
8000000E C= V=
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4.2.3 ARITHMETIC : ADD OPERATION ADD Rd, Rn, # immed ; Rd = Rn + #immed

Examples 4:
What are the results of ADDS R1, R2, # 99, if R2 contains 0xEEFFEEFF?
Instruction Data Calculation Answer
ADDS R1, R2, # 99 R2 = 0xEEFFEEFF 99 dec  hex 63 R2 = 0xEEFFEF62
0xEEFFEEFF APSR
+ 63 Z= N=
EEFFEF62 in Hex C= V=

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4.2.3 ARITHMETIC : ADD OPERATION with carry
Examples 5: What are the results of : ADC Rd, Rd, Rm ; Rd = Rd + Rm + carry
LDR R1, =0xFFFFFF01
LDR R2, =0xEEFFEEFF
MOVS R3, #0x11
ADDS R1, R1, R2
ADCS R2, R2, R3
Instruction Data Calculation Answer
LDR R1, =0xFFFFFF01 R1 =0xFFFFFF01 R1 =0xFFFFFF01
LDR R2, =0xEEFFEEFF R2 =0xEEFFEEFF R2 =0xEEFFEEFF
MOVS R3, #0x11 R3 =0x00000011 R3 =0x00000011
ADDS R1, R1, R2 R1 =0xFFFFFF01 0xFFFFFF01 R1 = 0xEEFFEE00
R2 = 0xEEFFEEFF + 0xEEFFEEFF APSR
EEFFEE00 in Hex Z = N = C= 1 V=
ADCS R2, R2, R3 R2 = 0xEEFFEEFF 0xEEFFEEFF R2 = 0xEEFFEF11
R3 =0x00000011 + 0x00000011 APSR
+ 1 (carry) Z = N = C= 0 V=
EEFFEF11 in Hex

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4.2.3 ARITHMETIC : SUB OPERATION
SUB Rd, Rn, Rm ; Rd = Rn − Rm
Examples 6:
If R2 and R3 contain 0x82059910 and 0x78048909, respectively, what are the results of SUBS R1, R2, R3?
Instruction Data Calculation Answer
SUBS R1, R2, R3 R2 = 0x82059910 R1 = R2 – R3 R1 = 0x0A011007
R3 = 0x78048909 0x82059910 APSR
- 0x78048909 Z= N=
0A011007 in Hex C= V=

Examples 7: SUB Rd, #immed ; Rd = Rd − #immed

What are the results of SUBS R3,#136 if R3 contain 0x80000056?
Instruction Data Calculation Answer
SUBS R3, #136 R3 = 0x80000056 R3 = R3 - #136 R1 = 0x7FFFFFCE
136 dec  0x80000056 APSR
- Z= N=
C= V=
SUBS R3, #256 R3 = 0x80000056 ERROR : Immediate data range must be 8 bit
256 dec 

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4.2.3 ARITHMETIC : SUB OPERATION
SUB Rd, Rn,#immed ; Rd = Rn − #immed
Examples 8:
What are the results of SUBS R5, R6, # 255, if R6 contains 0xAABBCCDD?

Instruction Data Calculation Answer

SUBS R5, R6, # 7 R6 = 0xAABBCCDD R5 = R6 - #7 = 0xAABBCCD6 R5 =0xAABBCCD6
APSR
Z= N=
C= V=
SUBS R5, R6, # 8 R6 = 0xAABBCCDD ERROR : Immediate Data range must be 3 bit

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4.2.3 ARITHMETIC : MUL OPERATION
MUL Rd, Rm ; Rd = Rd * Rm
Examples 9:
MULS R4, R5, R4 ; R4 = 0xFFFFFFF0 (-16) , R5 = 0xFFFFFFF6 (-10)
; R4 = R5*R5 = (-10)*(-16) =160 = 0x000000A0

Examples 10:
MULS R4, R5, R4 ;R4=0x0000000A, R5=0x00000064
;R5=R5*R4=10*100=1000=0x000003E8

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4.2.4 LOGICAL

Bit-wise logical operations, all condition code except X affected

Operation Instruction Operation Instruction

Bitwise AND ANDS Rd, Rd, Rn ; Rd = Rd & Rn Bitwise Move MVNS Rd, Rm
0 0 0 NOT 0 1
0 1 0 1 0
1 0 0
1 1 1 Bitwise EORS Rd, Rd, Rn ; Rd = Rd ^ Rn
Exclusive OR
Bitwise OR ORRS Rd, Rd, Rn ; Rd = Rd | Rn 0 0 0
0 1 1
0 0 0
1 0 1
0 1 1
1 1 0
1 0 1
1 1 1

Bit clear BICS Rd, Rd, Rn ; Rd = Rd & (~Rn)

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4.2.4 LOGICAL

Examples 11: Based on the instructions below, determine the results

LDR R1, =0x3795AC5F
LDR R2, =0xB6D34B9D
LDR R3, =0x456789AB
LDR R4, =0xCDEF1234
ANDS R1, R1, R2
ORRS R2, R2, R3
BICS R3, R3, R4
MVNS R4, R4
EORS R1, R1, R3

AND INSTRUCTION
R1 = 0x3795AC5F (0011 0111 1001 0101 1010 1100 0101 1111)
R2 = 0xB6D34B9D (1011 0110 1101 0011 0100 1011 1001 1101)

ANDS R1, R1, R2 ; ANS = R1=0x3691081D 0x3795AC5F 0011 0111 1001 0101 1010 1100 0101 1111
0xB6D34B9D 1011 0110 1101 0011 0100 1011 1001 1101
AND 0011 0110 1001 0001 0000 1000 0001 1101
3 6 9 1 0 8 1 D

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4.2.4 LOGICAL
OR INSTRUCTION
R2 = 0xB6D34B9D (1011 0110 1101 0011 0100 1011 1001 1101)
R3 = 0x456789AB (0100 0101 0110 0111 1000 1001 1010 1011)
0xB6D34B9D 1011 0110 1101 0011 0100 1011 1001 1101
0x456789AB 0100 0101 0110 0111 1000 1001 1010 1011
ORRS R2, R2, R3 ; ANS = R1=0xF7F7CBBF
OR 1111 0111 1111 0111 1100 1011 1011 1111
F 7 F 7 C B B F
BIT CLEAR INSTRUCTION (Rd = Rd & (~Rn))
R3 = 0x456789AB (0100 0101 0110 0111 1000 1001 1010 1011)
R4 = 0xCDEF1234 (1100 1101 1110 1111 0001 0010 0011 0100)
BICS R3, R3, R4 ; ANS = R1=0x0000898B
0x456789AB 0100 0101 0110 0111 1000 1001 1010 1011
0xCDEF1234 1100 1101 1110 1111 0001 0010 0011 0100
~(0xCDEF1234) 0011 0010 0001 0000 1110 1101 1100 1011
AND 0000 0000 0000 0000 1000 1001 1000 1011
0 0 0 0 8 9 8 B
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4.2.4 LOGICAL

MOVE NOT INSTRUCTION

R4 = 0xCDEF1234 (1100 1101 1110 1111 0001 0010 0011 0100)
0xCDEF1234 1100 1101 1110 1111 0001 0010 0011 0100
MVNS R4, R4 ; ANS = R1=0x3210EDCB NOT 0011 0010 0001 0000 1110 1101 1100 1011
3 2 1 0 E D C B

EOR INSTRUCTION
R1 = 0x3691081D (0011 0110 1001 0001 0000 1000 0001 1101)
R3 = 0x0000898B (0000 0000 0000 0000 1000 1001 1000 1011)
0x3691081D 0011 0110 1001 0001 0000 1000 0001 1101
0x0000898B 0000 0000 0000 0000 1000 1001 1000 1011
EORS R1, R1, R3 ; ANS = R1=0x36918196
E-OR 0011 0110 1001 0001 1000 0001 1001 0110
3 6 9 1 8 1 9 6

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4.2.4 LOGICAL

Try It Yourself
Based on the instructions below, determine the results

START
LDR R1, =0x2375A2B4
LDR R2, =0xC9D8E735
LDR R3, =0x87A21083
LDR R4, =0xFE459001
ANDS R1, R1, R2 ; 0x0150A234
ORRS R2, R2, R3 ; 0xCFFAF7B7
BICS R3, R3, R4 ; 0x01A20082
MVNS R4, R4 ; 0x01BA6FFE
EORS R1, R1, R3 ; 0x00F2A2B6
B START
END

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4.2.6 SHIFT AND ROTATE

 Shift/rotate can be in both directions: left, right

 The operand to be shifted/rotated must be a data register
Operation Instruction
Logical shift left LSLS Rd, Rn,#immed ; Rd = Rn « immed
LSLS Rd, Rn ; Rd = Rd « Rn

Logical shift right LSRS Rd, Rn,#immed ; Rd = Rn » immed

LSRS Rd, Rn ; Rd = Rd » Rn

Arithmetic shift ASRS Rd, Rn,#immed ; Rd = Rn » immed

right ASRS Rd, Rn ; Rd = Rd » Rn

Rotate right RORS Rd, Rd, Rn ; Rd rot by Rn

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4.2.6 SHIFT AND ROTATE

Examples 1: R0=0x4375A2B4

LSLS R1, R0, #1 / LSLS R2, R0, #2

Solution :
Before R0=0x2375A2B4
After R1 = 0x86EB4568 / After R2 = 0x0DD68AD0

0x2375A2B4 0100 0011 0111 0101 1010 0010 1011 0100

After 1st 1000 0110 1110 1011 0100 0101 0110 1000
SHIFT
Zero will
MSB set to C 8 6 E B 4 5 6 8 enter
After 2nd 0000 1101 1101 0110 1000 1010 1101 0000
SHIFT
MSB set to C 0 D D 6 8 A D 0

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4.2.6 SHIFT AND ROTATE

Examples 2: R0=0x8375A2B7

LSRS R1, R0, #1 / LSRS R2, R0, #2

Solution :
Before R0=0x8375A2B4
After R1 = 0x41BAD15B / After R2 = 0x20DD68AD

0x8375A2B4 1000 0011 0111 0101 1010 0010 1011 0111

After 1st 0100 0001 1011 1010 1101 0001 0101 1011
SHIFT
MSB set
Zero will enter 4 1 B A D 1 5 B to C
After 2nd 0010 0000 1101 1101 0110 1001 1010 1101
SHIFT
Zero will enter 2 0 D D 6 8 A D

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4.2.6 SHIFT AND ROTATE

Examples 3: R0=0x8375A2B7

ASRS R1, R0, #1 / ASRS R2, R0, #2

Solution :
Before R0=0x8375A2B4
After R1 = 0xC1BAD15B / After R2 = 0xE0DD68AD

0x8375A2B4 1000 0011 0111 0101 1010 0010 1011 0111

After 1st 1100 0001 1011 1010 1101 0001 0101 1011
SHIFT
MSB remains C 1 B A D 1 5 B MSB set
there to C
After 2nd 1110 0000 1101 1101 0110 1001 1010 1101
SHIFT
MSB remains E 0 D D 6 8 A D
there
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4.2.6 SHIFT AND ROTATE
Examples 4 :
LDR R0, =0x8375A2B7
MOVS R1, #1
RORS R0, R0, R1
RORS R0, R0, R1
Solution :
Before R0=0x8375A2B4
After R0 = 0xC1BAD15B / After R0 = 0xE0DD68AD

0x8375A2B4 1000 0011 0111 0101 1010 0010 1011 0111

After 1st 1100 0001 1011 1010 1101 0001 0101 1011
SHIFT
MSB remains MSB set
C 1 B A D 1 5 B
there to C

After 2nd 1110 0000 1101 1101 0110 1001 1010 1101
SHIFT
MSB remains E 0 D D 6 8 A D
there
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4.2.6 SHIFT AND ROTATE

Try It Yourself
EXERCISES 1:
Obtain the answer for each instruction. Calculate using theory and compare the answers with Kiel µ5.

START
LDR R0, =0xAAAAAAAA
LDR R1, =0xAAAAAAAA
LDR R2, =0xAAAAAAAA
LDR R3, =0xBBBBBBBB
LDR R4, =0xBBBBBBBB
LDR R5, =0xBBBBBBBB
LSLS R0, R0, #1 ; 0x55555554, C=1
LSLS R1, R1, #2 ; 0xAAAAAAA8, N=1
LSLS R2, R2, #3 ; 0x55555550, C=1
LSRS R3, R3, #1 ; 0x5DDDDDDD, C=1
LSRS R4, R4, #2 ; 0x2EEEEEEE, C=1
LSRS R5, R5, #3 ; 0x17777777
B START
END

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4.2.6 SHIFT AND ROTATE

Try It Yourself
EXERCISES 2:
Obtain the answer for each instruction. Calculate using theory and compare the answers with Kiel µ5.

START
LDR R0, =0xCCCCCCCC
LDR R1, =0xCCCCCCCC
LDR R2, =0xCCCCCCCC
LDR R3, =0xDDDDDDDD
LDR R4, =0xDDDDDDDD
MOVS R5, #1
MOVS R6, #2
ASRS R0, R0, #1 ; 0xE6666666, N=1
ASRS R1, R1, #2 ; 0xF3333333, N=1
ASRS R2, R2, #3 ; 0xF9999999, N=1, C=1
RORS R3, R3, R5 ; 0xEEEEEEEE, N=1, C=1
RORS R4, R4, R6 ; 0x77777777
B START
END

Prepared by : Siti Munaliza binti Moharad ~JKE_PSIS

4.1.4 REVERSE DATA BYTES

 These instructions are usually used for conversion between little endian and big endian data.
Examples 1 : 0x3795AC5F 37 95 AC 5F
R1 = 0x3795AC5F
REV R0, R1 ; ANS = R0=5FAC9537 REV 5F AC 95 37

Examples 2 : 0xB6D34B9D B6 D3 4B 9D

R2 = 0xB6D34B9D
REV16 R4, R2 ; ANS = R4= 0xD3B69D4B REV16 D3 B6 9D 4B

0x456789AB 45 67 89 AB
Examples 3 :
R3 = 0x456789AB / R3 = 0xA0A0AA55
REVSH FF FF AB 89
REVSH R5, R3 ; ANS = R5= 0xFFFFAB89 Sign extend to 11111111 11111111 10101011
; ANS = R5= 0x000055AA 32 bit
Prepared by : Siti Munaliza binti Moharad ~JKE_PSIS
C4

DEC 30043
MICROPROCESSOR FUNDAMENTALS

END OF CHAPTER 4

Prepared by : Siti Munaliza binti Moharad ~JKE_PSIS