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Data Sheet
Ultra-Low Power, Integrated ISM Band
Sub-GHz Transceiver
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
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• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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ISBN: 978-1-60932-269-4
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
32-Pin QFN
TEST4
TEST3
DVRS
PARS
AVRS
NC(2)
RFIO
VDD
32 31 30 29 28 27 26 25
TEST5 1 24 TEST2
33 GND(1)
TEST1 2 23 PLOCK
VCORS 3 22 IRQ1
VCOTN 4 21 IRQ0
MRF89XA
VCOTP 5 20 DATA
PLLN 6 19 CLKOUT
PLLP 7 18 SCK
TEST6 8 17 SDI
9 10 11 12 13 14 15 16
CSDAT
SDO
TEST7
TEST0
TEST8
OSC1
OSC2
CSCON
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
MRF89XA
OOK
RSSI
Demodulator X SPI
Reception Block
Digital
Demodulator
I X DATA
First Second
Stage Stage Filtering/ FSK
LNA IF Gain Amplification
Mixers Mixers Q Demodulator
X IRQ1
Preliminary
Sync Word
Control
LO1 TX LO2 TX Interface
I X IRQ0
I FIFO
First Modulation
Second (DDS, DACs,
PA Stage Stage
Mixers Q Interpolation Filters) Post-demodulator
Mixers Q
LO1 TX
© 2010 Microchip Technology Inc.
x x x x x x
Supply Crystal Loop Filter
FIGURE 1-2: MRF89XA TO MICROCONTROLLER INTERFACE (NODE) BLOCK DIAGRAM
© 2010 Microchip Technology Inc.
Loop Tank
Filter Circuit
Block Block
DATA I/O
Power
Memory PLOCK I/O
Management
CLKOUT OSC1
MRF89XA
Crystal Frequency = 12.8 MHz
DS70622B-page 9
Note: The interface between the MRF89XA and the MCU depends on the Data mode of operation. For more information refer to Section 3.8 “Data
Processing”.
MRF89XA
NOTES:
PARS I Waveform
LO2 TX Generator
PA Q
I
RFIO LO1 TX
Q
I
LO2 TX
Q
RSSI
OOK IRQ0
Demod
IRQ1
BitSync SDI
LNA
Control SDO
FSK
LO2 RX SCK
Demod
CSCON
LO1 RX CSDAT
CLKOUT
LO1 RX DATA
I LO2 RX TEST<8:0>
OSC1 Q
XO Frequency Synthesizer PLOCK
OSC2 LO
Generator
I
LO1 TX
Q
I
LO2 TX
Q
PLLP
PLLN
VCORS
VCOTN
VCOTP
DVRS
AVRS
VBAT 1 µF
Y5V VDD – Pin 26
2.1 – 3.6V
External Supply
Internal Regulator
1.4 V
VINTS
LNA
MRF89XA
÷75 * (Pi + 1) + Si
LO
PFD
XO ÷(Ri + 1)
Vtune
FCOMP
VCORS
2.5.1 REFERENCE OSCILLATOR PINS An external reference input, such as an oscillator, can
(OSC1/OSC2) be connected as a reference source. The oscillator can
be connected through a 0.01 µF capacitor if required.
The MRF89XA has an internal, integrated oscillator
circuit and the OSC1 and OSC2 pins are used to Choosing a higher tolerance crystal results in a lower
connect to an external crystal resonator. The crystal TX to RX frequency offset and the ability to select a
oscillator provides the reference frequency for the PLL. smaller deviation in baseband bandwidth. Therefore,
The crystal oscillator circuit, with the required loading the recommended crystal accuracy should be ≤40 ppm.
capacitors, provides a 12.8 MHz reference signal for The guidelines for selecting the appropriate crystal with
the PLL. The PLL then generates the local oscillator specifications are explained in Section 4.6 “Crystal
frequency. It is possible to “pull” the crystal to the Specification and Selection Guidelines”.
accurate frequency by changing the load capacitor Note: Crystal frequency error will directly trans-
value. The crystal oscillator load capacitance is late to carrier frequency (Frf), bit rate and
typically 15 pF, which allows the crystal oscillator circuit frequency deviation error.
to accept a wide range of crystals.
LO1 RX
Receiver
I LOs
÷8 LO2 RX
90º Q
LO
VCO Output
I
LO1 TX
90º Q
Transmitter
LOs
I
÷8 LO2 TX
90º Q
CSCON Input Input Input Input Input CSCON has priority over CSDAT.
CSDAT Input Input Input Input Input
SDO Input Input Input Input Input Output only if CSCON or CSDAT = 0.
SDI Input Input Input Input Input
SCK Input Input Input Input Input
(1) Output(1)
IRQ0 High-Z Output Output Output
(1) Output(1)
IRQ1 High-Z Output Output Output
DATA Input Input Input Output Input
CLKOUT High-Z Output Output Output Output
PLOCK High-Z Output(2) Output(2) Output(2) Output(2)
Note 1: High-Z if Continuous mode is activated; otherwise, Output.
2: Output if PLL_lock_en = 1; otherwise, High-Z.
3: Valid logic states must be applied to inputs at all times to avoid unwanted leakage currents.
Second First
Amplification up-conversion up-conversion Interpolation
DACs DDS
filters
Data
I Waveform
LO2 TX Generator
Q
Clock
I
RFIO PA LO1 TX
Q
I
LO2 TX
Q
RF IF Baseband
1
Fdev
I(t)
Q(t)
LO1 RX
LO2
RX First
Second down-conversion
down-conversion
0
IF2 = 0 IF1 Image LO1 RX Channel Frequency
in FSK mode Approx. 100 MHz Frequency
First
Second down-conversion
down-conversion
2.11 Serial Peripheral Interface (SPI) The SPI in the MRF89XA consists of the following two
sub-blocks, as illustrated in Figure 2-11:
The MRF89XA communicates with the host
microcontroller through a 4-wire SPI port as a slave • SPI CONFIG: This sub-block is used in all data
device. An SPI-compatible serial interface allows the operation modes to read and write the configuration
user to select, command and monitor the status of the registers which control all the parameters of the chip
MRF89XA through the host microcontroller. All (operating mode, frequency and bit rate).
registers are addressed through specific addresses to • SPI DATA: This sub-block is used in Buffered and
control, configure and read status bytes. Packet mode to write and read data bytes to and
from the FIFO. (FIFO Interrupts can be used to
manage the FIFO content).
CSCON
I/O
SPI SDI
Configuration
Config. SDI
Registers CONFIG SDO
(Slave) SDO
SCK
SCK
I/O
PIC® Microcontroller
(Master)
SPI
FIFO DATA
(Slave)
CSDAT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CSCON (In)
SCK (In)
New value at
address A1
SDI (In) start rw A(4) A(3) A(2) A(1) A(0) stop D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0)
Current value at
Address = A1 address A1*
SDO (Out) HZ x x x x x x x x D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) HZ
(input) (input)
* when writing the new value at address A1, the current content of A1 can be read by the µC.
(In)/(Out) refers to MRF89XA side
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CSCON (In)
SCK (In)
Current value at
Address = A1 address A1
SDO (Out) HZ x x x x x x x x D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) HZ
(input) (input)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
CSDAT (In)
SCK (In)
SDI (In) D1(7) D1(6) D1(5) D1(4) D1(3)D1(2) D1(1) D1(0) D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0)
x
SDO (Out)HZ x x x x x x x x HZ x x x x x x x x x HZ
(input) (input) (input)
CSDAT (In)
SCK (In)
SDI (In) x x x x x x x x x x x x x x x x x
SDO (Out)HZ D1(7) D1(6) D1(5) D1(4) D1(3) D1(2) D1(1) D1(0) HZ D2(7) D2(6) D2(5) D2(4) D2(3) D2(2) D2(1) D2(0) HZ
(input) (input) (input)
FIFO
Byte 1
Byte 0
8
Data TX/RX
SR (8 bits)
1
MSB LSB
0x00
0x00
Transmit/Receive
Control Registers FIFO 64 bytes
0x1F
0x40
Data TX/RX
SHIFT REGISTER
1 (8 bits)
MSB
Note 1: The combination of DMODE1:DMODE0 selects the data operation mode. See Table 2-7 for the available
data operation mode settings.
R1CVAL is activated if RPS = 0 in GCONREG. Also default values R1, P1 and S1 generate 915 MHz
in FSK Mode.
P1CVAL is activated if RPS = 0 in GCONREG. Also default values R1, P1 and S1 generate 915 MHz
in FSK Mode.
S1CVAL is activated if RPS = 0 in GCONREG. Also default values R1, P1 and S1 generate 915 MHz
in FSK Mode.
R2CVAL is activated if RPS = 1 in GCONREG. Also default values R2, P2 and S2 generate 920 MHz
in FSK Mode.
Note 1: Setting this bit to ‘0’ disables the RSSI IRQ source. It can be left enabled at any time, and the user can
choose to map this interrupt to IRQ0/IRQ1 or not.
Note 1: Setting this bit to ‘0’ disables the RSSI IRQ source. It can be left enabled at any time, and the user can
choose to map this interrupt to IRQ0/IRQ1 or not.
Where,
BUTFILV is the value in the register
fc is the center frequency
fo is the local oscillator frequency
fxtal is the crystal oscillator frequency
Note: fc – fo = 100 kHz only when fxtal = 12.8 MHz.
Where,
POLCFV is the value in the register
fc is the center frequency
fo is the local oscillator frequency
fxtal is the crystal oscillator frequency
bit 3-0 Reserved<3:0>: Reserved bits; do not use
1000 = Reserved (default)
bit 7-4 TXIPOLFV<3:0>: Transmission Interpolation Filter Cut Off Frequency Value bits
These bits control the cut off frequency of the interpolation filter in the transmission path.
TXIPOLFV<3:0> = 0111 Î fc = 200 kHz (default)
Where,
TXIPOLFV is the value in the register
fc is the center frequency
fo is the local oscillator frequency
fxtal is the crystal oscillator frequency
bit 3-1 TXOPVAL<2:0>: Transmit Output Power Value bits
111 = 13 dBm
110 = 10 dBm (default)
101 = 7 dBm
100 = 4 dBm
011 = 1 dBm
010 = -2 dBm
001 = -5 dBm
000 = -8 dBm
bit 0 Reserved: Reserved bit; do not use
0 = Reserved (default)
Note: BR is the bit rate (refer to BRSREG (Register 2-4) for more information).
MRF89XA
Register
Function/ Register Value on
Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Parameter Address POR
Type
General 0x00 GCONREG CMOD<2:0> FBS<1:0> VCOT<1:0> RPS 0x28
0x01 DMODREG MODSEL<1L0> DMODE0 OOKTYP<1:0> DMODE1 IFGAIN<1:0> 0x88
0x02 FDEVREG FDVAL<7:0> 0x03
0x03 BRSREG Reserved BRVAL<6:0> 0x07
0x04 FLTHREG FTOVAL<7:0> 0x0C
0x05 FIFOCREG FSIZE<1:0> FTINT<5:0> 0x0F
0x06 R1CREG R1CVAL<7:0> 0x77
0x07 P1CREG P1CVAL<7:0> 0x64
0x08 S1CREG S1CVAL<7:0> 0x32
0x09 R2CREG R2CVAL<7:0> 0x74
0x0A P2CREG P2CVAL<7:0> 0x62
0x0B S2CREG S2CVAL<7:0> 0x32
Preliminary
0x0C PACREG Reserved Reserved Reserved PARC<1:0> Reserved Reserved Reserved 0x38
0x0D FTXRXIREG IRQ0RXS<1:0> IRQ1RXS<1:0> IRQ1TX FIFOFULL FIFOEMPTY FOVRRUN 0x00
Interrupt 0x0E FTPRIREG FIFOFM FIFOFSC TXDONE IRQ0TXST Reserved RIRQS LSTSPLL LENPLL 0x01
0x0F RSTHIREG RTIVAL<7:0> 0x00
0x10 FILCREG PASFILV<3:0> BUTFILV<3:0> 0xA3
Receiver 0x11 PFCREG POLCFV<3:0> Reserved Reserved Reserved Reserved 0x38
0x12 SYNCREG POLFILEN BSYNCEN SYNCREN SYNCWSZ<1:0> SYNCTEN<1:0> Reserved 0x18
0x13 RESVREG Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x07
0x14 RSTSREG RSSIVAL<7:0> Read-only
0x15 OOKCREG OOKTHSV<2:0> OOKTHPV<2:0> OOKATHC<1:0> 0x00
SYNC Word 0x16 SYNCV31REG SYNCV<31:24> 0x00
© 2010 Microchip Technology Inc.
PARS I Waveform
LO2 TX Generator
PA Q
I
RFIO LO1 TX
Q
I
LO2 TX
Q
RSSI
OOK
IRQ0
Demod
IRQ1
BitSync SDI
LNA
Control SDO
FSK
LO2 RX SCK
Demod
CSCON
LO1 RX CSDAT
CLKOUT
DATA
TEST<8:0>
LO1 RX
I LO2 RX PLOCK
OSC1 Q
XO Frequency Synthesizer
OSC2 LO
Generator
I
LO1 TX
Q
I
LO2 TX
Q
PLLP
PLLN
VCORS
VCOTN
VCOTP
DVRS
AVRS
VDD
Pin 13
Undefined
(output)
Wait for Chip is ready from this point forward
10 ms
VDD
Wait for Chip is ready from this point forward
> 100 µs
5 ms
Pin 13
High-Z 1 High-Z
(input)
EQUATION 3-5:
f xtal
f dev = --------------------------------------------------------------------------
-
32 • [ 1 + val ( FDVAL<7:0> ) ]
EQUATION 3-6:
f dev
β = 2 • --------- ≥ 2
BR
DATA
PARS
95% 95%
[V]
tPARS tPARS
PA Output
Power 60 dB 60 dB
tPA_OUT tPA_OUT
EQUATION 3-8:
3 • fc ≤BW passive,filter ≤4 • f c
ButterFilter ButterFilter
-f C 0 fC f requency
Canceled side of
the polyphase filter
-f o 0 f requency
-f C
FSK mode: The 99% energy bandwidth of an FSK The choice of fc should be such that the modulated
modulated signal is approximated, as shown in signal falls in the filter bandwidth, anticipating the Local
Equation 3-9. Oscillator frequency drift over the operating
temperature and aging of the device as shown in
EQUATION 3-9: :Equation 3-10
EQUATION 3-10:
BW 99%,fsk = 2 • f dev + BR
-------
2
2 • f c > BW 99%,fsk + LO drifts
EQUATION 3-12:
400
350
FC (3dB Cut-off) [kHz]
300
250
200
150
100
50
0
0 2 4 6 8 10 12 14 16
Val BUTFILV<3:0> [d]
Actual Theoretical
Polyphase Filter's BW, OOK
BW BW
450
400
350
fc- fo with fc = 100 kHz [kHz]
300
250
200
150
100
50
0
0 2 4 6 8 10 12 14 16
Val BUTFILV<3:0> [d]
POLCFV<3:0> = 0011
160
140
RSSI Value (RSSIVAL<7:0>) [0.5dB/bit]
120
100
80
60
40
20
0
-120 -100 -80 -60 -40 -20 0
Pin [dBm]
3.4.7.4 RSSI IRQ Source An interrupt can be mapped to the IRQ0 or IRQ1 pins
through the IRQ0RXS<1:0> and IRQ1RXS<1:0> bits
The MRF89XA can be used to detect a RSSI level
(FTXRXIREG<7:6> and FTXRXIREG<5:4>).
above a preconfigured threshold. The threshold is set
Figure 3-10 illustrates the timing diagram of the RSSI
using RTIVAL<7:0> bits (RSTHIREG<7:0>) and the
interrupt source, with the RTIVAL<7:0> bits
IRQ status stored in the RIRQS bit (FTPRIREG<2>),
(RSTHIREG<7:0>) set to ‘11100’.
which is cleared by writing a ‘1’.
RSSIVAL<7:0> 24 26 27 30 25 20 20 20 18 22 33 20 22 34 33
RIRQS
Clear interrupt
RSSI
(dB)
''Peak -6 dB'' Threshold
Noise floor of
receiver
Time
Zoom
Decay in dB as defined in
OOKTHSV<2;0> Fixed 6dB difference
Period as defined in
OOKTHPV<2:0>
Increment
FTOVAL<7:0>
Yes
Glitch activity
on DATA ?
No
Optimization complete
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output
To DATA pin and
DCLK in
Continuous mode
DCLK
IRQ1
The BitSync can be disabled by setting the BSYNCEN that the BitSync can withstand. It can be esti-
bit (SYNCREG<6>) to ‘1’ and by holding the IRQ1 pin mated as given in Equation 3-17.
(pin 22) low. However, for optimum receiver perfor-
mance, it has to be used when the device is running in EQUATION 3-17:
Continuous mode. With this option a DCLK signal is
present on the IRQ1 pin. 1 BR
NumberOfBits = --- • -----------
The BitSync is automatically activated in Buffered and 2 ΔBR
Packet modes. The bit synchronizer bit-rate is con-
trolled by the BRVAL<6:0> bits (BRSREG<6:0>). For a
given bit rate, this parameter is determined by This implies approximately six consecutive unbalanced
Equation 3-16. bytes when the Bit Rate precision is 1%, which is easily
achievable (crystal tolerance is or should be at least in
EQUATION 3-16: the range of 50 to 100 ppm).
The registers associated with Receive mode are: 3.6.2 INTERRUPT SOURCES AND FLAGS
• GCONREG (Register 2-1) The MRF89XA generates an interrupt request for the
• DMODREG (Register 2-2) host microcontroller by pulling the IRQ0 or IRQ1 pins
• FDEVREG (Register 2-3) low or high based on the events and configuration set-
• BRSREG (Register 2-4) tings of these interrupts. All interrupt sources and flags
are configured through the Interrupt Configuration reg-
• FLTHREG (Register 2-5)
isters, based on the occurrence of the following events:
• FIFOCREG (Register 2-6)
• Interrupt Requests (IRQ0 and IRQ1) during differ-
• FTXRXIREG (Register 2-14)
ent receive stand-by data modes (such as Contin-
• FTPRIREG (Register 2-14) uous, Buffer and Packet) for following event
• RSTHIREG (Register 2-16) occurrences: SYNC, RSSI, PLREADY, ARDS-
• FILCREG (Register 2-17) MATCH and /FIFOEMPTY.
• PFCREG (Register 2-18) For example, Write Byte. The WRITEBYTE inter-
• SYNCREG (Register 2-19) rupt source goes high for one bit period each time
• RSTSREG (Register 2-21) a new byte is transferred from the shift register to
the FIFO (that is, each time a new byte is
• OOKCREG (Register 2-22)
received).
• SYNCV31REG (Register 2-23)
• Interrupt Requests (IRQ0 and IRQ1) during trans-
• SYNCV23REG (Register 2-24)
mit modes (such as Continuous, Buffer and
• SYNCV15REG (Register 2-25) Packet) for the following event occurrences: Data
• SYNCV07REG (Register 2-26) Clock, FIFOFULL, Transmit Done, Transmit Start
with IRQ0 and IRQ1.
For example, TX Done. The TXDONE interrupt
source goes high when the FIFO is empty and the
Shift register’s last bit has been sent to the modu-
lator (that is, the last bit of the packet has been
sent). One bit period delay is required after the ris-
ing edge of TXDONE to ensure correct RF trans-
mission of the last bit. In practice this may not
require special care in the MCU software due to
IRQ processing time.
RX DATA
Bit N-x = Bit N-1 = Bit N =
(NRZ)
SSYNCVAL<x> SYNCVAL<0> SYNCVAL<0>
DCLK
SYNC
TX/RX
MRF89XA
DATA
IRQ0
Control
IRQ1
SPI
Data RX
SYNC
Recognition
CONFIG
Packet FIFO
Handler (+SR)
CSDAT
TX
SCK
DATA
SDI
SDO
TX/RX MRF89XA
DATA
IRQ0
Control
IRQ1 (DCLK)
Data RX SPI
SYNC
CSCON
Recognition
CONFIG
SCK
SDI
SDO
Datapath
T_DATA T_DATA
DATA (NRZ)
DCLK
DATA (NRZ)
DCLK
MRF89XA
IRQ0
Control
IRQ1
SPI
Data RX
SYNC CSCON
Recognition
CONFIG
FIFO
(+SR)
CSDAT
TX
DATA SCK
SDI
SDO
Datapath
15 b15
b14
b13
b12
b11
b10
b9
FIFO b8
b7
b6
b5
b4
b3
b2
b1
0 b0
Data TX
(from SR) XXX b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 XXX
Start condition
(FIFOFM)
FIFOEMPTY
FIFOFULL
FOVRRUN
WRITEBYTE
15 b15
b14
b13
b12
b11
b10
b9
FIFO b8
b7
b6
b5
b4
b3
b2
b1
0 b0
MRF89XA
IRQ0
CONTROL
IRQ1
SPI
Data RX SYNC
RECOG. /CSCON
CONFIG
PACKET FIFO
HANDLER (+SR)
CSDAT
TX
DATA SCK
SDI
SDO
Datapath
Payload/FIFO
Payload/FIFO
X 15 X 14 X 13 X 12 X 11 X5 X4 X0
*** ***
X8 X7 X6 X5 X4 X3 X2 X1 X0
Band FL1 C5 C4 L1 L3 L4
R1
C1
0.047 µF
FIGURE 4-1:
1Ω 1%
C2 0.22 µF
ANTENNA
See Table C4 C3 1 µF
L1 L2
C12 1 6 See Table See Table 100 nH
GND GND
2 5
IN OUT
3 4
GND GND
C11 C5
APPLICATION DETAILS
VIN
See
L6 Table C7
R2
33 pF
100 kΩ
5%
trated in Figure 4-1. This application design (that is,
a matching circuit of the SAW filter and antenna is illus-
33 32 31 30 29 28 27 26 25
C8
NC
0.1 µF L3 L4 VDD
RFIO
PARS
DVRS
AVRS
TEST4
TEST3
See See 1 24
TEST5 TEST2
APPLICATION CIRCUIT SCHEMATIC
Table Table 2 23
Preliminary
TEST1 PLOCK PLOCK
3 22
VCORS IRQ1 IRQ1
4 U1 21
VCOTM IRQ0 IRQ0
5 MRF89XA- I/ MQ 20
VCOTP DATA
6 19
PLLM CLKOUT NC
7 18
PLLP SCK SCK
C9 C10 8 17
TEST6 SDI SDI
680 pF 0.01 µF
TEST7
OSC1
OSC2
TEST0
TEST8
CSCON
CSDATA
SDO
R3
9 10 11 12 13 14 15 16
6.8 kΩ
NC
1% SDO
CSDAT
CSCON
X1
Note: Component values for C11, C12, and L6 depend on 12.8 MHz
antenna impedance. 4 3
1 2
DS70622B-page 97
MRF89XA
MRF89XA
4.1 RF Transmitter Matching 4.3 SAW FILTER
The optimum load for the RF port at a given frequency FL1 is a SAW filter. While in Transmitting mode, the
band is listed in Table 4-1. These load values in the SAW filter is used to suppress the harmonics. While in
table are expected by the RF port pins to have as an Receiving mode, the SAW filter is used to reject the
antenna load for maximum power transfer. For all image frequencies and out-of-band interfering signals.
antenna applications, an RF choke inductor (L2) must
be included during transmission because the RF out- 4.3.1 SAW FILTER PLOT
puts are of open-collector type. Figure 4-2 and Figure 4-3 illustrates the plots of the
SAW filter used in the application circuit. The plots
4.2 Antenna Components shown are representative. For exact specifications,
refer to the SAW Filter manufacturer data sheet.
The MRF89XA is single-ended and has an unbalanced
input/output impedance close to 30-j25. Therefore, it
only requires a matching circuit to the SAW filter and
antenna. C11, C12, and L6, L1, C4, and C5 are tuned
to provide that impedance (30+j25) to the RFIO pin
(pin 31). In this case, the transceiver will be able to
transfer all power toward the antenna. This impedance
is called Optimum Load Impedance. L2 is a RF choke
inductor. L3 and L4 are basically VCO inductors. The
details are shown in Figure 4-1.
-10
-20
-30
Attenuation [dB]
-40
-50
-60
-70
-80
400 600 800 1000 1200 1400 1600 1800 2000
Frequency [MHz]
-10
-20
Attenuation [dB]
-30
-40
-50
-60
-70
-80
400 600 800 1000 1200 1400 1600 1800 2000
Frequency [MHz]
Pmax-1dB circle
Max Power
Zopt = 30 + j25Ω
PARS
0.047 µF
100 nH
1Ω 1%
SAW Antenna
port
PA
RFIO
DC block
LNA
TABLE 4-3: MRF89XA APPLICATION SCHEMATIC BILL OF MATERIALS FOR 868 MHz
Designator Value Description Manufacturer
C1 0.047 uF Capacitor, Ceramic, 10V, +/-10%, X7R, SMT 0402 Murata Electronics North America
C2 0.22 uF Capacitor, Ceramic, 16V, +/-10%, X7R, SMT 0402 Murata Electronics North America
C3 1 uF Capacitor, Ceramic, 6.3V, +/-10%, X5R, SMT 0603 Murata Electronics North America
C4 22 pF Capacitor, Ceramic, 50V, +/-5%, UHI-Q NP0, SMT Johanson Technology
0402
C5 1.8 pF Capacitor, Ceramic, 50V, +/-0.1 pF, UHI-Q NP0, Johanson Technology
SMT 0402
C7 33 pF Capacitor, Ceramic, 50V, +/-5%, C0G, SMT 0402 Murata Electronics North America
C8 0.1 uF Capacitor, Ceramic, 16V, +/-10%, C0G, SMT 0402 Murata Electronics North America
C9 680 pF Capacitor, Ceramic, 50V, +/-5%, C0G, SMT 0402 Murata Electronics North America
C10 0.01 uF Capacitor, Ceramic, 16V, +/-10%, X7R, SMT 0402 Murata Electronics North America
C11 4.3 pF Capacitor, Ceramic, 50V, +/-0.1 pF, UHI-Q NP0, Johanson Technology
SMT 0402
C12 1.5 pF Capacitor, Ceramic, 50V, +/-0.1 pF, UHI-Q NP0, Johanson Technology
SMT 0402
FL1 TA0801A SAW Filter EPCOS
L1 8.2 nH Inductor, Ceramic, +/-5%, SMT 0402 Johanson Technology
L2 100 nH Inductor, Ceramic, +/-5%, SMT 0402 Johanson Technology
L3 6.8 nH Inductor, Wirewound, +/-5%, SMT 0402 Johanson Technology
L4 6.8 nH Inductor, Wirewound, +/-5%, SMT 0402 Johanson Technology
L6 10 nH Inductor, Ceramic, +/-5%, SMT 0402 Johanson Technology
R1 1 ohm Resistor, 1%, +/-100 ppm/C, SMT 0402 Vishay/Dale
R2 100K ohm Resistor, 5%, +/-100 ppm/C, SMT 0402 Yageo
R3 6.8K ohm Resistor, 1%, +/-100 ppm/C, SMT 0402 Yageo
R4 0 ohm Resistor, SMT 0402 Yageo
R5 Not Populated
U1 MRF89XA Transceiver Microchip Technology Inc.
X1 12.800 Crystal, +/-10 ppm, 15 pF, ESR 100 ohms, SMT
MHz 5x3.2mm
Signal/Power/RF and
Common Ground
Signal/Power/RF and
Common Ground
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
IDDRX
3.0 mA typ.
IDDFS
1.3 mA typ.
IDDST
65 µA typ.
IDDSL
100 nA typ.
RX
Time MRF89XA can be put in
Any other mode
Wait
TSWRF
Receiver is ready:
- RSSI sampling is valid after a 1/fdev period
- Received data is valid
Wait
TSFS
Set MRF89XA in RX mode
Wait for Receiver settling
Wait
TSOSC
Set MRF89XA in FS mode
Wait for PLL settling
Note 1: If the lock detect indicator is available on an external interrupt pin of the companion microcontroller, it can be used to optimize
TSFS, without having to wait the maximum specified TSFS.
MRF89XA
IDD
IDDT
16 mA typ. @1 dBm
IDDFS
1.3 mA typ.
IDDST
65 µA typ.
IDDSL
100 nA typ.
TX
Time MRF89XA can be put in
Any other mode
Wait
TSTR
Data transmission can start in
Continuous and Buffered
modes
Wait
TSFS
Set MRF89XA in TX mode
Packet mode starts its operation
Wait
TSOSC
Set MRF89XA in FS mode
Wait for PLL settling
Note 1: TSFS time can be improved by using the external lock detector pin as an external interrupt trigger.
IDDFS
1.3 mA typ.
Time
Wait
TSTWF
MRF89XA is now ready
for data transmission
Wait
TS HOP
1. Set R2/P2/S2
2. Set MRF89XA in FS mode, change
Frequency Band Select bits (FBS<1:0>) if needed, then switch
from R1/P1/S1 to R2/P2/S2
MRF89XA is in TX mode
On channel 1 (R1/P1/S1)
MRF89XA
IDD
IDDR
3 mA typ.
IDDFS
1.3 mA typ.
Time
Wait
TSRWF
MRF89XA is now ready
for data reception
Wait
TS HOP
1. Set R2/P2/S2
2. Set MRF89XA in FS mode, change
Frequency Band Select bits (FBS<1:0>), then switch
from R1/P1/S1 to R2/P2/S2
MRF89XA is in RX mode
On channel 1 (R1/P1/S1)
Note: It is also possible to move from one channel to another without having to switch off the receiver. This method
is faster and overall draws more current. For timing information, refer to TSRHOP.
IDDT
16 mA typ. @1 dBm
IDDR
3.0 mA typ.
Time
Wait
TSRWF
MRF89XA is ready
to receive data
Set MRF89XA in
Wait RX mode
TSTWF
Set MRF89XA in
TX mode
MRF89XA is in
RX mode
-90.0 14.0
-92.0 12.0
-94.0 10.0
Sensitivity @ BER=0.1%
-98.0 6.0
-100.0 4.0
-102.0 2.0
-104.0 0.0
-106.0 -2.0
863 864 865 866 867 868 869 870
Frequency [MHz]
-90.0 14.0
-92.0 12.0
-94.0 10.0
Sensitivity [dBm]
-98.0 6.0
-100.0 4.0
-102.0 2.0
-104.0 0.0
-106.0 -2.0
902 904 906 908 910 912 914 916 918 920 922 924 926 928
Frequency [MHz]
Note: Measured in FSK mode only. OOK sensitivity characteristics will be similar. The sensitivity difference along the band remains inside
the ripple performance of the SAW filter (the nominal passband of the 869 MHz SAW filter is 868-870 MHz). The SAW filter ripple
response is referenced to its insertion loss at 869 MHz and 915 MHz for each filter.
6.0
5.0
4.0
Sensitivity Loss [dB]
3.0
2.0
1.0
0.0
-1.0
-25 -20 -15 -10 -5 0 5 10 15 20 25
LO Drift [kHz]
6.0
5.0
4.0
Sensitivity Loss [dB]
3.0
2.0
1.0
0.0
-1.0
-100 -80 -60 -40 -20 0 20 40 60 80 100
LO Drift [kHz]
Note: In FSK mode, the default filter setting (“A3” at address 0x16) is kept, leading to fc = 96 kHz typical. In OOK mode, “F3” is set at address
0x16, leading to (fc – fo) = 95 kHz typical. Both of these settings ensure that the channel filter is wide enough, therefore characterizing
the demodulator response and not the filter response.
0.0
50 100 150 200 250 300
Sensitivity Improvement [dB] =>
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
fc of Active Filter [kHz]
1.0
0.0
0 50 100 150 200 250 300 350
Sensitivity Improvement [dB] =>
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
fc-fo [kHz]
1.5
1.0
Sensitivity Improvement [dB] =>
0.5
0.0
2.10 2.40 2.70 3.00 3.30 3.60 85°C
25°C
-0.5
0°C
-40°C
-1.0
-1.5
-2.0
-2.5
VDD [V]
Note: The sensitivity performance is very stable over the VDD range, and the effect of high temperature is minimal.
8.0
6.0
Sensitivity Improvement [dB] =>
4.0
2.0
0.0
02 5 50 75 100
-2.0
-4.0
-6.0
-8.0
Bit Rate [kbps]
2.0
1.5
Sensitivity Improvement [dB] =>
1.0
0.5
0.0
1.5 4 6.5 9 11.5 14 16.5
-0.5
-1.0
-1.5
-2.0
-2.5
Bit Rate [kbps]
70
60
50
40
ACR [dB]
30
20
10
0
-1000 -800 -600 -400 -200 0 200 400 600 800 1000
Offset [kHz]
50
40
30
ACR [dB]
20
10
0
-300 -200 -100 0 100 200 300
-10
-20
Offset [kHz]
Note: In FSK mode, the unwanted signal is unmodulated (as described in the EN 300-220). Co-channel rejection (CCR, offset = 0 kHz) is
positive due to the DC cancellation process of the zero-IF architecture. In OOK mode, the polyphase filter efficiency is limited, thus
limiting the adjacent channel rejection at 2xFo distance.
10.0 2.0
8.0 0.0
6.0 -2.0
4.0 -4.0
2.0 -6.0
0.0 -8.0
863 864 865 866 867 868 869 870
Frequency [MHz]
10.00 2.0
8.00 0.0
6.00 -2.0
4.00 -4.0
2.00 -6.0
0.00 -8.0
902 904 906 908 910 912 914 916 918 920 922 924 926 928
Frequency [MHz]
Note: As noted inSection 4.3.1 “SAW Filter Plot”, the 869 MHz SAW filter does not cover the entire European 863-870 MHz frequency band
when used in a 50Ω environment. Therefore, the output power degradation at the lowest frequencies. For applications in the 863-860
MHz band, it is recommended that an appropriate SAW filter be implemented or that the SAW response is tuned by external matching.
The SAW filter ripple references are the insertion loss of each SAW at 869 MHz and 915 MHz.
12.0 28.00
26.00
8.0
24.00
4.0 22.00
POUT [dBm]
20.00
0.0
18.00
-4.0 16.00
14.00
-8.0
12.00
-12.0 10.00
01 23 456 7
TX Output Power (TXOPVAL<2:0>) [d]
Pout IDD
2.0 22.0
-12.0 10.0
0123 4567
TX Output Power (TXOPVAL<2:0>) [d]]
Pout IDD
Note: +10 dBm typical. Output power is achievable, evan at SAW filter’s output.
1.0
0.5
POUT Improvement [dB] =>
0.0
2.1 2.4 2.7 3.0 3.3 3.6
85ºC
-0.5 25ºC
-40ºC
0ºC
-1.0
-1.5
-2.0
VDD [V]
Conditions:
• POUT = +10.6dBm
• fdev = +/-200kHz
• BR =100 kbps (Chip rate=100 kCps, as data whitening is enabled)
• Packet mode, data whitening enabled
MRF89XA
Sleep Mode Current Stand-by Mode Current
1200 100
90
1000
80
70
800
Isleep [nA]
Istby [µA]
60
600 50
40
400
30
20
200
10
0 0
2.1 2.4 2.7 3 3.3 3.6 2.1 2.4 2.7 3 3.3 3.6
VDD [V] VDD [V]
FS Mode Current RX Mode Current
2.00 4.00
1.80
3.50
1.60
Preliminary
3.00
1.40
1.20 2.50
Ifs [mA]
Irx [mA]
1.00 2.00
0.80
1.50
0.60
1.00
0.40
0.20 0.50
0.00 0.00
2.1 2.4 2.7 3 3.3 3.6 2.1 2.4 2.7 3 3.3 3.6
VDD [V] TX Mode Current
VDD [V]
(Max Output Power)
30.0
25.0
© 2010 Microchip Technology Inc.
20.0
TXLVL=000
Legend:
Itx [mA]
15.0
85ºC
25ºC
10.0
0ºC
-40ºC
5.0
0.0
2.1 2.4 2.7 3.0 3.3 3.6
VDD [V]
MRF89XA
6.0 PACKAGING INFORMATION
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
01/05/10