International eae zo Rectifier IRF530 HEXFET® Power MOSFET © Dynamic dv/dt Rating ‘* Repetitive Avalanche Rated 7 © 175°C Operating Temperature © Fast Switching © Ease of Paralleling ® Simple Drive Requirements Voss = 100V Ros(on = 0.162 Ip = 14A Description Third Generation HEXFETs from Intemational Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 package is universally preferred for all commercial-industrial applications at power dissipation levels to approximately 50 watts. The low thermal resistance and low package cost of the TO-220 contribute to its wide acceptance throughout the industry. Absolute Maximum Ratings Ser Hee Parameter] Max Units lo@ To=25°C _| Continuous Drain Current, Vos @ 10 V 4 1p @ Ti Continuous Drain Current, Vas @ 10 V 40 a | tow Pulsed Drain Current © [Po @ Tc= 25°C _| Power Dissipation Ww Linear Derating Factor _ Ti Gate -to-Source Voltage v Single Pulse Avalanche Energy ® 69 md alanche C te 14 [A Repetitive Avalanche Energy © 88 md Peak Diode Recovery dvidt 55 Vins Ts ‘Operating Junction and “55 to +175 j Tero Storage Temperature Range °c Soldering Temperature, fr 10 seconds 300 (1.6mm from ease) | Mounting Torque, 6-32 or M3 screw 10 lofein (1.4 Nem) Thermal Resistance _ ____ Parameter Min. Typ. Max. | Units | Rec Junetion-to-Case = = 17 | Recs Case-to-Sink, Flat, Greased Surface = —__|.-o | Rasa Junetion-to-Ambient = 62 | 17IRF530 TGR Electrical Characteristics @ Ty = 25°C (unless otherwise specified) Parameter Min. | Typ. | Max. | Units Test Conditions Vienoss | Drain-1o-Source Breakdown Volage | 100 | — | — | V_|VaseOV, lo= 250uA ‘AVery0s9/AT)| Breakdown Voltage Temp. Coefficient_| — | 0.12| — | VPC | Reference to 25°C, lo= mA Rosie Static Drain-to-Souroe On-Resistance | — | — | 016] @ |Ves=10V, lo-8.4A @ Vesey Gate Threshold Voltage 20 | — | 40 [| V_|Vos-Vos, lo= 250A ‘e Forward Transconductange 51 | — | — | S |Vos=80V, lo=8.4A © ; =[= 7s Vos=100V, Vas=OV Joss Drain-to-Source Leakage Current Se eS a Gate-to-Source Forward Leakage == 100, [ves=20v Gate-to-Source Reverse Leakage = [= [100 Ves=-20V a Total Gate Charge = [= [26 Wo T4A Qos Gate-to-Source Charge == 155] 00 | Vose8ov Qui Gateto-Drain (‘Miller’) Charge — [=r Vos=10V See Fig. 6 and 13 © ton) Tumn-On Delay Time = 0 T= Voo=50V te Rise Time ee ta “Tum-Off Dalay Time. — [es T= Ro=t20. ni Fall Time = [a T= Fiox3.60_See Figure 10@ bo Intemal Drain Inductance —|4a5)— eee ck nH | from package & bs Intema! Source Inductance — |r} and center of die contact i Cis Input Capacitance = | 670 | — Vos=0V Cox ‘Output Capacitance =| 250 =] PF | Voo=25v Cos Reverse Transler Capacitance — [eo [= f=1,0MHz See Figure 5 Source-Drain Ratings and Characteristics Parameter Min. | Typ. | Max. | Units Test Conditions 1s Continuous Source Current Pao ee MOSFET symbol ° (Body Diode) a. | Showing the Tsu Pulsed Source Currant Ee eee ot integral reverse (Body Diode) © pn junction diode. ls Vso. Diode Forward Voltage = [= [25 |_V_ | T28G, Iga14A, Vaso © te Reverse Recovery Time — [150 [280 |ns_|T)=26°C, trata Or Reverse Recovery Charge = [oes [17 [uc |diet=100a/us @ ten Forward Tum-On Time Tntinsic turn-on ime fs neglagiblo (turn-on is dominated by LevLo) Notes: © Repatitve rating: pulse width limited by max. junction temperature (See Figure 11) ® Vpp=25V, starting Ty=25°C, L=528uH Re=250, las=14A (See Figure 12) © Ispst4A, difdt<140A/us, VooA >) ous 7 nt “0 a 2 oN < ; Duly Factor < 0.1% - 4 { Fig 10a. Switching Time Test Circuit é I - £ ‘Ds 1 fee A, | om 6 ! F I 10%. /\ | a as ee 7 To, Case Temperature (°C) on) pena Fig 10b. Switching Time Waveforms TU Pod 1. OUTY FACTOR, Onty/ty 2. PEAK TyePoy X Zense¢ To O48 : 10 ty, Rectangular Pulse Duration (seconds) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-CaseIRF530 TOR] Vary to obtain reauited as 200 nn te 38 = tn Eso 5 2. | ge 2 Fig 12a. Unclamped Inductive Test Circuit 2 fe Verjoss 2 ami 4 “ 3° Nd foo ub MY AE Yoo * 25V Vos 6 2 75s eS Starting T,, Junction Temperature(°C) ks — — — ie Fig 12c. Maximum Avalanche Energy Fig 12b. Unclamped Inductive Waveforms Vs. Drain Current Cunent Regustr Vos aN ee eet coven Sanpng Reesers Fig 13a. Basic Gate Charge Waveform Fig 1b. Gate Charge Test Circuit Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit - See page 1505 Appendix B: Package Outline Mechanical Drawing — See page 1509 Appendix C: Part Marking Information - See page 1516 International Appendix E: Optional Leadforms - See page 1525 TOR) Rectifier