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Unit-5 Memory system

Characteristics of memory system:

Key characteristics of memory system

1. Location:
Internal location memory: it refers to the internal to the system such as processor
registers, main memory, cache
External location memory: it refers to the external to the system such as optical disks,
magnetic disks
2. Capacity: it refers to the capability of the memory to store data, in terms of number of
words and number of bytes
3. Unit of transfer: it refers to the transferring the data from memory to other unit of
computer system. It is in terms of word and block
4. Access method: it refers to the accessing the memory. Methods are: sequential, direct,
random, associative
5. Performance: performance of computer can be measured in terms of access time ,
cycle time and transfer rate.
6. Physical type: it is physically made of following materials such as semiconductor,
magnetic, optical and magneto-optical
7. Physical characteristics: memory may be volatile/non volatile and erasable/non
erasable
8. Organization: memory can be organized in to various modules.

primary memory:

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Main Memory: Every computer has a temporary storage area, which is built into the computer
hardware, and in which instruction and data of a program are stored and executed by the CPU. This
storage space is known as primary storage or main memory storage.
Every storage unit of a computer system is characterized and evaluated based on the properties such
as storage capacity, access time, and cost per bit of storage, volatile and random access.
1. Storage capacity: it is the amount of data, which can be stored in the storage unit. Main memory
has less storage capacity.
2. Access time: this is the time required to locate and retrieve stored data from the storage unit, in
response to a program instruction. Primary storage unit have faster access time.
3. Cost per bit of storage: this refers to the cost of a storage unit for a given storage capacity.
Primary storage units have higher cost per bit of storage.
4. Volatile. If the storage unit can retain the data stored in it, even when the power is turned off or
interrupted, it is called non-volatile storage. On the other hand, if the data stored are lost, when the
power is turned off or interrupted, it is called volatile storage. The non-volatile storage is desirable.
5. Random access: if the time taken to access a piece of data from the storage unit is independent of
the location of the data in the storage unit, it is called a random access storage or random access
memory (RAM). Each separate location of a RAM is as easy to access as any other location and
takes the same amount of time.
Main memory capacity:
Any data or information stored in computer memory is in the form of sequence of bits. A bit is a
binary digit either a 1 or 0. A group of 8 bits is called byte. Half of a byte is called a nibble. A word
is a group of sixteen bits or two bytes. A character is a number, letter or a special symbol. Eight bits
together make up a character
Main memory capacity is measured in terms of
1) 8 bits = 1 byte
2) 1024 bytes = 1 KB
3) 1 KB(kilobytes) is about 103 bytes kilo = thousand
4) 1 MB(megabytes) is about 106 bytes mega= million
5) 1 GB (gigabytes) is about 109 bytes giga= billion

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Types of main memory

1. RAM
2. ROM
RAM-random access memory(RW memory):
Random Access Memory called volatile and main memory of the computer system. It consist of
some IC chips on the motherboard (circuit board). processor can read for and write into this memory
.This memory is used for information that are likely to be altered such as writing program or
receiving data. This memory is volatile i.e. the content will be lost if the power is turned off and
commonly known as RAM, RAM are basically of two types. Read/write memory can be divided into
static and dynamic categories.
Static random access memory (SRAM) retains the data, once written, without further manipulation
so long as the source of power holds its value. SRAM is typically used for implementing the
processor registers and cache memories. The bulk of main memory in a typical computer system,
however, consists of dynamic random access memory (DRAM).
DRAM is a complex memory device that uses a tiny capacitor to store a bit. A charged capacitor
represents 1 bit. Since capacitors slowly lose their charge due to leakage, they must be refreshed
periodically to replace the charges representing 1 bit. A typical refresh period is about 64 ms.
Reading from DRAM involves testing to see if the corresponding bit cells are charged.
Unfortunately, this test destroys the charges on the bit cells. Thus, DRAM is a destructive read
memory. For proper operation, a read cycle is followed by a restore cycle. As a result, the DRAM
cycle time, the actual time necessary between accesses, is typically about twice the read access time,
which is the time necessary to retrieve a datum from the memory
Several types of DRAM chips are available.
SRAM vs DRAM
A. Static RAM (SRAM)
This memory is made up of flip flops and it stores bit as voltage. A single flip flop stores binary data
either 1 or 0. Each flip flop is called storage cell. Each cell requires six transistors. Therefore, the
memory chip has low density but high speed. This memory is more expensive and consumes more
power.
B. Dynamic RAM (DRAM)
This memory is made up of MOS transistor gates and it stores the bit as charge. The advantage of
DRAM are it has high density, low power consumption and cheaper than SRAM. But the bit
information leaks therefore needs to be rewritten again every few milliseconds. It is called refreshing
the memory and requires extra circuitry to do this. It is slower than SRAM..
FPM DRAMs Fast page-mode (FPM) DRAMs are an improvement over the previous generation
DRAMs. FPM DRAMs exploit the fact that we access memory sequentially, most of the time. To
know how this access pattern characteristic is exploited, we have to look at how the memory is
organized. Internally, the memory is organized as a matrix of bits. For example, a 32-Mb memory
could be organized as 8 K rows (i.e., 8192 since K = 1024) and 4-K columns. To access a bit, we
have to supply a row address and a column address. In the FPM DRAM, a page represents part of the
memory with the same row address. To access a page, we specify the row address only once; we can
read the bits in the specified page by changing the column addresses. Since the row address is not
changing, we save on the memory cycle time.
EDO DRAMs Extended Data Output (EDO) DRAM is another type of FPM DRAM. It also exploits
the fact that we access memory sequentially. However, it uses pipelining to speed up memory access.
That is, it initiates the next request before the previous memory access is completed. A characteristic
of pipelining inherited by EDO DRAMs is that single memory reference requests are not sped up.
However, by overlapping multiple memory access requests, it improves the memory bandwidth.

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SDRAMs Both FPM DRAMs and EDO DRAMs are asynchronous in the sense that their data output
is not synchronized to a clock. The synchronous DRAM (SDRAM) uses an external clock to
synchronize the data output. This synchronization reduces delays and thereby improves the memory
performance. The SDRAM memories are used in systems that require memory satisfying the
PC100/PC133 specification. SDRAMs are dominant in low-end PC market and are cheap.
DDR SDRAMs The SDRAM memories are also called single data rate (SDR) SDRAMs as they
supply data once per memory cycle. However, with increasing processor speeds, the processor bus
(also called front-side bus or FSB) frequency is also going up. For example, Pentium systems now
have 533-MHz FSB that supports a transfer rate of about 4.2 GB/s. To satisfy this transfer rate,
SDRAMs have been improved to provide data at both rising and falling edges of the clock. This
effectively doubles the memory bandwidth and satisfies the high data transfer rates of faster
processors.
RDRAMs Rambus DRAM (RDRAM) takes a completely different approach to increase the memory
bandwidth. A technology developed and licensed by Rambus, it is a memory subsystem that consists
of the RAM, RAMcontroller, and a high-speed bus called the Rambus channel. Like the DDR
DRAM, it also performs two transfers per cycle. In contrast to the 8-byte-wide data bus of DRAMs,
Rambus channel is a 2-byte data bus. However, by using multiple channels, we can increase the
bandwidth of RDRAMs. For example, a dual-channel RDRAM operating at 533 MHz provides a
bandwidth of 533 * 2 * 4 = 4.2 GB/s, sufficient for the 533-MHz FSB systems.
From this brief discussion it should be clear that DDR SDRAMs and RDRAMs compete with each
other in the high-end market. The race between these two DRAM technologies continues as Intel
boosts its FSB to 800 MHz.
Read Only Memory (ROM):
ROM contains a permanent pattern of data that cannot be changed. It is non volatile that is no power
source is required to maintain the bit values in memory. ROM are basically of 5 types.
A. Masked ROM: A bit pattern is permanently recorded by the manufactures during production.
B. Programmable ROM: In this ROM, a bit pattern may be written into only once and the writing
process is performed electrically. That may be performed by a supplier or customer.
C. Erasable PROM (EPROM):
This memory stores a bit in the form of charge by using EPROM programmer which applies high
voltage to charge the gate .Information can be erased by exposing ultra violet radiation. It is reusable.
The disadvantages are :(i) it must be taken out off circuit to erase it (ii). The entire chip must be
erased (iii) the erasing process takes 15 to 20 minutes.
D. Electrically Erasable PROM(EEPROM):
It is functionally same as EPROM except that information can be altered by using electrical signal at
the register level rather than erasing all the information. It is expensive compared to EPROM and
flash and can be erased in 10 ms.
E. Flash Memory:
It is variation of EPROM. The difference is that EPROM can be erased in register level but flash
memory must be erased in register level but flash memory must be erased in its entirety or at block
level.
Cache memory: it is memory between CPU and main memory. It is also called as buffer memory
between CPU and main memory. It is used in temporary storage, data & instructing during
processing. It is faster than main memory. It is commonly used for minimizing the memory
processor speed mismatch.

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Primary memory terminologies

1. Bit:
The basic unit of memory is the binary digit, called a bit. A bit may contain a 0 or a 1. The binary
� �

number system requires only two values to be distinguished. Consequently, it is the most reliable
�

method for encoding digital information.

2. Memory address:

Organizing memory:

 Adjacent cells have consecutive addresses (by definition).

 � Computers that use the binary number system (including octal and hexadecimal notation for
binary numbers) express memory addresses as binary numbers.
 � If an address has m bits, the maximum number of cells addressable is . ___

 � For example, an address used to reference the memory of Fig. 2-9 (a) needs at least 4 bits
in order to express all the numbers from 0 to 11.
 � A 3-bit address is sufficient for Fig. 2-9 (b) and (c), however.
 The number of bits in the address determines the maximum number of directly addressable
cells in the memory and is independent of the number of bits per cell.
 � For example, a memory with ____ _2 cells of 8 bits each and a memory with _____ cells of 64 bits
each need 12-bit addresses

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words
The significance of the cell is that it is the smallest addressable unit. Nearly all manufacturers have
standardized on an 8-bit cell, which is called a byte
Bytes are grouped into words
�

A computer with a 32-bit word has 4 bytes/word, whereas a computer with a 64-bit A word has 8
�

bytes/word.
most instructions work on words
For example,:
�

a 32-bit machine will have 32-bit registers and instructions for manipulating 32-bit words – such as
adding two words together.

Byte ordering

The bytes within a multi-byte data item can be numbered from Left-to-Right (Big-Endian) or
from Right-to-Left (Little-Endian). In the following example, table cells represent bytes, and the
cell numbers indicate the address of that byte in Main Memory.

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In Big-Endian systems the most significant byte of a multi-byte data item has the lowest address,
while the least significant byte has the highest address.

In Little-Endian systems, the least significant byte of a multi-byte data item has the lowest
address, while the most significant byte has the highest address. Note: an N-character string
value is not treated as one large multi-byte value, but rather as N single character values, i.e. the
first character of the string always has the lowest address, the last character has the highest
address. This is true for both big-endian and little-endian.

Example: Show the contents of memory at word address 24 if that word holds the number given
by 122E 5F01H in both the big-endian and the little-endian schemes?

Note: By convention, we order the bytes within a memory word left-to-right for big-endian and
right-to-left for little-endian.

Example: Show the contents of main memory from word address 24 if those words hold the text
JIM SMITH.

The bytes labelled with ? are unknown. They could hold important data, or they could be don’t
care bytes – the interpretation is left up to the programmer.

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Unfortunately computer systems, in use today are split between those that are big-endian, and
those that are little-endian. This leads to problems when a big-endian computer wants to transfer
data to a little-endian computer. Some recent architectures (e.g. PowerPC) allow the endian-ness
of the architecture to be switched programmatically.

Error correcting codes:

Computers memories can make error occasionally due to voltage spikes on the
power line or other causes.
To guard against such errors, some memories use error-detecting or error-
correcting codes.
When these codes are used extra bits are added to each memory word in a
special way. these extra bits are called redundant bits.
When a word is read out of memory, the extra bits are checked to see if an error
has occurred.
Suppose that a memory consists of m data bits to which we will add r redundant
or check bits.
Let total length be n= m +r
Thus, an n-bit unit containing data and r check bits is often refered to as an n-bit
codeword.
The number of bits positions in which two code words differs is called the
hamming distance.
The error detecting and correcting properties depends upon hamming distance.
To detect d single bit errors, you need a distance d+1 code.
Similarly, to correct d single bit error, you need a distance 2d+1 code.
Let a word=00111 and
A word=00010
Therefore, hamming distance=2 because, two bit positions changed.

ERROR CHECKING
Ensuring the integrity of data stored in memory is an important aspect of memory design. Two
primary means of accomplishing this are parity and error correction code (ECC).

Historically, parity has been the most commonly used data integrity method. Parity can detect -
but not correct - single-bit errors. Error Correction Code (ECC) is a more comprehensive
method of data integrity checking that can detect and correct single-bit errors.

The type of data integrity checking depends on how a given computer system will be used. If the
computer is to play a critical role - as a server, for example - then a computer that supports data
integrity checking is an ideal choice. In general:
 Most computers designed for use as high-end servers support ECC memory.
 Most low-cost computers designed for use at home or for small businesses support non-
parity memory.

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PARITY
When parity is in use on a computer system, one parity bit is stored in DRAM along with every 8
bits (1 byte) of data. The two types of parity protocol - odd parity and even parity - function in
similar ways.

This table shows how odd parity and even parity work. The processes are identical but with
opposite attributes.

ODD PARITY EVEN PARITY

The parity bit is forced to 0 if the
The parity bit will be forced to 1 (or turned "on") if its
byte contains an even number of
corresponding byte of data contains an even number
1's.
Step of1's.
1
The parity bit is forced to 1 if its
If the byte contains an odd number of 1's, the parity
corresponding byte of data contains
bit is forced to 0 (or turned "off ").
an odd number of 1's.
Step The parity bit and the corresponding 8 bits of data are
(Same as for odd parity)
2 written to DRAM.
Just before the data is sent to the CPU, it is
intercepted by the parity circuit. (Same as for odd parity)

If the parity circuit sees an odd number of 1's, the data Data is considered valid if the
Step is considered valid. The parity bit is stripped from the parity circuit detects an even
3 data and the 8 data bits are passed on to the CPU. numberof1's.

If the parity circuit detects an even number of 1's, the Data is invalid if the parity circuit
data is considered invalid and a parity error is detects an odd number of 1's.
generated.
Parity does have its limitations. For example, parity can detect errors but cannot make
corrections. This is because the parity technology can't determine which of the 8 data bits are
invalid.
Consider adding a single parity bit to the data. The bit is chosen so that the number of 1 bits in
the codeword is even (or odd). Now a single error results in an invalid codeword. It takes two
errors to go from one valid codeword to another.
Imagine we want to design a code with m data bits and r check bits that will allow all single-bit
errors to be corrected. Each of the 2m legal memory words has n illegal codewords at a distance 1
from it.
Form these by inverting each of the n bits in the n-bit codeword.
Each of the 2m legal memory words requires n + 1 bit patterns dedicated to it.
(n + 1) 2m <= 2n since n = m + r, (m + r + 1) <= 2r

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In above, Number of check bits for a code that can correct a single error.

The following figure illustrates an error-correcting code for 4-bit words. The three circles form 7
regions. Encode the 4-bit word 1100 in four of those regions then add a parity bit to each of the
three empty regions so that the sum of the bits in each circle is an even number.
Now suppose that the bit in the AC region goes bad, changing from a 0 to a 1. Circles A and C
have the wrong parity. The only single-bit change that corrects them is to restore AC back to 0,
thus correcting the error.

(a) Encoding of 1100

(b) Even parity added

(c) Error in AC

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Hamming’s algorithm for error correcting and detecting

Hamming’s algorithm can be used to construct single error-correcting codes for any size
memory word. In a Hamming code, r parity bits are added to an m-bit word, forming a new word
of length m + r bits.
The bits are numbered starting at 1, not 0, with bit 1 the leftmost (high-order) bit. All bits whose
bit number is a power of 2 are parity bits; the rest are used for data.
In a 16-bit word, 5 parity bits are added. Bits 1, 2, 4, 8, and 16 are parity bits. The word has 21
total bits
Each parity bit checks specific bit positions; the parity bit is set so that the total number of 1s in
the checked positions is even. The positions checked are:

Bit 1 checks bits 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21.

Bit 2 checks bits 2, 3, 6, 7, 10, 11, 14, 15, 18, 19.

Bit 4 checks bits 4, 5, 6, 7, 12, 13, 14, 15, 20, 21.

Bit 8 checks bits 8, 9, 10, 11, 12, 13, 14, 15.

Bit 16 checks bits 16, 17, 18, 19, 20, 21.

In general each bit b is checked by those bits b1, b2, …, bj such that b1 + b2 + … + bj = b.

Figure: Construction of the Hamming code for the memory word 11110000010101110 by
adding 5 check bits to the 16 data bits.

Note: take example of your class note and do practice more and more times.

 Consider what would happen if bit 5 in the word on the previous slide were inverted by a
surge on the power line. Bit 5 would then be a 0. The 5 parity bits would be checked with
the following results:
 Parity bit 1 incorrect (positions checked contain 5 1s)

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Parity bit 2 correct (positions checked contain 6 1s)

Parity bit 4 incorrect (positions checked contain 5 1s)

Parity bit 8 correct (positions checked contain two 1s)

Parity bit 16 correct (positions checked contain four 1s)

 The incorrect bit must be one of the bits checked by parity bit 1 and by parity bit
4. These are bits 5, 7, 13, 15, or 21. However, bit 2 is correct, eliminating 7 and
15. Similarly, bit 8 is correct, eliminating 13. Finally, bit 16 is correct,
eliminating 21. The only bit left is 5, which is the one in error.
 If all parity bits are correct, there were no errors (or more than one). Otherwise,
add up all the incorrect parity bits. The sum gives the position of the incorrect bit.

 Example: construct a Hamming code for the 16-bit memory word:

1111000010101110. The 21-bit codeword is 001011100000101101110

0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 1 0 1 1 1 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
- - - - --

The parity bits are underlined.

 To simulate a problem, what would happen if bit 5 were inverted

by a surge in the power line. The new codeword would be:

0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 1 0 1 1 1 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
- - - - --

 Check the 5 parity bits (for even parity):

1. Parity bit 1 is incorrect: 1,3,5,7,9,11,13,15,17,19,21

contain five 1s
2. Parity bit 2 is correct: 2,3,6,7,10,11, 14,15,18,19
contain six 1s
3. Parity bit 4 is incorrect: 4,5,6,7,12,13,14,15, 20,21
contain five 1s
4. Parity bit 8 is correct: 8,9,10,11,12,13,14,15
contain two 1s
5. Parity bit 16 is correct: 16,17,18,19,20,21
contain four 1s

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 Analysis: Parity bits 1 and 4 are incorrect, so the incorrect

is a bit that is in both lists: 5, 7, 13, 15, or 21
7 is also correct in parity bit 2
13 is also correct in parity bit 8
15 is correct in parity bit 2
21 is correct in parity bit 16
5 is left shared by both parity bit 1 and 4.
The incorrect bit is in bit 5.

 Faster method: Add up the incorrect parity bits ( 1 + 4 = 5)

Cache Memory

 Cache Memory - a technique of combining a small amount of fast memory (cache) with a
large amount slow memory (main memory) to get the speed of the fast memory (almost) and the
capacity of the large memory at a moderate price.

 The small, fast memory is called a cache: The most heavily used memory
words are kept in the cache.

 When the CPU needs a word, it first looks in the cache. Only if the word
is not there, does it go to main memory.
 If a substantial fraction of the words are in the cache, the average
access time can be greatly reduced.
 Success or failure of this system depends on what fraction of the words are in the cache.

 Locality principle: the observation that the memory references made in

any short time interval tend to use only a small fraction of the total memory.

 The locality principle forms the basis for most cache systems.

 When a word is referenced, it and some of its neighbors are brought from
the large slow memory into the cache, so that the next time it is used
it can be accessed quickly.

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 If a word is read or written k times in a short interval, the computer

will need 1 reference to slow memory and k - 1 references to fast memory.
The larger k is, the better the overall performance.

 h = (k - 1)/k where h is the "hit ratio", the fraction of all references

that can be made from the cache.

 1 - h is called the "miss ratio", the percentage of time where the

reference will be made out of main memory.

 Mean access time = c + (1 - h)/m where c is the cache access time, and
m is the main memory access time.

 As h -> 1, all references can be satisfied ou of the cache, and the

access time approaches c.

 As h -> 0, a memory reference is needed every time, so the access time

approaches c + m, first a time c to check the cache (unsuccessfully), and then
a time m to do the memory reference.

Using locality principle, the main memories and caches are divided up into fixed block size
blocks. These blocks inside the cache are commonly referred to as cache lines.

Cache design issues:

1. Cache size: The bigger the cache, the better it performs, but also the more its costs.
2. Size of the cache line: A 16 KB cache can be divided into 1024 lines of 16 bytes, 2048
lines of 8 bytes and other combinations.
3. Cache organization: How does the cache keep track of which memory words are
currently being held?
4. Whether the instructions and data are kept in the same cache or different ones.
a. Example: unified cache for both data and instruction and split cache for data and
instruction each separately. This architecture is also called Harvard architecture.
5. The number of caches: the number of caches can be used as level L1, level L2 and level
L3 as required but its cost also increases.

Memory packaging and its types

The arrangement of memory chips is known as memory packaging.

SIMM (Single In-line Memory Modules)

SIMMs are used to store a single row of DRAM, EDO or BEDO chips where the module is
soldered onto a PCB. One SIMM can contain several chips. When you add more memory to a
computer, most likely you are adding a SIMM.
The first SIMMs transferred 8 bits of data at a time and contained 30 pins. When CPU's began to
read 32-bit chunks, a wider SIMM was developed and contained 72 pins.

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72 pin SIMMS are 3/4" longer than 30 pin SIMMs and have a notch in the lower middle of the
PCB. 72 pin SIMMs install at a slight angle.

DIMM (Dual In-line Memory Modules)

DIMMs allow the ability to have two rows of DRAM, EDO or BEDO chips. They are able to
contain twice as much memory on the same size circuit board. DIMMs contain 168 pins and
transfer data in 64 bit chunks.
DIMMs install straight up and down and have two notches on the bottom of the PCB.
SO DIMM (Small Outline DIMM)
SO DIMMs are commonly used in notebooks and are smaller than normal DIMMs. There are
two types of SO DIMMs. Either 72 pins and a transfer rate of 32 bits or 144 pins with a transfer
rate of 64 bits.
RDRAM - RIMM
Rambus, Inc, in conjunction with Intel has created new technology, Direct RDRAM, to increase
the access speed for memory. RIMMs appeared on motherboards sometime during 1999. The in-
line memory modules are called RIMMs. They have 184 pins and provide 1.6 GB per second of
peak bandwidth in 16 bit chunks. As chip speed gets faster, so does the access to memory and the
amount of heat produced. An aluminum sheath, called a heat spreader, covers the module to
protect the chips from overheating.
SO RIMM
Similar in appearance to a SO DIMM and uses Rambus technology.

Figure . A single inline memory module (SIMM) holding

32 MB. Two of the chips control the SIMM

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Floppy Disks
•
With the advent of the personal computer, a way was needed to distribute software - the
solution was found in the diskette or floppy disk.
 Unlike hard disks, where the heads float just above the surface on a cushion of rapidly-
moving air, floppy disk heads actually touch the diskettes.
 As a result, both the media and the heads wear out comparatively quickly.
 To reduce wear and tear, personal computers retract the heads and stop the rotation when
a drive is not reading or writing.
 Various sizes exist: 5.25 inch and 3.5 inch - and obsolete 8.5 inch.
• The 3.5-inch diskettes come in a rigid jacket for protection.
IDE (Integrated Drive Electronics)

IDE (Integrated Drive Electronics) is a standard electronic interface used between a computer
motherboard's data paths or bus and the computer's disk storage devices. The IDE interface is
based on the IBM PC Industry Standard Architecture (ISA) 16-bit bus standard, but it is also
used in computers that use other bus standards. Most computers sold today use an enhanced
version of IDE called Enhanced Integrated Drive Electronics (EIDE). In today's computers, the
IDE controller is often built into the motherboard.

IDE was adopted as a standard by American National Standards Institute (ANSI) in November,
1990. The ANSI name for IDE is Advanced Technology Attachment (ATA). The IDE (ATA)
standard is one of several related standards maintained by the T10 Committee.

 Modem personal computer disks evolved from the one in the IBM PC XT, which was a
10- MB Seagate disk controlled by a Xebec disk controller on a plug-in card.
•
The controller was capable of handling two drives.
•
The operating system read from and wrote to a disk by putting parameters in CPU registers
and then calling the BIOS (Basic Input Output System), located in
•
The move was then away from having the controller on a separate board, to having it
closely integrated with the drives, starting with IDE (Integrated Drive Electronics) drives in
the mid 1980s.
•
Only 528MB could be addressed by the operating system.

EIDE Disks
•
Eventually, IDE drives evolved into EIDE drives (Extended IDE), which also support a second
addressing scheme called LBA (Logical Block Addressing)
•

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Still only 528MB could be addressed.

•
EIDE drives and controllers also have other improvements, such as the ability to control
four drives instead of two, a higher transfer rate, and the ability to control CD-ROM drives.

SCSI Disks
•
SCSI stands for (Small Computer System Interface) and is pronounced "scuzzy."
•
SCSI disks have a different interface and much higher transfer rates than IDE / EIDE disks.
•
They are the standard disk in most UNIX workstations, Macintoshes and high-end Intel PCs.
•
SCSI is more than just a hard disk interface - it is a bus to which a SCSI controller and up to
seven devices can be attached.
•
These can include one or more SCSI hard disks, CD-ROMS, CD recorders, scanners,
tape units, and other SCSI peripherals.
•
Each SCSI device has a unique ID, from 0 to 7 (15 for wide SCSI) and two connectors: one
for input and one for output for "daisy-chaining" allowing all the devices to run at once.

RAID
•
CPU performance has been increasing exponentially
over the past decade, roughly doubling every 18 months.
•
Not so with disk performance.
•
It was realised that parallel IO might be a good idea.
•
This has led to a new class of IO device called a RAID.
•
The originator defined RAID as Redundant Array of Inexpensive Disks, but industry
redefined the I to be "Independent" rather than "Inexpensive"

CD-ROM
•
Optical (as opposed to magnetic) disks have become available.
•
They have much higher recording densities than conventional magnetic disks.
•
CD-ROM stands for Compact Disk – Read Only Memory
•
A CD is prepared using a molding process from a "burned" (using a laser) master disk.

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•
Data is physically stored on the CD-ROM surface as a series of depressions called pits
and unburned areas between the pits called lands.
•
In play-back, a low-power laser diode shines infrared light and reads the disk by reflection.
•
A pit / land transition represents 1, its absence a 0.

CD-ROM

Spiral groove
Pit
Land
2K block of user data

CD-Recordables
A CD-Recorder (CD-R) is now a common peripheral which is similar in size to a CD-ROM
drive
•
These devices are different from magnetic disks because once written, CD-ROMs can not
be erased.
•
Useful for backup purposes and for making copies of CDs.

CD-Rewritables
•
Although people are used to other write-once media such as paper and photographic film,
there is a demand for a rewritable CD-ROM.
•
One technology now available is CD-RW (CD ReWritable), which uses the same size media
as CD-R.
•
However, CD-RW uses a different alloy for the recording layer.
•
The reason CD-RW has not replaced CD-R is that that the CD-RW blanks are much more
expensive than the CR-R blanks.
•
Also, for applications consisting of backing up hard disks, the fact that once written, a CD-R
can not be accidentally erased is a big plus.

Note: for detail and figure refer to given note.

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DVD
•
DVD, originally an acronym for Digital Video Disk, but now officially Digital Versatile Disk.
•
Looks like a CD-ROM.
•
What is new is the use of - Smaller pits (0.4 microns versus 0.8 microns for CDs).
- A tighter spiral (0.74 microns between tracks versus 1.6 microns for CDs).
- A red laser (at 0.65 microns versus 0.78 microns for CDs).
•
Together, these improvements raise the capacity sevenfold, to 4.7 GB.
•
Four formats have been defined - max capacity possible would be 17 GB.

Unit -6 Input output organization

6.1 Peripheral devices:
The devices which are used to communicate the CPU with outside world for data and
information sharing and others.
The peripheral devices are:
Input Devices: used for communicating with input devices
•Keyboard
•Optical input devices-Card Reader-Paper Tape Reader-Bar code reader-Digitizer-Optical Mark
Reader
•Magnetic Input Devices-Magnetic Stripe Reader
•Screen Input Devices-Touch Screen-Light Pen-Mouse
•Analog Input Devices

Output Devices: used for communicating with output devices

•Card Puncher, Paper Tape Puncher
•CRT
•Printer (Impact, Ink Jet, Laser, Dot Matrix)
•Plotter
•Analog
•Voice

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6.2 Input/Output Interfaces

•Provides a method for transferring information between internal storage (such as
memory and CPU registers) and external I/O devices
•Resolves the differencesbetween the computer and peripheral devices
–Peripherals -Electromechanical Devices
–CPU or Memory -Electronic Device
–Data Transfer Rate
»Peripherals -Usually slower
»CPU or Memory -Usually faster than peripherals
•Some kinds of Synchronization mechanism may be needed

–Unit of Information
»Peripherals –Byte, Block, …
»CPU or Memory –Word
–Data representations may differ

Each peripheral has an interface module associated with it Interface

-Decodes the device address (device code)
-Decodes the commands (operation)
-Provides signals for the peripheral controller
-Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory

thus, from above we have,

the input output buses in computer system are mainly:
address bus
data bus
control bus

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Input/output buses and memory buses

Functions of Buses
* MEMORY BUSis for information transfers between CPU and the MM
* I/O BUSis for information transfers between CPU and I/O devices through their I/O interface
Physical Organizations
Many computers use a common single bus system for both memory and I/O interface units
-Use one common bus but separate control lines for each function
-Use one common bus with common control lines for both functions
* Some computer systems use two separate buses, one to communicate with memory and the
other with I/O interfaces
I/O Bus
-Communication between CPU and all interface units is via a common I/O Bus
-An interface connected to a peripheral device may have a number of data registers , a control
register, and a status register
-A command is passed to the peripheral by sending to the appropriate interface register
-Function code and sense lines are not needed (Transfer of data, control, and status information
is always via the common I/O Bus)

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I/O interface types:

Isolated I/O
Separate I/O read/write control lines in addition to memory read/write control lines
-Separate (isolated) memory and I/O address spaces
-Distinct input and output instructions
Memory-mapped I/O
A single set of read/write control lines (no distinction between memory and I/O transfer)
-Memory and I/O addresses share the common address space
-> reduces memory address range available
-No specific input or output instruction
-> The same memory reference instructions can be used for I/O transfers
-Considerable flexibility in handling I/O operations
Example of I/O interface

Information in each port can be assigned a meaning depending on the mode of operation of the
I/O device
→Port A = Data; Port B = Command; Port C = Status
-CPU initializes(loads) each port by transferring a byte to the Control Register
→Allows CPU can define the mode of operation of each port
→Programmable Port: By changing the bits in the control register, it is possible to change the
interface characteristics.

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Transmitter Register
-Accepts a data byte(from CPU) through the data bus
-Transferred to a shift register for serial transmission Receiver
-Receives serial information into another shift register
-Complete data byte is sent to the receiver register Status Register Bits
-Used for I/O flags and for recording errors Control Register Bits
-Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of
stop bits

Input/Output techniques
• Programmed I/O
• Interrupt driven I/O
• Direct Memory Access (DMA)

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Programmed I/O:
• CPU has direct control over I/O
 Sensing status of I/O
 Read/write commands
 Transferring data to I/O
• CPU waits for I/O module to complete operation
• Wastes CPU time (waits I/O ready?)
In detail
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
Input/output commands in programmed I/O
• CPU issues address
• Identifies module (& device if >1 per module)
• CPU issues command

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• Control - telling module what to do

• e.g. spin up disk
• Test - check status
• e.g. power? Error?
• Read/Write
• Module transfers data via buffer from/to device

Interrupt driven I/O

• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
Basic operation:

• CPU issues read command

• I/O module gets data from peripheral whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
CPU view point:
• Issue read command
• Do other work
• Check for interrupt at end of each instruction cycle
• If interrupted:-
• Save context (registers)
• Process interrupt
• Fetch data & store

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Figure: simple interrupt processing

DMA( direct memory access)

* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between Memory and Device,
freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory address and the block size(number of
words)

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DMA operation
Starting an I/O
-CPU executes instruction to
Load Memory Address Register
Load Word Counter
Load Function(Read or Write) to be performed
-Issue a GO command
-Upon receiving a GO Command DMA performs I/O
operation as follows independently from CPU
Input
[1] Input Device <-R (Read control signal)
[2] Buffer(DMA Controller) <-Input Byte; and assembles the byte into a word until word is full
[4] M <-memory address, W(Write control signal)
[5] Address Reg <-Address Reg +1; WC(Word Counter) <-WC -1
[6] If WC = 0, then Interrupt to acknowledge done, else go to [1]
Output
[1] M <-M Address, R
M Address R <-M Address R + 1, WC <-WC -1
[2] Disassemble the word
[3] Buffer <-One byte; Output Device <-W, for all disassembled bytes
[4] If WC = 0, then Interrupt to acknowledge done, else go to [1]

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DMA Cycle stealing:

-While DMA I/O takes place, CPU is also executing instructions
-DMA Controller and CPU both access Memory -> Memory Access Conflict Memory Bus
Controller
-Coordinating the activities of all devices requesting memory access
-Priority System
-Memory accesses by CPU and DMA Controller are interwoven, with the top priority given to
DMA Controller
-> Cycle Stealing
Cycle Steal:
-CPU is usually much faster than I/O(DMA), thus
CPU uses the most of the memory cycles
-DMA Controller steals the memory cycles from CPU
-For those stolen cycles, CPU remains idle
-For those slow CPU, DMA Controller may steal most of the memory cycles which may cause
CPU remain idle long time

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