ALU (Arithmetic Logic Unit)

An arithmetic logic unit (ALU) is a digital circuit that

performs arithmetic and bitwise logical operations on integer binary numbers. It is a
fundamental building block of the central processing unit found in many digital
computers. Powerful and complex ALUs are often used in modern, high performance
CPUs and graphics processing units (GPUs). A single CPU or GPU may contain
multiple ALUs.Basically an ALU is constructed from four hardware building blocks such
as AND and OR gate, inverters and multiplexers

Typical Schematic Symbol of an ALU

A and B: the inputs to the ALU(aka operands)

R: Output or Result

F: Code or Instruction from the Control Unit (aka as op-code)

D: Output status; it indicates cases such as:

• carry-in

• carry-out,

• overflow,

• division-by-zero

Construction of ALU

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 A 1-Bit ALU

The logical operations are easiest, because they map directly onto the hardware
components in Figure B.2.1.The 1-bit logical unit for AND and OR looks like Figure B.5.1. The
multiplexor on the right then selects a AND b or a OR b, depending on whether the value of
Operation is 0 or 1. The line that controls the multiplexor is shown in color to distinguish it
from the lines containing data. Notice that we have renamed the control and output lines of
the multiplexor to give them names that reflect the function of the ALU The next function to
include is addition. An adder must have two inputs for the operands and a single-bit output
for the sum. There must be a second output to pass on the carry, called Carry Out. Since the
Carry Out from the neighbor adder must be included as an input, we need a third input. This
input is called Carry In.

Figure The 1-bit logical unit for AND and OR.

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 FIGURE A 1-bit adder. This adder is called a full adder; it is also called a (3,2)
adder because it

has 3 inputs and 2 outputs. An adder with only the a and b inputs is called a (2,2)
adder or half adder.

Figure: A 1-bit ALU that performs AND, OR, and addition

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 Figure: A 32-bit ALU constructed from 32 1-bit ALUs

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 Figure :A 1-bit ALU that performs AND, OR, and addition on a and b or a and b.
By selecting b (Binvert = 1) and setting CarryIn to 1 in the least significant bit of
the ALU, we get two’s complement subtraction of b from a instead of addition of
b to a.

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 Figure: A 1-bit ALU that performs AND, OR, and addition on A and B or A and B.
By selecting a (A invert = 1) and b (B invert = 1), we get a NOR b instead of a AND
b.

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 3.3 Instruction execution

The CPU executes each instruction in series of small steps.

The steps are as follows:

1. fetch the next instruction from memory into the instruction register
2. change the program counter to point to the following instruction
3. determine the type of instruction just fetched
4. if the instruction uses a word in a memory, determine where it is
5. fetch the word , if needed into a CPU register
6. execute the instruction
7. go to step 1 to begin executing the following instruction
This sequence of steps is frequently referred to as the fetch-decode- execute cycle.
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 Instruction execution in detail

1 .Fetching the instruction…(fetch cycle)

The next instruction is fetched from the memory address that is currently stored in
the program counter (PC), and stored in the instruction register (IR). At the end of
the fetch operation, the PC points to the next instruction that will be read at the next
cycle.

2. Decode the instruction……(decode cycle)

The decoder interprets the instruction. During this cycle the instruction inside the IR
(instruction register) gets decoded.

3. In case of a memory instruction (direct or indirect) the execution phase will be in the next clock pulse.
If the instruction has an indirect address, the effective address is read from main memory, and any
required data is fetched from main memory to be processed and then placed into data registers(Clock
Pulse: T3). If the instruction is direct, nothing is done at this clock pulse. If this is an I/O instruction or a
Register instruction, the operation is performed (executed) at clock Pulse.

4. Execute the instruction…..(execute cycle )

The control unit of the CPU passes the decoded information as a sequence of control signals to the
relevant function units of the CPU to perform the actions required by the instruction such as reading
values from registers, passing them to the ALU to perform mathematical or logic functions on them, and
writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The
result generated by the operation is stored in the main memory, or sent to an output device. Based on
the condition of any feedback from the ALU, Program Counter may be updated to a different address
from which the next instruction will be fetched.

The cycle is then repeated.

3.4 Addressing modes

Instruction Format defines the layout of bits in an instruction

The format of an instruction is divided into groups called fields as follows.

 Op-code field
 address field
 mode field

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 Figure: Instruction format

Operand addressing

 it refers to the amount of byte assigned to the operands.

1. Three-address instructions (3 byte)
o Use mainly memory
o Use mainly register
2. Two-address instructions (2 byte)
o Immediate instruction are involved generally.
3. One-address instructions( 1 byte)
o A register called accumulator (ACC) is necessary.
4. Zero-address instructions ( 0 byte)
o Use a stack
o Last-in, first-out (LIFO)
o Use push and pop instruction
o TOS: top of stack

3.4 Addressing mode:

It defines as follows:

 The rule for interpreting or modifying the address field of an instruction.

• addressing mode – method of forming a memory address

• For a given instruction set architecture, addressing modes define how machine
language instructions identify the operand (or operands) of each instruction.

• An addressing mode specifies how to calculate the effective memory address of

an operand by using information held in registers and/or constants contained
within a machine instruction or elsewhere.

• Different types of addresses involve tradeoffs between instruction length,

addressing flexibility, and complexity of address calculation

Effective address: The address of operand produced by the application of the rule for
interpreting or modifying the address field of the instruction before the operand is
actually referenced.

Types of addressing modes:

1. Immediate addressing mode

2. Direct addressing mode
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 3. Register addressing mode
4. Register indirect addressing mode
5. Indexed addressing mode
6. Based indexed addressing mode
7. Stack addressing mode

Immediate addressing mode:

In this mode,
• the instruction itself contains the value to be used; located in the address field of the
instruction
• the value is stored in memory immediately after the instruction opcode in memory
• Similar to using a constant in a high level language
• Advantage
– fast, since the value is included in the instruction; no memory reference to
fetch data
• Disadvantage
– not flexible, since the value is fixed at compile-time
– can have limited range in machines with fixed length instructions
thus,
 Operand is part of instruction
 Operand = address field
e.g. ADD 5
where, Add 5 to contents of accumulator
there fore, 5 is operand
 No memory reference to fetch data
 Fast
 Limited range

Instruction

 Op-code  operand

Figure: immediate addressing diagram

Direct addressing mode:

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 In this mode,
• The instruction tells where the value can be found, but the value itself is out in
memory.
• The address field contains the address of the operand
• Effective address (EA) = address field (A)
• In a high level language, direct addressing is frequently used for things like
global variables.
• Advantage
• Single memory reference to access data
• More flexible than immediate
• e.g. ADD A
— Add contents of cell A to accumulator
— Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective address
• Limited address space

Figure: direct addressing diagram

Indirect addressing:
In this mode Memory cell pointed to by address field contains the address of (pointer to) the operand

•effective address(EA) = (A)

—Look in A, find address (A) and look there for operand
•e.g. ADD (A)
—Add contents of cell pointed to by contents of A to accumulator

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 Figure : Addressing diagram of indirect addressing mode
Register addressing mode:
Register addressing mode is conceptually same as the direct addressing mode but specifies a
register instead of memory location. thus
• Operand is held in register named in address filed
• Effective address(EA) = R
• Limited number of registers
• Very small address field needed
— Shorter instructions
— Faster instruction fetch

Figure: Register addressing diagram

Register indirect addressing mode:
In this addressing mode, the operand specified comes from memory or goes to memory, but its
address is not hardwired into the instruction, as a direct addressing, instead, the address is
contained in a register. When a address is used in this manner, it is called a pointer.
Advantage:
It can reference memory without paying the price of having a full memory address in the
instruction. Thus,
• EA = (R)
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 • Operand is in memory cell pointed to by contents of register R
• Large address space (2n)
• One fewer memory access than indirect addressing
•

Figure: Register indirect addressing diagram

Indexed addressing:
It is frequently useful to be able to reference memory words at a known offset from a register. The
addressing memory by giving a register( explicit or implicit) plus a constant offset is called indexed
addressing.
• A = base
• R = displacement
• EA = A + R
• Good for accessing arrays
— EA = A + R
— R++
Based indexed addressing:
the memory addressing is computed by adding up two registers plus an(optional) offset. In which one
of the register is base and other is the index.
For example:
MOV R4 (R2+R5)

Stack addressing mode:

• Operand is (implicitly) on top of stack
• e.g. ADD Pop top two items from stackand add
• ex: PUSH and POP instruction

Table: Examples for addressing modes

Addressing mode Assembly convention Register transfer Explanation

Direct address LD ADR AC-M[ADR] Load memory address
direct
Indirect address LD @ADR AC-M[M[ADR]] Load through pointer to
memory cell
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Relative address LD $ADR AC-M[PC+ADR] load program counter
value plus address
Immediate LD #NBR AC-NBR Immediate data or
number to accumulator
Indexed addressing LD ADR(X) AC-M[ADR+XR] Load with address plus
indexed value
Register LD R1 AC-R1 Load direct with register
value
Register indirect LD (R1) AC-M(R1) Load with address
pointed by register

Where LD-load , AC- accumulator, NBR-number, ADR-adrress,

Hardwired and micro-programmed

For instruction, the control unit causes the CPU to execute the sequence of steps
correctly. The control unit provides various control signals to execute the
instruction to the CPU. There are two approaches or ways to provide the
controls signals, these are:

a. hardwired control
b. micro-programmed control
c. The
d. first approach is to physically connect all of the control lines to the actual machine
e. instructions. The instructions are divided up into fields, and different bits in the
f. instruction are combined through various digital logic components to drive the control
g. lines. This is called hardwired control, and is illustrated in figure (1)

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The control unit is implemented using hardware (for example: NAND gates, flip-flops, and counters).We need a
special digital circuit that uses , as inputs, the bits from the Opcode field in our instructions, bits from the flag
(or status) register,
signals from the bus, and signals from the clock. It should produce, as outputs, the control signals to drive the
various components in the computer.
The advantage of hardwired control is that is very fast. The disadvantage is that the instruction set and the
control logic are directly tied together by special circuits that are complex and difficult to design or modify. If
someone designs a hardwired computer and later decides to extend the instruction set, the physical components
in the computer must be changed. This is prohibitively expensive, because not only must new chips be
fabricated but also the old ones must be located and replaced.
Microprogramming is a second alternative for designing control unit of digital computer (uses software for
control). A control unit whose binary control variables are stored in memory is called a microprogrammed
control unit. The control variables at any given time can be represented by a string of 1's and 0's called a
control word (which can be programmed to perform various operations on the component of the system). Each
word in control memory contains within it a microinstruction. The microinstruction specifies one or more
microoperatiotins for the system.
A sequence of microinstructions constitutes a micr-oprogram. A memory that is part of a control unit is
control memory.
A more advanced development known as dynamic microprogramming permits a microprogram to be loaded
initially from an auxiliary memory such as a magnetic disk. Control units that use dynamic microprogramming
employ a writable control memory; this type of memory can be used for writing (to change the microprogram)
but is used mostly for reading.
The general configuration of a microprogrammed control unit is demonstrated in the block diagram of Figure
(2). The control memory is assumed to be a ROM, within which all control information is permanently stored.

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The control memory address register specifies the address of the microinstruction and the control data register
holds the microinstruction read from memory the microinstruction contains a control word that specifies one or
more microoperations for the data processor. Once these operations are executed, the control must determine
the next address. The location of the next microinstruction may be the one next in sequence, or it may be locate
somewhere else in the control memory. For this reason it is necessary to use some bits of the present
microinstruction to control the generation of the address of the next microinstruction. The next address may also
be a function of external input conditions. While the microoperations are being executed, the next address is
computed in the next address generator circuit and then transferred into the control address register
to read the next microinstruction.
The next address generator is sometimes called a microprogram sequencer, as it determines the address
sequence that is read from control memory, the address of the next microinstruction can be specified several
ways, depending on the sequencer inputs. Typical functions of a microprogram sequencer are incrementing the
control address register by one, loading into the control address register an address from control memory,
transferring an external address or loading an initial address to start the control
operations.
The main advantages of the microprogrammed control are the fact that once the hardware configuration is
established; there should be no need for further hardware or wiring changes. If we want to establish are different
control sequence for the system, all we need to do is specify different set microinstructions for control memory.
The hardware configuration should not be changed for different operations; the only thing that must be changed
is the microprogram residing in control memory.
Microinstructions are stored in control memory in groups, with each group specifying routine. Each computer
instruction has microprogram routine in control memory to generate the microoperations that execute the
instruction. The hardware that controls the address sequencing of the control memory must be capable of
sequencing the microinstructions within a routine and be to branch from one routine to another. The address
sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit conditions.
3. A mapping process from the bits of the instruction to an address for control memory.
4. A facility for subroutine call and return.
Figure (3) shows a block diagram of control memory and the associated hardware needed for selecting the next
microinstruction address. The microinstruction in control memory contains a set of bits to initiate
microoperations in computer registers and other bits to specify the method by which the address is obtained.
The diagram shows four different paths from which the control address register (CAR) receives the address.
The incrementer increments the content of the control address register by one, to select the next
microinstruction in sequence. Branching is achieved by specifying the branch address in one of the fields of the
microinstruction. Conditional branching is obtained by using part of the microinstruction to select a specific
status bit in order to determine its condition. An external address is transferred into control memory via a
mapping logic circuit. The return address for a subroutine is stored in a special register whose value is then
used when the microprogram wishes to return from the subroutine.

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In brief,
Hard‐wired Control Unit‐advantages
1. Minimizes the average number of clock cycles needed per instruction
2. occupies a relatively small area (typically 10%) of the CPU chip area
3. High efficiency in terms of operation speed
4. is to minimize cost of the circuit

Problems With Hard Wired Designs

•Complex sequencing & micro‐operation logic
•Difficult to design and test
•Inflexible design
•Large design turn around time for complex design
•Difficult to add new instructions

Microprogrammed Control in brief

The concept of micro programmed control, employ the following steps:

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 1. Any instruction to be executed on a CPU can be broken down into a set of sequential micro
operations –each specifying a RTL operation on the data path. The set of micro operations to be
executed on the RTL components at any time step is referred as microinstructions.
The sequence of control signals necessary to execute the sequential microinstructions stored in
ROM called control ROM
2. To implement an instruction on the data path , the control signals stored in the ROM can be
accessed
3. The control signals read from the ROM are used to control the micro operations associated with
a microinstruction to be executed at any time step
4. The address of the next micro instruction is generated
5. The steps 3,4 and 5 are repeated till the set of sequential microinstructions associated with the
instruction is executed

Micro‐programmed Control Unit ‐Advantages

1. A micro‐programmed control unit is flexible and allows designers to incorporate new and more
powerful instructions as VLSI technology increases the available chip area for the CPU
2. allows any design errors discovered during the prototyping stage to be removed

RISC AND CISC

Concept behind RISC and CISC architectures
As and when new evolving needs emerge with respect to the hardware design/architecture, hardware
architects invent various technologies and tools to implement the desired architecture in order to fulfill these
needs. Hardware architecture may be implemented to be either hardware specific or software specific, but
according to the application both are used in required proportion. As far as the processor hardware is
concerned, there are two types of concepts to implement the processor hardware architecture. First one is
Reduce instruction set computer (RISC) and other is Complex instruction set computer (CISC)

Intel supporters implement CISC architecture so they provide that software implementation is easily. So the
hardware designing to be more complex but software coding would be relatively easy. On the other hand,
Apple supporters want the hardware to be simple and easy and software to take the major role. There for
they implement RISC based architecture.

RISC Architecture
RISC architecture based computer provide the minimum set of instructions that can handle all essential
operation and instruction complexity is reduce by the

 Having few simple instructions that are the same length and execute in single clock in RISC
 Allowed memory access only with explicit load and store instructions
Hence each instruction takes less time to complete work but execution time is different.
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Examples: – Atmel AVR, Apple, LC3, MIPS, PowerPC (IBM), SPARC (Sun)

CISC Architecture
CISC architecture based computer are designed to reduce the cost of memory because the bigger
programs requires more storage thus increasing the cost of memory and large memory becomes more
expensive. To solve these problems, the number of instructions per program can be reduced by
embedding multiple operations within a single instruction, thereby making instructions more complex.

Figure – CISC Architecture

Example: – 8085, Intel x86 and AMD processor

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CISC Characteristics

The design of an instruction set for a computer must take into consideration not only machine language
constructs, but also the requirements imposed on the use of high-level programming languages. The
translation from high-level to machine language programs is done by means of a compiler program. One
reason for the trend to provide a complex instruction set is the desire to simplify the compilation and improve
the overall computer performance. The task of a compiler is to generate a sequence of machine instructions
for each high-level language statement.

The task is simplified if there are machine instructions that implement the statements directly. The essential
goal of a CISC architecture is to attempt to provide a single machine instruction for each statement that is
written in a high-level language.

Examples of CISC architectures are the Digital Equipment Corporation VAX computer and the IBM 370
computer.

Another characteristic of CISC architecture is the incorporation of variable-length instruction

formats. Instructions that require register operands may be only two bytes in length, but instructions that
need two memory addresses may need five bytes to include the entire instruction code. If the computer has
32-bit words (four bytes), the first instruction occupies half a word, while the second instruction needs one
word in addition to one byte in the next word. Packing variable instruction formats in a fixed-length memory
word requires special decoding circuits that count bytes within words and frame the instructions according to
their byte length. the instructions in a typical CISC processor provide direct manipulation of operands residing
in memory. For example, an ADD instruction may specify one operand in memory through index addressing
and a second operand in memory through a direct addressing. Another memory location may be included in
the instruction to store the sum. This requires three memory references during execution of the instruction.
Although CISC processors have instructions that use only processor registers, the availability of other modes
of operations tend to simplify high-level language compilation. However, as more instructions and addressing
modes are incorporated into a computer, the more hardware logic is needed to implement and support
them, and this may cause the computations to slow down. In summary, the major characteristics of CISC
architecture are:

1. A large number of instructions—typically from 100 to 250 instructions

2. Some instructions that perform specialized tasks and are used infrequently

3. A large variety of addressing modes—typically from 5 to 20 different modes

4. Variable-length instruction formats

5. Instructions that manipulate operands in memory

RISC Characteristics

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The concept of RISC architecture involves an attempt to reduce execution time by simplifying the instruction
set of the computer. The major characteristics of a RISC processor are:

1. Relatively few instructions

2. Relatively few addressing modes

3. Memory access limited to load and store instructions

4. All operations done within the registers of the CPU

5. Fixed-length, easily decoded instruction format

6. Single-cycle instruction execution

7. Hardwired rather than microprogrammed control

The small set of instructions of a typical RISC processor consists mostly of register-to-register operations, with
only simple load and store operations for memory access.

Thus each operand is brought into a processor register with a load instruction. All computations are done
among the data stored in processor registers. Results are transferred to memory by means of store
instructions. This architectural feature simplifies the instruction set and encourages the optimization of
register manipulation. The use of only a few addressing modes results from the fact that almost all instructions
have simple register addressing. Other addressing modes may be included, such as immediate operands and
relative mode. By using a relatively simple instruction format, the instruction length can be fixed and aligned
on

word boundaries. An important aspect of RISC instruction format is that it is easy to decode. Thus the
operation code and register fields of the instruction code can be accessed simultaneously by the control. By
simplifying the instructions and their format, it is possible to simplify the control logic. For faster operations, a
hardwired control is preferable over a microprogrammed control.

A characteristic of RISC processors is their ability to execute one instruction per clock cycle. This is done by
overlapping the fetch, decode, and execute phases of two or three instructions by using a procedure referred
to as pipelining. A load or store instruction may require two clock cycles because access to memory takes
more time than register operations. Efficient pipelining, as well as a few other characteristics, are sometimes
attributed to RISC, although they may exist in non-RISC architectures as well. Other characteristics attributed
to RISC architecture are:

A relatively large number of registers in the processor unit Use of overlapped register windows to speed-up
procedure call and return Efficient instruction pipeline Compiler support for efficient translation of high-level
language programs into machine language programs. A large number of registers is useful for storing
intermediate results and for optimizing operand references. The advantage of register storage as opposed to
memory storage is that registers can transfer information to other registers much faster than the transfer of
information to and from memory. Thus register-to-memory operations can be minimized by keeping the most
frequent accessed operands in registers. Studies that show improved performance for RISC architecture do
not differentiate between the effects of the reduced instruction set and the effects of a large register file. For
this reason a large number of registers in the processing unit are sometimes associated with RISC processors.
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