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Control Unit –
A control unit (CU) handles all processor control signals. It directs all input and output flow, fetches
the code for instructions and controlling how data moves around the system.
The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU may need,
e.g. Addition, Subtraction, Comparisons. It performs Logical Operations, Bit Shifting Operations, and
Arithmetic Operation.
2. Program Counter (PC): Keeps track of the memory location of the next instructions
to be dealt with. The PC then passes this next address to Memory Address Register
(MAR).
4. Memory Data Register (MDR): It stores instructions fetched from memory or any
data that is to be transferred to, and stored in, memory.
5. Current Instruction Register (CIR): It stores the most recently fetched instructions
while it is waiting to be coded and executed.
6. Instruction Buffer Register (IBR): The instruction that is not to be executed
immediately is placed in the instruction buffer register IBR.
Input/Output Devices – Program or data is read into main memory from the input device or
secondary storage under the control of CPU input instruction. Output devices are used to
output the information from a computer.
Buses – Data is transmitted from one part of a computer to another, connecting all major
internal components to the CPU and memory, by the means of Buses. Types:
1. Data Bus: It carries data among the memory unit, the I/O devices, and the
processor.
2. Address Bus: It carries the address of data (not the actual data) between memory
and processor.
3. Control Bus: It carries control commands from the CPU (and status signals from
other devices) in order to control and coordinate all the activities within the
computer.
A instruction is of various length depending upon the number of addresses it contain. Generally CPU
organization are of three types on the basis of number of address fields:
3. Stack organization
The term addressing modes refers to the way in which the operand of an instruction is specified. The
addressing mode specifies a rule for interpreting or modifying the address field of the instruction
before the operand is actually executed.
IMPORTANT TERMS
Immediate addressing mode (symbol #):In this mode data is present in address field of
instruction .Designed like one address instruction format.
Note:Limitation in the immediate mode is that the range of constants are restricted by size
of address field.
Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general
purpose registers. The data is in the register that is specified by the instruction.
Here one register reference is required to access the data.
Register Indirect mode: In this addressing the operand’s offset is placed in any one of the
registers BX, BP, SI, DI as specified in the instruction. The effective address of the data is in
the base register or an index register that is specified by the instruction.
Here two register reference is required to access the data.
Auto Indexed (increment mode): Effective address of the operand is the contents of a
register specified in the instruction. After accessing the operand, the contents of this register
are automatically incremented to point to the next consecutive memory location.(R1)+.
Here one register reference, one memory reference, and one ALU operation is required to
access the data.
Auto indexed ( decrement mode): Effective address of the operand is the contents of a
register specified in the instruction. Before accessing the operand, the contents of this
register are automatically decremented to point to the previous consecutive memory
location. –(R1)
Here one register reference, one memory reference and one ALU operation is required to
access the data.
Auto decrement mode is the same as the auto-increment mode. Both can also be used to implement
a stack as push and pop. Auto increment and Auto-decrement modes are useful for implementing
“Last-In-First-Out” data structures.
Direct addressing/ Absolute addressing Mode (symbol [ ]): The operand’s offset is given in
the instruction as an 8 bit or 16 bit displacement element. In this addressing mode, the 16-
bit effective address of the data is part of the instruction.
Here only one memory reference operation is required to access the data.
Indirect addressing Mode (symbol @ or () ):In this mode address field of instruction
contains the address of effective address.Here two references are required.
1st reference to get an effective address.
2nd reference to access the data.
Indexed addressing mode: The operand’s offset is the sum of the content of an index
register SI or DI and an 8 bit or 16-bit displacement.
Based Indexed Addressing: The operand’s offset is sum of the content of a base register BX
or BP and an index register SI or DI.
Note:
1. PC relative and based register both addressing modes are suitable for
program relocation at runtime.
RISC vs CISC
Characteristic of RISC –
Characteristic of CISC –
15. Instruction may take more than single clock cycle to get executed.
16. Less number of general purpose register as operation get performed in memory itself.
Fixed logic circuits that correspond directly to the Boolean expressions are used to
generate the control signals.
Hardwired control is faster than micro-programmed control.
The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words.
Instruction Cycle
Memory Buffer Register(MBR) : It is connected to the data lines of the system bus.
It contains the value to be stored in memory or the last value read from the
memory.
PC ←(PC) + I
t3: IR ←(MBR)
Memory Organization :
Memories are made up of registers. Each register in the memory is one storage location. The storage
location is also called a memory location. Memory locations are identified using Address. The total
number of bit a memory can store is its capacity.
Based on this data storage i.e. Bytewise Based on this data storage i.e. Wordwise
storage, the memory chip configuration storage, the memory chip configuration
is named as Byte Addressable Memory. is named as Word Addressable Memory.
Simultaneous access memory organisation: If H1 and H2 are the Hit Ratios and T1 and T2 are the
access time of L1 and L2 memory levels respectively then the
Average Memory Access Time can be calculated as:
Hierarchical Access Memory Organisations: If H1 and H2 are the Hit Ratios and T1 and T2 are the
access time of L1 and L2 memory levels respectively then the
Average Memory Access Time can be calculated as:
Cache Memory
Cache Memory is a special very high-speed memory. It is used to speed up and synchronizing with
high-speed CPU.
Levels of memory: Level 1 or Register, Level 2 or Cache memory, Level 3 or Main Memory, Level 4 or
Secondary Memory.
Cache Mapping:
There are three different types of mapping used for the purpose of cache memory which is as
follows: Direct mapping, Associative mapping, and Set-Associative mapping.
Note: Translation Lookaside Buffer (i.e. TLB) is required only if Virtual Memory is used by a
processor. In short, TLB speeds up the translation of virtual address to a physical address by storing
page-table in faster memory. In fact, TLB also sits between the CPU and Main memory.
Locality of reference –
Since size of cache memory is less as compared to main memory. So to check which part of main
memory should be given priority and loaded in the cache is decided based on the locality of
reference.
Write Policy
40. Write Through: In this technique, all write operations are made to main memory as
well as to the cache, ensuring that main memory is always valid.
For hierarchical access:
41. Write Back: In write-back updates are made only in the cache. When an update
occurs, a dirty bit, or use bit, associated with the line is set. Then, when a block is
replaced, it is written back to main memory if and only if the dirty bit is set.
For hierarchical access:
Pipelining
Pipelining is a process of arrangement of hardware elements of the CPU such that its overall
performance is increased. Simultaneous execution of more than one instruction takes place in a
pipelined processor.
RISC processor has 5 stage instruction pipeline to execute all the instructions in the RISC instruction
set. Following are the 5 stages of RISC pipeline with their respective operations:
Stage 1 (Instruction Fetch)
In this stage the CPU reads instructions from the address in the memory whose
value is present in the program counter.
Stage 2 (Instruction Decode)
In this stage, instruction is decoded and the register file is accessed to get the values
from the registers used in the instruction.
ETpipeline = k + n – 1 cycles
= (k + n – 1) Tp
In the same case, for a non-pipelined processor, execution time of ‘n’ instructions will be:
ETnon-pipeline = n * k * Tp
So, speedup (S) of the pipelined processor over non-pipelined processor, when ‘n’ tasks are
executed on the same processor is:
S = ETnon-pipeline / ETpipeline
S = [n * k] / [k + n – 1]
When the number of tasks ‘n’ are significantly larger than k, that is, n >> k
S=n*k/n
S=k
So, Throughput = n / (k + n – 1) * Tp
Note: The cycles per instruction (CPI) value of an ideal pipelined processor is 1
There are mainly three types of dependencies possible in a pipelined processor. These are :
47. Structural dependency: This dependency arises due to the resource conflict in the
pipeline. A resource conflict is a situation when more than one instruction tries to
access the same resource in the same cycle. A resource can be a register, memory,
or ALU.
48. Control Dependency (Branch Hazards): This type of dependency occurs during the
transfer of control instructions such as BRANCH, CALL, JMP, etc. On many instruction
architectures, the processor will not know the target address of these instructions
when it needs to insert the new instruction into the pipeline. Due to this, unwanted
instructions are fed to the pipeline.
49. Data Dependency (Data Hazard):Data hazards occur when instructions that exhibit
data dependence, modify data in different stages of a pipeline. Hazard cause delays
in the pipeline. There are mainly three types of data hazards:
1) RAW (Read after Write) [Flow/True data dependency]
2) WAR (Write after Read) [Anti-Data dependency]
3) WAW (Write after Write) [Output data dependency]
Input/Output Organization
The input/output (I/O) architecture is computer system’s interface to the outside world. Each I/O
module interfaces to the system bus and controls one or more peripheral devices.
50. Programmed I/O: In programmed I/O, the processor executes a program that gives
its direct control of the I/O operation, including sensing device status, sending a read
or write command, and transferring the data.
51. Interrupt driven I/O: In interrupt driven I/O, the processor issues an I/O command,
continues to execute other instructions, and is interrupted by the I/O module when
the I/O module completes its work.
52. Direct Memory Access(DMA): In Direct Memory Access (DMA), the I/O module and
main memory exchange data directly without processor involvement.
There are several ways to represent floating point number but IEEE 754 is the most efficient in most
cases. IEEE 754 has 3 basic components:
Flag register
57. Carry flag (CY): After an addition of two numbers, if the sum in the accumulator is
larger than eight bits, then the flip-flop uses to indicate a carry called the Carry flag,
which is set to one.
58. Parity (P): If the result has an even number of 1s, the flag is set to 1; for an odd
number of 1s the flag is reset.
59. Auxiliary Carry (AC): In an arithmetic operation, when a carry is generated from
lower nibble and passed on to higher nibble then this register is set to 1.
60. Sign flag(S): It is a single bit in a system status (flag) register used to indicate
whether the result of the last mathematical operation resulted in a value in which
the most significant bit was set.
61. Trap Flag (TF): It sets to enable one step execution of program. This is used for
debug purpose.
62. Interrupt Flag (IF): It is used to enable or disable interrupt during execution.
63. Direction Flag (DF): The direction flag is a flag that controls the left-to-right or right-
to-left direction of string processing.