Chapter 2: 8051 Assembly Language Programming

Summary:
- 8051 Microcontrollers (MC) assembly language programming structure will be demonstrate using simple
instructions like MOV and ADD
- Assembly language terms, such as, Op-code, operand ….. will be explained.
- Line by line execution of an 8051 program and the role of program counter will be examined.
- Assembly language directives and different data types supported by the MC will be explained.
- Program status word (PSW) and Fag bits and will be discussed.
- Allocation of internal memory (ROM and RAM) will be introduced.

• Microcontroller’s Registers are used to temporarily store information of the following types:
• A data byte to be processed by ALU
• A memory address of the stored data byte, needed to be fetched/stored before/after processing

• The vast majority of 8051 register are 8-bit registers, which can only store one byte (8-bit) of data

• The 8 bits of a register are shown from MSB=D7 to the LSB=D0. With an 8-bit data type, any data larger than
8 bits must be broken into 8-bit pieces before it is processed

• The most widely used MC registers are as follows:

• A (ACCumulator) used for arithmetic and logic inst

• B, R0 (register 0) , R1, R2, R3, R4, R5, R6, R7
• DPTR (data pointer), and PC (program counter)
are the 16-bit registers of MC. PC points to the
next instruction to be executed and so on. Thus
most of 8051 can access 64K byte (0-FFFFH)
program codes. DPTR (ch5) is used in index
addressing mode of indirect mem add. Mode.

MOV destination, source; copy source to destination.

• The instruction tells the CPU to move (in reality, COPY) the source operand to the destination operand
 Register A as Destination. This can have the following formats:
1. MOV A, #data  example: MOV A, #25H after exe., 25H  A (if no Hex, consider Dec)
2. MOV A, Rn  example: MOV A, R3  after execution, byte data content of R3  A
3. MOV A, direct  example: MOV A, 30H  after exe. data contents of P.A.=30HA
4. MOV A, @Ri (i=0 or 1)  example: MOV A, @R0  after execution, data pointed by the
“PA stored in R0”  A
5. MOV A, Pn=0,1,2,3  example: MOV A, P1  after exe., byte data content of port P1  A
6. MOV R6,R2 is invalid (But MOV 6,2 is allowed, if using BANK 1)
 Register A as Source. This can have the following formats:
1. MOV Rn, A  example: MOV R3, A  after execution, byte data content of A  R3
2. MOV direct, A  example: MOV 30H, A  after exe., data contents of PA=A30H
3. MOV @Ri (i=0 or 1), A  example: MOV @R0, A  after execution, byte data contents of A
stored in the memory location whose P.A. stored in R0
4. MOV Pn=0,1,2,3, A  example: MOV P, A1  after exe., byte data content of port A port P1

1
  Register Rn as destination. This can have the following formats:
1. MOV Rn, #data  example: MOV R0, #25H 
after execution, 25H  R0
2. MOV Rn, A  example: MOV R3, A
3. MOV Rn, direct  example: MOV R0, 30H  after execution,
data contents of PA=30HR0
 Destination is DIRECT address. This can have the following formats:
1. MOV direct, #data  example: MOV 30H, #25
2. MOV direct, A  example: MOV 30H, A
3. MOV direct, Rn  example: MOV 30H, R1
4. MOV direct, direct  MOV 30H, 31H
5. MOV direct, @Ri (i=0 or 1)  example: MOV 30H, @R0
 Destination is INDIRECT address. This can have the following formats:
6. MOV @Ri (i=0 or 1), #data  example: MOV @R0, #25
7. MOV @Ri (i=0 or 1), A  example: MOV @R1, A
8. MOV @Ri (i=0 or 1), direct  MOV @R0, 31H

MOV R0,A ;copy contents of A into R0

;(now A=R0=55H)
MOV R1,A ;copy contents of A into R1
;(now A=R0=R1=55H)
MOV R2,A ;copy contents of A into R2
;(now A=R0=R1=R2=55H) SFR
MOV R3,#0F5H ;load value F5H into R3
;(now R3=F5H)
MOV A,R3 ;copy contents of R3 into A
;now A=R3=F5H
NOTE ILLEGAL or INVALID instructions:
• • “MOV A, A”  Invalid
• “MOV A, #7F2H” ; ILLEGAL: 7F2H>8 bits (FFH)  Invalid
• Value (proceeded with #) can be loaded directly to registers A, B, or R0 – R7
• “MOV A, #23H”
• If values 0 to F moved into an 8-bit register, the rest of the bits are assumed all zeros
• “MOV A, #5”, the result will be A=05; i.e., A = 00000101 in binary
RAM
• Moving a value that is too large into a register will cause an error
• ADD A, source; ADD the 8-bit source operand to the accumulator register (A) and store the result in A.
• Source operand can be either a register, immediate or memory data, but destination must always be register A
 Register A as Destination. This can have the following (initially, register-A12H, retister-R302H,
contents of memory location 30H4H, R0=35H and contents of memory location 35H03H
1. ADD A, #data  example: ADD A, #25H  after execution, (25H+12H) = 37H  A
2. ADD A, Rn  example: ADD A, R3  after execution, (37H+02H) = 39H  A
3. ADD A, direct  example: ADD A, 30H  after execution, (39H+04H) = 3DH  A
4. ADD A, @Ri (i=0 or 1)  example: ADD A, @R0  after execution, (3DH+03H) = 41H A

2
 Addition of signed ( +, -) numbers use OV flag (OV=set=1) to determine errors (either carry from D6D7
or D7 out, but not (OV=reset) if both carry’s present from D6D7 AND D7 out
• Problem: Write a program that will add 34H and 25H of byte data.

8051 Assembler (low level language)  PINNACLE or MIDE software

Assembly language provides mnemonics (abbreviated codes in English) for the machine code instructions. There
are two types of instructions in Assembly Language:
• Assembly language instructions  Assembled
 Machine code for CPU exe  This tells
the CPU what to do EDIT or
• Directives (or pseudo-instructions)   give Notepad
directions to the assemblers (translator)
• The step of Assembly language program are outlines as follows: myfile.src

1) First we use an editor to type a program, many excellent editors Source Code
or word processors are available that can be used to create
and/or edit the program 8051
assembler
• Notice that the editor must be able to produce an ASCII file
• For many assemblers, the file names follow the usual DOS
conventions, but the source file has the extension “asm“ or
“src”, depending on which assembly you are using Machine Code
this file lists all
2) The “asm” source file containing the program code the Op-codes,
created in step 1 is fed to an 8051 assembler P. Addresses &
• Assembler converts instructions into machine code Assembler
• The assembler will produce an object and a list files errors (pg 45)
• The extension for the object file is “obj” while the
extension for the list file is “lst”
3) Assembler require a third step called linking
• The linker program takes one or more object code files and
produce an absolute object file with the extension “abs”
• This abs file is used by 8051 trainers that have a monitor
Object to Hex
program
Convert.
4) Next the “abs” file is fed into a program called “OH” (object to
hex converter) which creates a file with extension “hex” that is
ready to burn into ROM
• This program comes with all 8051 assemblers
• Recent Windows-based assemblers combine step 2
through 4 into one step.

3
Two Assembly language instructions exists: (1) That is assembled and (2) that is not assembled
Directives/Pseudo-instructions  Not assembled (instruction for CPU. Ex: “ORG 00H” or “END”
instructions (some MC use .ORG)  already discussed in 8088/8086 case.

Memory physical Adresses Machine Codes Op-codes and Operands

Psedo-op

• The program counter points to the address of the next instruction to be executed
• Program counter (PC) is 16 bits wide (access 64K code) and auto increments after execution to point next ins.
• This means that it can access program addresses 0000 to FFFFH, a total of 64K bytes of code
• When powered up, all 8051 members start at memory address 0000 as P.C=0000H. This means the first op-code
to be executed is burned into ROM address 0000H and this is achieved by the ORG Directive in program code
ROM spaces: 8051 family has different on-chip ROM (up to 64 KB) for internal storage:
- Such as: AT89C51  4 Kbyte (KB); AT89C52  8 KB; DS89C420  16 KB; DS5000  32 KB;
• ‘DB’  Directives/Pseudo to initialize data:
- Same as 8086/8088 programming, the DB instruction can be used as follows: (remember need use ‘H’ for hex data)
ORG 500H
DATA1: DB 28 ; 1CH will be stored in PA=500H
DATA2: DB “25” ; ASCII code of 32H and 35H will be stored  see table – next page
DATA3: DB “My Name is Ahmed” ; will store the ASCII codes of each ASCII letter.

• ASCII (American Standard Code for Information Interchange (next page):

• 0 1 2 3 4 5 6 7 8 9 A B C D E F
• 0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI
• 1 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS GS RS US
• 2 SP ! " # $ % & ' ( ) * + , - . /
• 3 0 1 2 3 4 5 6 7 8 9 : ; < = > ?
• 4 @ A B C D E F G H I J K L M N O
• 5 P Q R S T U V W X Y Z [ \ ] ^ _
• 6 ` a b c d e f g h i j k l m n o
• 7 p q r s t u v w x y z { | } ~ DEL
•

4
ORG (origin)  Directives/Pseudo
• The ORG directive is used to indicate the beginning of the address
• The number that comes after ORG can be either in hex and decimal
• If the number is not followed by H, it is decimal and the assembler will convert it to hex
• END  Directives/Pseudo
• This indicates to the assembler the end of the source (asm) file
• The END directive is the last line of an 8051 program
• Mean that in the code anything after the END directive is ignored by the assembler
• EQU (equate)  Directives/Pseudo This is used to define a constant without occupying a memory location
• This directive does not set aside storage for a data item but associates a constant value with a data label
• Can be changed in all the cases within the program by changing the definition

Section 2.6: 8051 FLAG bits and the PSW (program status word) Register:
• PSW or Program Status Word register, also referred to as the flag register, is an 8 bit register
• Six-bits out of eight-bits are used: four-bits are for conditional flags (PSW.7, PSW.6, PSW.2, PSW.0),
two-bits are used to change register banks (PSW.4, PSW.3) and two-bits are used for user defined general
purpose status flag bits (PSW.5, PSW.1).
• Out of 128D=7FH Byte RAM memory, 00H to 1FH (or 32D) bytes are used for Register Banks

Used with ADD/SUB for JC/JNC: SETB C  set bit carry; CLR C  clear carry

Used to perform BCD arithmetic; Carry from D3 to D4.

Errors in Signed operation  too large causing data to go to sign-bit

(Reg A only)

5
 Ex1: Find how flags are affected for following two
line program: 0 1
MOV A, #38H  00111000B
ADD A, #2FH  00101111B
------------------------
register A  01100111 B

the updated flag bits of PSW register are:

CF  ‘0’ or NC
AF  ‘1’ or AC
PF  ‘1’ or PO == this is for 8051

Ex2: Find how flags are affected for following

program :
MOV A, #9CH  10011100
Delete this
ADD A, #64H  01100100
CF box
 ‘1’ = cy to see
AF  ‘1’ = ac
PF answers
 ‘0’ = PE
ZF  ‘1’ = ‘ZR or zero’  set

(1) MOV R1, #07H ; R107H of Bank 0 (default)

(2) INC 30H ; increment mem content by 1 of Address 30H
(3) DEC @R1 ;decrement mem content by 1 of address 07H
- Selection of Bank 1, 2, 3 as default for Rn (0 to 7)
(4) SETB PSW.3  select Bank 1 (initially 0’s)
- remember PSW is bit addressable register in SFR
(5) now, MOV R1, #07H same as MOV 09, #07H

6
- So there is a problem of programming 8051 as BANK-1 uses the same RAM spaces of STACK. So we must not
use both at a time or use another RAM array to allocate for STACK (using SP register  see pinnacle 52)

So if bank-1 is selected 
MOV R1, #07H
is same as
MOV 09, #07H
As we have preciously
selected BANK-1 with
following instruction:
SETB PSW.3
- We need to move
STACK using “SP” reg

- SP register of CPU (default value=07H) access Bank 1 memory locations as 24 bytes of temporary stack.
7
Use of STACK Segment (default Bank 1): to temporary store data.
- PUSH  (a) SPnew=SP+1; (b) Load Rn contents into PA SPnew .
- POP (a) load Rn contents, (b) SPnew=SP-1;
- If Bank-1 and STACK are both needed by program, then default SP=07H (PA08H to 1FH, 24 Bytes) cannot
be used. Other RAM locations are used as STACK MOV SP, #5FH  PA of 1st stack location is 60H

Memory physical
Adresses

LAB Simulators:

8
Register A (Accumulator)
The most important of all special function registers, that’s the first comment about Accumulator which is also
known as ACC or A. The Accumulator (sometimes referred to as Register A also) holds the result of most of
arithmetic and logic operations. ACC is usually accessed by direct addressing and its physical address
isE0H. Accumulator is both byte and bit addressable. You can understand this from the figure shown below. To
access the first bit (i.e bit 0) or to access accumulator as a single byte (all 8 bits at once), you may use the same
physical address E0H. Now if you want to access the second bit (i.e bit 1), you may use E1H and for third bit E2H
and so on.

Register B
The major purpose of this register is in executing multiplication and division. The 8051 micro controller has a
single instruction for multiplication (MUL) and division (DIV). If you are familiar with 8085, you may now
know that multiplication is repeated addition, where as division is repeated subtraction. While programming
8085, you may have written a loop to execute repeated addition/subtraction to perform multiplication and
division. Now here in 8051 you can do this with a single instruction.
Ex: MUL A,B – When this instruction is executed, data inside A and data inside B is multiplied and answer is
stored in A.
Note: For MUL and DIV instructions, it is necessary that the two operands must be in A and B.
Note: Follow this link if you are interested in knowing about differences between a microprocessor and
microcontroller.
Register B is also byte addressable and bit addressable. To access bit o or to access all 8 bits (as a single byte),
physical address F0 is used. To access bit 1 you may use F1 and so on. Please take a look at the picture below.

Note: Register B can also be used for other general purpose operations.

Port Registers
As you may already know, there are 4 ports for 8051. If you are unfamiliar of the architecture of 8051 please read
the following article:- The architecture of 8051
So 4 Input/Output ports named P0, P1, P2 and P3 has got four corresponding port registers with same name P0,
P1, P2 and P3. Data must be written into port registers first to send it out to any other external device through
ports. Similarly any data received through ports must be read from port registers for performing any operation. All

9
4 port registers are bit as well as byte addressable. Take a look at the figure below for a better understanding of
port registers.

From the figure:-

 The physical addresses of port 0 is 80, port 1 is 90, port 2 is A0, port 3 is B0

Stack Pointer
Known popularly with an acronym SP, stack pointer represents a pointer to the the system stack. Stack pointer is
an 8 bit register, the direct address of SP is 81H and it is only byte addressable, which means you cant access
individual bits of stack pointer. The content of the stack pointer points to the last stored location of system stack.
To store something new in system stack, the SP must be incremented by 1 first and then execute the “store”
command. Usually after a system reset SP is initialized as 07H and data can be stored to stack from 08H onwards.
This is usually a default case and programmer can alter values of SP to suit his needs.

Power Management Register (PCON)

Power management using a microcontroller is something you see every day in mobile phones. Haven’t you
noticed and got wondered by a mobile phone automatically going into stand by mode when not used for a couple
of seconds or minutes ? This is achieved by power management feature of the controller used inside that phone.
As the name indicates, this register is used for efficient power management of 8051 micro controller. Commonly
referred to as PCON register, this is a dedicated SFR for power management alone.

10
From the figure below you can observe that there are 2 modes for this register :- Idle mode and Power down
mode.

Setting bit 0 will move the micro controller to Idle mode and Setting bit 1 will move the micro controller to
Power down mode.

Processor Status Word (PSW)

Commonly known as the PSW register, this is a vital SFR in the functioning of micro controller. This register
reflects the status of the operation that is being carried out in the processor. The picture below shows PSW register
and the way register banks are selected using PSW register bits – RS1 and RS0. PSW register is both bit and byte
addressable. The physical address of PSW starts from D0H. The individual bits are then accessed using D1, D2 …
D7. The various individual bits are explained below.

Bit No Bit Direct Name Function

Symbol Address
0 P D0 Parity This bit will be set=’1’, if ACC has odd
number of 1’s after an operation. If not, bit
will remain cleared.
1 - D1 User definable bit
2 OV D2 Overflow OV flag is set if there is a carry from bit 6
but not from bit 7 of an Arithmetic
operation. It’s also set if there is a carry from
bit 7 (but not from bit 6) of Acc

11
3 RS0 D3 Register LSB of the register bank select bit. Look for
Bank explanation below this table.
select bit 0
4 RS1 D4 Register MSB of the register bank select bits.
Bank
select bit 1
5 F0 D5 Flag 0 User defined flag
6 AC D6 Auxiliary This bit is set if data is coming out from bit 3
carry to bit 4 of Acc during an Arithmetic
operation.
7 CY D7 Carry Is set if data is coming out of bit 7 of Acc
during an Arithmetic operation.
At a time registers can take value from R0,R1…to R7. You may already know there are 32 such registers. So how
you access 32 registers with just 8 variables to address registers? Here comes the use of register banks. There are
4 register banks named 0,1,2 and 3. Each bank has 8 registers named from R0 to R7. At a time only one register
bank can be selected. Selection of register bank is made possible through PSW register bits PSW.3 and PSW.4,
named as RS0 and RS1.These two bits are known as register bank select bits as they are used to select register
banks. The picture will talk more about selecting register banks.

So far we have discussed about all major SFR’s in 8051. There are many others. Please remember there are 21
SFR’s and we have discussed only 9 specifically. The table below lists all other 12 SFR’s.

12
 SFR Physical Function
Special Address
DPH 83 Data pointer registers (High). Only byte addressing
possible.
DPL 82 Data pointer register (Low). Only byte addressing
possible.
IP B8 Interrupt priority. Both bit addressing and byte
addressing possible.
IE A8 Interrupt enable. Both bit addressing and byte addressing
possible.

SBUF 99 Serial Input/Output buffer. Only byte addressing is possible.

SCON 98 Serial communication control. Both bit addressing and

byte addressing possible.

TCON 88 Timer control. Both bit addressing and byte addressing possible.

TH0 8C Timer 0 counter (High). Only byte addressing is possible.

TL0 8A Timer 0 counter (Low). Only byte addressing is possible.

TH1 8D Timer 1 counter (High). Only byte addressing is possible.

TL1 8B Timer 1 counter (Low). Only byte addressing is possible.

13
TMOD 89 Timer mode select. Only byte addressing is possible.

14
15
16
17
18
19