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######set_lef_files###########
set init_lef_file
{/home/sumpd26/srikanth_pudhari/alu_project/pnr/inputs/pnr_inputs/lef/gpdk090_9lm.lef
/home/sumpd26/srikanth_pudhari/alu_project/pnr/inputs/pnr_inputs/lef/gsclib090_fromOA.lef
/home/sumpd26/srikanth_pudhari/alu_project/pnr/inputs/pnr_inputs/lef/gsclib090_macro.lef}
######set_netlist_file#########
set init_verilog
/home/sumpd26/srikanth_pudhari/alu_project/synthesis/ALU/mappednewalumul.vg
#######set_viewdefinition_file######
set init_mmmc_file
/home/sumpd26/srikanth_pudhari/alu_project/pnr/inputs/pnr_inputs/viewDefinition.tcl
set init_pwr_net VDD
init_design
########SANITY_CHECKS############
checkDesign -netlist
checkDesign -PhysicalLibrary
checkdesign -timingLibrary
check_timing
timeDesign -preplace
###############
floorPlan -site gsclib090site -r 0.958384332925 0.699976 2 2 2 2
checkDesign -floorplan
#########PIN_PLACEMENT###########
editPin -fixOverlap 1 -unit MICRON -spreadDirection clockwise -side Top -layer 8
-spreadType start -spacing 0.2 -start 0.0 0.0 -pin {{a[0]} {a[1]} {a[2]} {a[3]} {a[4]} {a[5]} {a[6]}
{a[7]} {a[8]} {adda[0]} {adda[1]} {adda[2]} {adda[3]} {adda[4]} {adda[5]} {adda[6]} {adda[7]}
{adda[8]} {addb[0]} {addb[1]} {addb[2]} {addb[3]} {addb[4]} {addb[5]} {addb[6]} {addb[7]}
{addb[8]} {b[0]} {b[1]} {b[2]} {b[3]} {b[4]} {b[5]} {b[6]} {b[7]} {b[8]} {c[0]} {c[1]} {c[2]} {c[3]} {c[4]}
{c[5]} {c[6]} {c[7]} {c[8]} ci clk co {d[0]} {d[1]} {d[2]} {d[3]} {d[4]} {d[5]} {d[6]} {d[7]} {d[8]} I1 I2
orAll_r powerDwn {q[0]} {q[1]} {q[2]} {q[3]} {q[4]} {q[5]} {q[6]} {q[7]} {q[8]} {q[9]} {q[10]} {q[11]}
{q[12]} {q[13]} {q[14]} {q[15]} {q[16]} {q[17]} rst se si so {sumab[0]} {sumab[1]} {sumab[2]}
{sumab[3]} {sumab[4]} {sumab[5]} {sumab[6]} {sumab[7]} {sumab[8]} {sumab[9]} taiwan TE
TRI}
#legalize_Pin########
legalizePin
########TO_VERIFY_PIN_PLACEMENT#######
checkPinAssignment
#########adding Global_nets########
globalNetConnect VDD -type pgpin -pin VDD
globalNetConnect VSS -type pgpin -pin VSS
######special routes########
sroute
#######TO_ADD_METAL_LAYERS#########
addStripe -nets {VDD VSS} -layer Metal9 -direction horizontal -width 0.7 -spacing 0.7
-set_to_set_distance 13.1 -start_offset 5.34
setAddStripeMode -stacked_via_bottom_layer M8 -stacked_via_top_layer M9
addStripe -nets {VDD VSS} -layer Metal8 -direction vertical -width 0.7 -spacing 0.7
-set_to_set_distance 18 -start_offset 6
setAddStripeMode -stacked_via_bottom_layer M7 -stacked_via_top_layer M8
addStripe -nets {VDD VSS} -layer Metal7 -direction horizontal -width 0.465 -spacing 0.465
-set_to_set_distance 8.55 -start_offset 3.2
setAddStripeMode -stacked_via_bottom_layer M6 -stacked_via_top_layer M7
addStripe -nets {VDD VSS} -layer Metal6 -direction vertical -width 0.465 -spacing 0.465
-set_to_set_distance 12 -start_offset 4
setAddStripeMode -stacked_via_bottom_layer M5 -stacked_via_top_layer M6
addStripe -nets {VDD VSS} -layer Metal5 -direction horizontal -width 0.24 -spacing 0.24
-set_to_set_distance 6 -start_offset 1.8
setAddStripeMode -stacked_via_bottom_layer M4 -stacked_via_top_layer M5
#########TO_ENDCAP#####
addEndCap -preCap FILL4 -postCap FILL4 -prefix ENDCAP
#########palce_design####
placeDesign -noPrePlaceOpt
##########verify_PG_short####
verify_PG_short
verifyConnectivity
verify_drc
report_timing
reportRoute
reportSpecialRoute
############check_timing_slacks_pre_cts#########
#####setup_slack######
timeDesign -preCTS
#######hold_slack#####
timeDesign -preCTS -hold
#####congestion###
describeCongestion
reportCongestion
reportCongestion -hotspot
reportCongestion -overflow
reportDensityMap
############TO_opt_design###################
place_opt_design
verify_PG_short
verifyConnectivity
verify_drc
report_timing
reportRoute
reportSpecialRoute
#####congestion###
describeCongestion
reportCongestion
reportCongestion -hotspot
reportCongestion -overflow
reportDensityMap
############check_timing_slacks_pre_cts#########
#####setup_slack######
timeDesign -preCTS
#######hold_slack#####
timeDesign -preCTS -hold
#########################################################################
#################CTS#####################################################
#########################################################################
##################
###########Non_Default_Rules Adding#####################
add_ndr -width_multiplier {M9:M8 2} -spacing_multiplier {M9:M8 2} -name top_route_ndr
add_ndr -width_multiplier {M7:M6 2} -spacing_multiplier {M7:M6 2} -name trunk_route_ndr
add_ndr -width_multiplier {M5:M4 2} -spacing_multiplier {M5:M4 2} -name leaf_route_ndr
source alu.spec
ccopt_design -cts
###########setup&hold checking###############
timeDesign -postCTS
timeDesign -postCTs -hold
##sanity checks##
#########################################################################
################ROUTING#################################################
#########################################################################
###################
#######################ENABLE_CPPR########
setAnalysisMode -analysisType onChipVariation -cppr both
###########setup&hold checking###############
timeDesign -postCTS
timeDesign -postCTs -hold
###########Generating_def#######
defOut myAlu.def
########Generating_SPEF#########
rcOut -spef myalu.spef
#########Generating_GDS#########
streamOut myalu