Computer Architecture and

Organization
Chapter 2
Lecture 1

The CPU
 Chapter 2 – The CPU
✓In this chapter:
✓Review of computer arithmetic
✓Instruction sets
✓Processor structure and function
✓The control unit
✓RISC?
 Computer Arithmetic
✓ Concerns:
✓ The way in which numbers are represented (binary format)
✓ Algorithms used for basic operations (add, subtract, multiply,
divide)
✓ Commonly performed on two different types of
numbers:
✓ Integer
✓ Floating point
 The ALU

✓ALU:
✓Part of computer that performs arithmetic and logical
operations on data
✓All other components are there to serve ALU
✓Core of the computer
✓Based on simple digital logic devices that can store
binary digits and perform simple Boolean logic
operations
 The ALU
✓How the ALU is interconnected:
✓Inputs and outputs
Control Flags
unit
ALU
Registers Registers

✓ Control unit:
✓ provides signals that control operation of ALU & movement
of data into and out of ALU
✓ Registers:
✓ present data to ALU and store results of operation
✓ Flags:
✓ set as a result of an operation E.g. if overflow happen
 Integer Representation
✓ Binary number system: arbitrary number can be
represented by digits 0 & 1, sign, and point
E.g -1101.01012 = -13.312510
✓ For storage and processing,
✓Only 0 & 1 used to represent numbers
✓ E.g. 8 bit word for non-negative integers:
✓00000000 = 0
✓00000001 = 1
✓00101001 = 41
✓11111111 = 255
 Integer Representation
✓ In general, if n bit sequence of binary digits
an-1an-2 … a1a0 is interpreted as unsigned integer A, its
value is:
n −1
A =  2 ai i

i =0

✓ Several alternatives to represent signed integers

✓ All involve treating MSB as sign bit
✓ if 0 +ve
✓ if 1 -ve
 Integer Representation
✓Signed-Magnitude Representation
✓Simplest form of representation
✓In an n-bit word, rightmost n-1 bits hold
magnitude
✓In general,
 n−2 i
 2 ai if an−1 = 0
 i =0
A =  n−2
− 2i a
 
 i =0
i if an−1 = 1
 Integer Representation

✓Drawbacks:
✓Signs and magnitudes should be considered in
addition and subtraction
✓Two representations of 0:
✓+010 = 00000000
✓-010 = 10000000
✓Which is difficult to test for 0
✓Because of these drawbacks, it is rarely used
 Integer Representation

✓Twos Complement Representation

✓The most common scheme
✓Uses MSB as sign bit
✓It differs in the way the other bits are interpreted
✓Mostly focuses on rules of producing negative
numbers
 Integer Representation
✓ Characteristics of twos complement representation
and arithmetic
Range -2n-1 through 2n-1 – 1
No of representations of One
zero
Negation Take the Boolean complement of each bit of
the corresponding positive number, then add 1
to the resulting bit pattern viewed as an
unsigned integer
Expansion of bit length Add additional bit positions to the left and fill
in with the value of the original sign bit
Overflow rule If two numbers with the same sign (both
positive or both negative) are added, then
overflow occurs if and only if the result has
the opposite sign
Subtraction rule To subtract B from A, take the twos
complement of B and add it to A
 Integer Representation

✓In general, for both +ve and –ve numbers,

✓Twos complement:
n−2
n −1
A = − 2 an−1 + 2 a
i =0
i
i

✓ The most –ve twos complement no that can be

represented is -2n-1
✓ The largest +ve no that can be represented is +2n-1 -1
✓ Although twos comp seems awkward, it is universally
used as processor representation for integers
 Integer Representation
✓Converting b/n two different bit lengths
✓To store n-bit integer in m bits, m>n
✓In sign magnitude: move sign bit to leftmost
and fill with 0s
✓E.g +18 = 00010010 (8 bits)
+18 = 0000000000010010 (16 bits)
-18 = 10010010 (8-bits)
-18 = 1000000000010010 (16 bits)
✓Twos complement: move sign bit to leftmost
and fill in with copies of sign bit (called sign
extension)
✓E.g -18 = 11101110 (8 bits)
-18 = 1111111111101110 (16 bits)
 Integer Arithmetic
✓Negation
✓Sign-magnitude: invert sign bit
✓Twos complement:
1. Take Boolean complement of each bit
2. Treating result as unsigned, add 1
✓E.g.
+18 = 00010010
Bitwise compliment = 11101101
+ 1
11101110 = -18
 Integer Arithmetic
✓Special cases:
✓For A = 0
✓E.g. consider 8-bit representation:
0 = 00000000 (twos complement)
Bitwise comp = 11111111
+ 1
100000000 = 0
✓The carry out of msb is ignored; so negation of
0 is 0
 Integer Arithmetic
✓For a bit pattern of 1 followed by n-1 zeros:
✓Same no is obtained
✓Which is a problem
✓E.g.
-128 = 10000000 (twos complement)
Bitwise comp = 01111111
+ 1
10000000 = -128
This anomaly is unavoidable; this is because there is
no representation for +2n-1 in twos complement
 Addition and Subtraction
✓Addition proceeds as if the two numbers were
unsigned integers
1001 = -7 1100 = -4
✓ E.g. +0101 = 5 +0100 = 4
1110 = -2 0000 = 0
(a) (-7) + (+5) (b) (-4) + (+4)
0011 = 3 1100 = -4
+0100 = 4 +1111 = -1
0111 = 7 1011 = -5
(c) +3) + (+4) (d) (-4) + -1)
0101 = 5 1001 = -7
+0100 = 4 +1010 = -6
1001 = overflow 0011 = overflow
(e) +5) + (+4) (f) (-7) + (-6)
 Addition and Subtraction
✓ If result is +ve, a +ve no in twos complment form
is obtained (same as unsigned-int)
✓ If –ve, -ve no in twos complement
✓ Cary bit beyond end of the word ignored
✓ Overflow: – when result is larger than can be held
in the word size being used
✓When occurs, ALU must signal it so that no
attempt is made to use the result
✓Overflow rule:
✓If two nos with same size are added, overflow
occurs if and only if result has opposite sign
 Addition and Subtraction

✓Subtraction rule:
✓To subtract one number (subtrahend) from another
(minuend), take the twos complement (negation)
of the subtrahend and add it to the minuend.
 Addition and Subtraction
0010 = 2 0101 = 5
✓Examples: +1001 = -7
1011 = -5
+1110 = -2
0011 = 3

(a) M = 2 = 0010 (b) M = 5 = 0101

S = 7 = 0111 S = 2 = 0010
-S = 1001 -S = 1110
1011 = -5 0101 = 5
+1110 = -2 +0010 = 2
1001 = -7 0111 = 7

(c) M = -5 = 1011 (d) M = 5 = 0101

S = 2 = 0010 S = -2 = 1110
-S = 1110 -S = 0010
0111 = 7 1010 = -6
+0111 = 7 +1100 = -4
1110 = overflow 0110 = overflow

(e) M = 7 = 0111 (a) M = -6 = 1010

S = -7 = 1001 S = 4 = 0100
-S = 0111 -S = 1100
 Addition and Subtraction
✓ Block diagram of Hardware for Addition and Subtraction
✓ Shows data paths and HW elements needed

B Register A Register

Complementer

SW

OF Adder
 Multiplication
✓ Complex operation (both in HW and SW)
✓ Wide variety of algorithms have been used
✓ Unsigned integers:
✓Successive shift and add :– generate partial
products one for each digit in multiplier
✓E.g. Multiplication of unsigned binary integers
1011 multiplicand (11)
x 1101 multiplier (12)
1011
0000
1011 partial products
1011
10001111 product (143)
 Multiplication
✓Partial products: when multiplier bit = 0,
pp=0; when 1, pp = multiplicand
✓Total product is produced by summing pps
✓Multiplication of two n-bit binary integers
results in a product up to 2n bits in length
 Multiplication
✓Hardware implementation
Flowchart
Example
 Generally
✓ The operation of the multiplier is as follows.
✓ Control logic reads the bits of the multiplier one at a time.
If is 1, then the multiplicand is added to the A register
and the result is stored in the A register, with the C bit used
for overflow.
✓ Then all of the bits of the C, A, and Q registers are shifted
to the right one bit, so that the C bit goes into goes into and
is lost. If is 0, then no addition is performed, just the shift.
✓ This process is repeated for each bit of the original
multiplier.
✓ The resulting -bit product is contained in the A and Q
registers.
 Reading Assignment
✓Multiplication: two’s compliment
multiplication
✓Text:- page 319
✓Division:
✓Floating point