Arc Chap3

Bahir Dar University
Faculty of Electrical and Computer

Engineering
Computer Architecture and Organization

[CoEg3091]
Chapter Three
The CPU
23-Oct-16
The CPU 2
In this chapter:
 Review of computer arithmetic
 Instruction sets
 Processor structure and function
 The control unit
23-Oct-16
Computer Arithmetic 3
Concerns:
 The way in which numbers are represented
(binary format)
 Algorithms used for basic operations (add,
subtract, multiply, divide)
Commonly performed on two different types of
numbers:
 Integer
 Floating point
 Representation chosen is crucial issue
23-Oct-16
The ALU 4
ALU:
 Part of computer that performs arithmetic and
logical operations on data
 All other components are there to service ALU
 Core of the computer
 Based on simple digital logic devices that can
store binary digits and perform simple Boolean
logic operations
23-Oct-16
The ALU 5
How the ALU is interconnected:

 Inputs and outputs
Control Flags
unit
ALU
Registers Registers
 Control unit:
 provides signals that control operation of ALU & movement
of data into and out of ALU
 Registers:
 present data to ALU and store results of operation
 Flags:
 set as a result of an operation
23-Oct-16
Integer representation 6
In binary number system, arbitrary numbers can be

represented by digits 0 & 1, sign, and point
 E.g -1101.01012 = -13.312510
For purpose of computer storage and processing,
only 0 & 1 used to represent numbers.
E.g. non-negative integers :
 00000000 = 0
 00000001 = 1
 00101001 = 41
 11111111 = 255
23-Oct-16
In general, if n bit sequence of binary digits

an-1an-2 … a1a0 is interpreted as unsigned integer A,
its value is: n 1
A   2 ai i
i 0
Several alternatives to represent signed integers

All involve treating most significant bit (msb) as sign
bit
23-Oct-16
Signed-Magnitude Representation
 Simplest form of representation
 In an n-bit word, rightmost n-1 bits hold
magnitude
 In general,
 n2 i
 2 ai if an1  0
 i 0
A   n2
 2i a
 
 i 0
i if an1  1
23-Oct-16
Drawbacks:
 Signs and magnitudes should be considered in
addition and subtraction
 Two representations of 0:
+010 = 00000000
-010 = 10000000
Which is difficult to test for 0
 Because of these drawbacks, it is rarely used
23-Oct-16
Twos Complement Representation

 The most common scheme
 Uses msb as sign bit
 It differs in the way the other bits are interpreted
 Mostly focuses on rules of producing negative
numbers
23-Oct-16
Characteristics of twos complement representation

and arithmetic
Range -2n-1 through 2n-1 – 1
No of representations of zero One
Negation Take the Boolean complement of each bit of
the corresponding positive number, then add 1
to the resulting bit pattern viewed as an
unsigned integer
Expansion of bit length Add additional bit positions to the left and fill
in with the value of the original sign bit
Overflow rule If two numbers with the same sign (both
positive or both negative) are added, then
overflow occurs if and only if the result has the
opposite sign
Subtraction rule To subtract B from A, take the twos
23-Oct-16 complement of B and add it to A
In general, for both +ve and –ve numbers,

 Twos complement: n2
n1
A   2 an1  2 a
i 0
i
i
The most –ve twos complement number that can

be represented is -2n-1
the largest +ve number that can be represented is
+2n-1 -1
Although twos complement seems awkward, it is
universally used as processor representation for
integers
23-Oct-16
Converting b/n two different bit lengths

 To store n-bit int in m bits, m>n
 In sign magnitude: move sign bit to leftmost and fill
with 0s
 E.g +18 = 00010010 (8 bits)
+18 = 0000000000010010 (16 bits)
-18 = 10010010 (8-bits)
-18 = 1000000000010010 (16 bits)
 Twos complement: move sign bit to leftmost and fill in
with copies of sign bit (called sign extension)
 E.g - 18 = 11101110 (8 bits)
23-Oct-16 -18 = 1111111111101110 (16 bits)
Integer Arithmetic 14
Negation
 Sign-magnitude: invert sign bit
 Twos complement:
 Take Boolean complement of each bit
 Treating result as unsigned, add 1
 E.g.
00010010
Bitwise complement, 11101101
+ 1
23-Oct-16 11101110 = -18
Special cases:
 For A = 0
 E.g. consider 8-bit representation:
0 = 00000000 (twos complement)
Bitwise comp = 11111111
+ 1
100000000 = 0
 The carry out of msb is ignored; so
negation of 0 is 0
23-Oct-16
 For a bit pattern of 1 followed by n-1 zeros:

 Same no is obtained
 Which is a problem
 E.g.
-128 = 10000000 (twos complement)
Bitwise comp = 01111111
+ 1
100000000 = -128
 This anomaly is unavoidable; this is because
there is no representation for +2n-1 in twos
23-Oct-16 complement
Addition and Subtraction 17
Addition proceeds as if the two nos were

unsigned integers
E.g. 1001 = -7 1100 = -4
+0101 = 5 +0100 = 4
1110 = -2 0000 = 0
(a) (-7) + (+5) (b) (-4) + (+4)
0011 = 3 1100 = -4
+0100 = 4 +1111 = -1
0111 = 7 1011 = -5
(c) +3) + (+4) (d) (-4) + -1)
0101 = 5 1001 = -7
+0100 = 4 +1010 = -6
1001 = overflow 0011 = overflow
(e) +5) + (+4) (f) (-7) + (-6)
23-Oct-16
If result is +ve, a +ve no in twos compl form is

obtained (same as unsigned-int)
If –ve, -ve no in twos complement
Cary bit beyond end of the word ignored
Overflow – when result is larger than can be held in
the word size being used
 When occurs, ALU must signal it so that no
attempt is made to use the result
 Overflow rule:
 If two nos with same size are added, overflow
23-Oct-16 occurs if and only if result has opposite sign
Subtraction rule:
 To subtract one no (subtrahend) from
another (minuend), take the twos
complement (negation) of the subtrahend
and add it to the minuend.
23-Oct-16
0010 = 2 0101 = 5
Examples: +1001 = -7 +1110 = -2
1011 = -5 0011 = 3
(a) M = 2 = 0010 (b) M = 5 = 0101

S = 7 = 0111 S = 2 = 0010
-S = 1001 -S = 1110
1011 = -5 0101 = 5
+1110 = -2 +0010 = 2
1001 = -7 0111 = 7
(c) M = -5 = 1011 (d) M = 5 = 0101

S = 2 = 0010 S = -2 = 1110
-S = 1110 -S = 0010
0111 = 7 1010 = -6
+0111 = 7 +1100 = -4
1110 = overflow 0110 = overflow
(e) M = 7 = 0111 (a) M = -6 = 1010

S = -7 = 1001 S = 4 = 0100
23-Oct-16 -S = 0111 -S = 1100
Block diagram of Hardware for Addition and

Subtraction
 Shows data paths and HW elements needed
B Register A Register
Complementer
SW
OF Adder
23-Oct-16
Multiplication 22
Complex operation (both in HW and SW)

Wide variety of algorithms have been used
Unsigned integers:
 Successive shift and add – generate partial
products one for each digit in multiplier
 E.g. multiplication of unsigned binary integer
1011 multiplicand (11)
x 1101 multiplier (12)
1011
0000
1011 partial products
1011
10001111 product (143)
23-Oct-16
Multiplication 23
Partial products: when multiplier bit = 0,

pp=0; when 1, pp = multiplcand
Total product is produced by summing pps
Multiplication of two n-bit binary integers
results in a product up to 2n bits in length
23-Oct-16
Multiplication 24
Hardware implementation
23-Oct-16
Reading Assignment 25
Multiplication:
 Text: pp 302 – 317
Floating point Arithmetic:
 Text: pp317 – 328
23-Oct-16
Micro Operations 26
A computer executes a program of instructions (or

instruction cycles)
The execution of an instruction involves a sequence of
substeps, generally called cycles.
Each instruction cycle has a number of steps or phases:
- Fetch,
- Indirect (if specified),
- Execute,
- Interrupt (if requested)
Each cycle is in turn made up of a sequence of more
fundamental operations, called micro operations which are
functional or atomic operations of a CPU.
23-Oct-16
27
The figure - depicts execution of a program which consists

of sequential execution of instructions.
23-Oct-16
Micro operations (µops) 28
Examples of µops:
 Shift, count, clear, load, increment
4 categories:
 Register transfer µops
 Arithmetic µops
 Logic µops
 Shift µops
23-Oct-16
Microoperations (µops) 29
Register transfer µops

 Transfer binary information from one register to
another
 Do not change information content
 Registers are named by capital letters to denote
functions: e.g. MAR, IR, PC, …
 Information transfer from one register to another:
R2R1
 Transfer has to occur only under predetermined
control condition that can be shown by if-then stmt:
 If (p = 1) then (R2R1) p – control signal
23-Oct-16
Example: Implementation of controlled transfer

P: R2 R1
Block diagram Control P Load

R2 Clock
Circuit
n
R1
Timing diagram t t+1
Clock
Load
Transfer occurs here
23-Oct-16
Bus and memory transfers

 A common bus system consists of a set of common
lines one for each bit of a register
 One way of construction: using multiplexers which
select source register whose binary info is placed on the
bus
 E.g BUS R
4*1 4*1 4*1 4*1
MUX 3 MUX 2 MUX 1 MUX 0
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
23-Oct-16
In general, a bus system will multiplex k registers of

n bits each to produce n-line bus
No of muxes required = n; size of each = k*1
 E.g. for 8 registers of 16 bits each = 16 muxes of
8x1 with 3 select lines
 Transfer of info:
 Connect bus lines to i/ps of all destination
registers
 Activate Load control of particular
destination register
23-Oct-16
Memory Transfer:
 Read operation – from M to outside:
Read: DR M[AR]
 Write operation – new info to M:
Write: M[AR]  R1
23-Oct-16
Arithmetic µops
 Basic arithmetic µops:
 Addition, subtraction, increment and shift
 Add:
 R3  R1 + R2
 => HW implementation requires 3 registers and
adder
 Subtract:
 R3  R1 + R2’ + 1
 other arithmetic µops:
 R2  R2’, R2  R2’+1
 R1  R1+ 1,
23-Oct-16 R1  R1 - 1
Hardware implementation
 E.g 1) adder subtractor:
B3 A3 B2 A2 B1 A1 B0 A0
FA C3 FA C2 FA C1 FA C0
C4 S3 S2 S1 S0
 M = 1 => MΘB = B’; C=1

=>twos comp subtract
 M = 0 => MΘB = B; C=0
23-Oct-16
=> add
 E.g. 2) Binary incrementer:

 By using counter
 By using half adders connected in cascade
A3 A2 A1 A0 1
x y x y x y x y
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
23-Oct-16
Logic µops
 Specify binary operations for strings of bits stored in
registers
 Consider each bit separately
 Examples:
 XOR: p: F  AΘB
 Clear: p: F  0
 AND: p: F  A Λ B
 Transfer: p: F  A
 OR: p: F  A V B
23-Oct-16
HW implementation
 Most computers use only AND, OR, XOR and
complement
0 Function table
Bi S1 S0 Output -operation
1 4X1 0 0 F=AB AND
F 0 1 F = AB OR
MUX i
2 1 0 F=AB XOR
1 1 F = A’ Complement
3 Select
S1
S0
23-Oct-16
Shift µops
 Used for serial transfer of data
 Logical shift transfers 0 through the serial I/P
 E.g. R  shl R Shift-left register R
R  shr R Shift-right register R
R  cil/cir R Circular shift register R
R  ashl/ashr R Arithmetic shift reg R
e.g. ashr implementation:
sign
bit
23-Oct-16
HW implementation: bidirectional shift reg with

llel load, or using mulgtiplexers (more efficient)
0 for shift right (down)
Serial Select
input (IR) 1 for shift left (up)
Function table
S
MUX H0
0 select Output
1
A0 S H0 H1 H2 H3
S
A1
MUX H1 0 IR A0 A1 A2
0
1
A2 1 A1 A2 A3 IL
A3
S
MUX H2
0
1
S
MUX H3
0
1
Serial
23-Oct-16
input (IL)
Arithmetic logic shift unit

 A no of storage registers connected to a common
operational unit – the ALU
S3
S2 C i
S1
S0
D i
Arithmetic
Circuit
Select
0 4x1 F
C i+1 i
1 MUX
2
3
E i
Logic
B i
Circuit
A
i
shr
A i-1
shl
A
23-Oct-16 i+1
Instruction Sets: characteristics and 42
Functions
Computer instruction: binary code that
specifies sequence of µops for the computer
Operation of the processor: determined by
instruction it executes
 Referred to as machine instructions
Instruction set: collection of different
instructions that the processor can execute
Every computer has its own instruction set
23-Oct-16
Machine Instruction Fields 43
Each instruction must contain the information required by
the CPU for execution
Machine language instructions usually are made up of
several fields.
The major two fields are:
- Opcode (Operation Code): specifies the particular operation
that is to be performed.
E.g. ADD, MOV, LOAD, etc…
- Operands: specifies where to get the source and destination
operands for the operation specified by the opcode.
- Instruction can normally have one or two operands (source
operand, destination operand) and there are some
instructions with no operand also.
23-Oct-16
Contd… 44
Examples of instruction set

- ADD - Add two numbers together.
- COMPARE - Compare numbers.
- IN - Input information from a device, e.g. keyboard.
- JUMP - Jump to designated RAM address.
- JUMP IF - Conditional statement that jumps to a
designated RAM address.
- LOAD - Load information from RAM to the CPU.
- OUT - Output information to device, e.g. monitor.
- STORE - Store information to RAM.
- …….
23-Oct-16
Machine Instruction Cha-cs 45
Elements of machine instruction:

 Each instruction must contain info required by
the processor (see instruction state diagram)
 Operation Code:
 Specifies operations to be performed
 E.g. ADD, I/O, …
 Operation specified by binary code
 Source Operand reference:
 Operands that are input for the operation
23-Oct-16
 Result Operand Reference:

 Result that may be produced by operation
 Next Instruction Reference:
 Tells the processor where to fetch next instruction
after current instruction is complete
Next instruction:
 Can be located in main M or secondary M (virtual M)
 In most cases, immediately follows current instruction
 No explicit ref to instruction
 When ref needed, main M or virtual M address
supplied
23-Oct-16
Source and result operands can be in one of three

areas:
 Main or virtual M: as with next instruction references
 Processor register:
 Processor contains one/more registers for
references
 One register – implicit reference
 More than one register – unique no is assigned,
instruction must contain this no
 I/O device: instruction must specify I/O module and
device for the operation
23-Oct-16
Instruction Representation:
 Each instruction is represented by sequence of
bits
 Instruction is divided into fields
 More than one format with most instruction sets
 E.g. simple instruction format (16-bit):
4 bits 6 bits 6 bits

Opcode Operand ref Operand ref
16 bits
23-Oct-16
E.g. IAS instruction format:

 Two forms each with 40 bits
0 1 39
a) Number word
0 8 20 28 39
opcode address opcode address

b) Instruction word
23-Oct-16
Instruction representation:
 Binary representation – difficult to deal with
 Common practice – to use symbolic representation.
i.e.:
 Opcodes – represented by abbreviations – mnemonics
that indicate operations
E.g. ADD – Add, SUB – Subtract,
DIV – Divide
 Operands – also represented symbolically
e.g. ADD R, Y
 Each symbolic opcode has a fixed binary representation
 Programmer specifies location of each symbolic
23-Oct-16 operand
Instruction Types:
 High-level language – expresses operations in concise
algebraic form using variables
 Machine language – in basic form, involving movement
of data to/from registers
 E.g: in C/C++, X = X + Y;
in machine, LOAD X, M[addr1]
ADD X, M[addr2]
STORE X, M[addr1]
23-Oct-16
A computer should have set of instructions

that allows user to formulate data processing
task
In other words, a high level language must be
translated into machine language to be
executed
 Sufficient set of machine instructions to
express any of high-level language
instructions
23-Oct-16
Instruction Types:
 data processing : arithmetic and logic
instructions
 data storage : memory instructions
 Data movement : I/O instructions
 Control : test and branch instructions
23-Oct-16
Types of Operands:
 Machine instructions operate on data
 Most important general categories of data are:
 Addresses : are a form of data
 Numbers :
 which all machine languages include
 3 types: integer, float, decimal
 Characters : represented by sequence of bits; no of codes
available, e.g. ASCII – 7/8 bit
 Logical data : n-bit unit of data considered as n 1-bit items of
data each having 0 or 1
 Type: determined by operation being performed
23-Oct-16
Types of Operands 55
Addresses:
 Are a form of data
 To determine address, calculation must be
made on operand reference
 In this context, addresses are considered to be
unsigned integers
23-Oct-16
Numbers:
 Included in all machine languages
 Numbers stored in a computer are limited:
 In magnitudes that can be represented
 In precision (floats)
 Thus programmer has to understand
consequences of rounding, overflow and
underflow
23-Oct-16
Three types of numerical data:

 Integer or fixed point
 Floating point
 Decimal
 Packed decimal:
 For applications with great deal of I/O and
little computations
 Each digit is represented by a 4-bit code
 E.g. 0 = 0000, 1 = 0001, 8 = 1000, …
 Not efficient; only 10 of the 16 possible
23-Oct-16
values used
 Packed decimal …
 To form the numbers, 4-bit codes are strung
together:
 E.g. 246 = 0000 0010 0100 0110
 Less compact but avoids conversion overhead
 -ve numbers: a 4-bit sign digit at either end of
the string
 Many machines provide arithmetic
instructions for performing operations
directly on packed decimal nos.
23-Oct-16
Characters:
 Common form of data
 Not easy to process/transfer
 Number of codes to represent characters by bits:
 E.g. Morse code (the earliest!)
 ASCII – each character represented by 7-bit
pattern; some of the patterns represent
control characters
 EBCDIC – an 8-bit code used in IBM
mainframes
23-Oct-16
Logical Data:
 Each addressable n-bit data viewed as n 1-bit
items, with values 0 or 1
 Advantages:
 To store array of data items with values only
0 or 1
 To manipulate bits of data item
Note: “type” of a unit of data is determined by the
operation being performed on it
23-Oct-16
Instruction Set Design:

 One of the most interesting and most analyzed
aspect of computer design
 Very complex, b/c affects so many aspects
 Fundamental design issues:
 Operation repertoire: how many and which
operations to provide, and how complex
operations should be
 Data types: various types of data upon which
operations are performed
23-Oct-16
 instruction format: instruction length (bits),

no of addresses, size of various fields, and so
on
 Registers: no of processor registers that can
be referenced by instructions, and size
 Addressing: the mode/modes by which
address of an operand is specified
 These issues are highly interrelated and must be
considered in designing an instruction set
23-Oct-16
Types of Operations 63
Number of opcodes varies widely from machine to

machine
However, general types of operations are found on all
machines
Categories:
 Data transfer
 Arithmetic
 Logical
 Conversion
 I/O
 System control
 Transfer of control
23-Oct-16
Data transfer:
 Most fundamental type of machine instruction
 It specifies:
 Location of source and destination operands,
e.g. M, R, top of stack
 Length of data to be transferred
 Mode of addressing for each operand
 E.g. MOVE, STORE, LOAD, EXCHANGE,
PUSH, POP,…
 The simplest type in terms of processor action
23-Oct-16
Arithmetic:
 Basic operations: ADD, SUBTRACT, MULT,
DIVIDE
 Provided in most machines (for fixed/floating
point)
 Other single operand instructions:
 ABSOLUTE, NEGATE, INCREMENT,
DECREMENT
 Execution may involve data transfer operations
23-Oct-16
Logical:
 Provided by most machines for manipulating
individual bits
 Based up on Boolean operations, NOT, AND,
OR, XOR, (most common)
 E.g. if [R1]=10100101, [R2]=00001111, then
 [R1]AND[R2] = 00000101 (masking)
 In addition, variety of shift and rotate
instructions:
 SHR, SHL, ASHR, ASHL, ROR, ROL
23-Oct-16
Conversion:
 Change/operate on format of data
 E.g. TRANSLATE, CONVERT
 Translation e.g. from EBCDIC to ASCII, binary
to BCD, …
I/O:
 Only a few are provided in many
implementations
 E.g. IN, OUT
23-Oct-16
System control:
 Those that can be executed only while processor
is in a certain privileged state
 Typically preserved for use of operating system
 E.g. instruction to alter a control register
Transfer of control:
 To change sequence of instruction execution
 E.g. JUMP, RET, EXEC, SKIP,HALT,
WAIT, NOP
23-Oct-16
Addressing Modes 69
Addressing modes are the different ways in which the CPU

generates the address of operands.
In other words, they provide access paths to memory locations
and CPU registers
Effective address: is the address (binary bit pattern) issued by
the CPU to the memory
Commonly used addressing modes are explained below:
 Immediate
 Direct
 Indirect
 Register
 Register Indirect
 Displacement (Indexed)
 Stack
23-Oct-16
Immediate Addressing 70
Operand is part of instruction

Operand = address field
E.g. ADD 5
- Add 5 to contents of accumulator
- 5 is operand
No memory reference to fetch data
Fast
Diagram:
Instruction
Opcode Operand
23-Oct-16
Direct Addressing 71
Address field contains address of operand

Effective address (EA) = address field (A)
E.g. ADD A
- Add contents of cell A to accumulator
- Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective address
Limited address space
23-Oct-16
Direct Addressing Diagram 72
Instruction
Opcode Address A
Memory
Operand
23-Oct-16
Indirect Addressing 73
Memory cell pointed to by address field contains the address

of (pointer to) the operand
EA = (A)
- Look in A, find address (A) and look there for operand
E.g. ADD (A)
- Add contents of cell pointed to by contents of A to accumulator
Large address space
2nd where n = word length
May be nested, multilevel, cascaded
- e.g. EA = (((A)))
- Draw the digram yourself
Multiple memory accesses to find operand
Hence
23-Oct-16
slower
Indirect Addressing Diagram 74
Instruction
Opcode Address A
Memory
Pointer to operand
Operand
23-Oct-16
Register Addressing 75
Operand is held in register named in address field

EA = R
Limited number of registers
Very small address field needed
- Shorter instructions
- Faster instruction fetch
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
- Requires good assembly programming or complier writing
- N.B. C programming
 register int a;
23-Oct-16
Register Addressing Diagram 76
Instruction
Opcode Register Address R
Registers
Operand
23-Oct-16
Register Indirect Addressing 77
c.f. indirect addressing

EA = (R)
Operand is in memory cell pointed to by contents of register
R
Large address space (2nd)
One fewer memory access than indirect addressing
23-Oct-16
Register Indirect Addressing Diagram 78
Instruction
Opcode Register Address R
Memory
Registers
Pointer to Operand Operand
23-Oct-16
Displacement Addressing 79
EA = A + (R)
Address field hold two values
- A = base value
- R = register that hold displacement
- or vice versa
23-Oct-16
Displacement Addressing Diagram 80
Instruction
Opcode Register R Address A
Memory
Registers
Pointer to Operand +
Operand
23-Oct-16
Assembly Language 81
A processor can understand and execute

machine instructions
Such instructions are simply binary numbers
So, to program in machine language, requires
to enter as binary data
Fixed binary patterns assigned for each
instruction
Program can be represented by sequencing
these binary numbers (machine language)
23-Oct-16
E.g consider the ff statement:

 Y = A + B; where A = 3, B = 4
 Let the program be stored in M, starting from
location 100
 Program instructions:
 Load contents of location 200 into Accumulator
(AC)
 Add contents of location201 into AC
 Store contents of AC into location 202
23-Oct-16
Binary program:
Address Contents
100 0000 0001
101 0000 0011
102 0000 0010
Data:
Address Contents
200 0000 0011
201 0000 0100
202 0000 0000
This
23-Oct-16
is clearly tedious and error-prone task!
A slight improvement:
 Write the program in hex – as a series of lines:
Address Contents
100 01
101 05
102 02
…
200 03
201 04
202 00
23-Oct-16
For more improvement, symbolic names –

mnemonics can be used for each instruction
LDA 200
ADD 201
STA 202
…
DAT 03
DAT 04
DAT 00
This is called assembly language program

23-Oct-16
Stacks
Instruction formats
23-Oct-16
Processor Structure and Function: 87
Processor Organization
CPU must:
 Fetch instructions
 Interpret instructions
 Fetch data
 Process data
 Write data
23-Oct-16
Processor Organization 88
To do these things, it needs small internal

memory - Registers
To perform computation – ALU
To control movement of data & operation of
ALU – Control Unit
For data transfer and control logic – Internal
Bus
23-Oct-16
The CPU with the system bus
23-Oct-16
Internal structure of the CPU
23-Oct-16
Register Organization 91
CPU must have some working space (temporary

storage) called registers
Number and function vary between processor designs
One of the major design decisions
Top level of memory hierarchy
CPU registers perform two roles:
 User visible registers: enable programmer to
minimize main memory references by optimizing
their uses
 Control and status registers: used by control unit to
control operation of the processor
23-Oct-16
User visible registers: may be referenced by

machine language
Categories:
 General purpose
 Data
 Address
 Condition codes
23-Oct-16
General purpose registers:

 Can be assigned to variety of functions by the
programmer
 May be true general purpose
 May be restricted
 May be used for data or addressing
 Data
 Accumulator
 Addressing
 Segment
23-Oct-16
Data registers:
 Used only to hold data
 Cannot be employed in calculation of operand
address
Address registers:
 Can be general purpose or devoted particular
addressing mode
 Examples:
 Segment registers – to hold base address of a
segment in segmented memory
 Index registers – for indexed addressing

23-Oct-16
Stack pointer – points to top of stack
Design issues:
 General purpose or specialized use:
 Make them general purpose
o Increase flexibility and programmer
options
o Increase instruction size & complexity
 Make them specialized
o Smaller (faster) instructions
o Less flexibility
23-Oct-16
 No. of registers:
 Between 8 – 32 is optimum
 Fewer = more memory references
 More does not reduce memory references
and takes up processor real estate
 Register length:
 Large enough to hold full address
 Large enough to hold full word
 Often possible to combine two data registers
23-Oct-16
Condition codes:
 Hold condition codes (also referred to as flags)
 Bits set by processor hardware as result of
operations
 E.g. result of last operation was zero
 Can be read (implicitly) by programs
 e.g. Jump if zero
 Can not (usually) be set by programs
23-Oct-16
Control and Status Registers:

 To control operation of the CPU
 Most are not visible to user
 4 registers essential to instruction execution:
 Program Counter (PC)
 Instruction Register (IR)
 Memory Address Register (MAR)
 Memory Buffer Register (MBR)
23-Oct-16
Program Status Word (PSW):

 Contains condition codes + other status
 Common fields or flags:
 Sign of last result
 Zero
 Carry
 Equal
 Overflow
 Interrupt enable/disable
 Supervisor
23-Oct-16
Example Microprocessor Register 10
0
Organization
Two 16-bit microprocessors
23-Oct-16
10
Instruction Pipelining 1
Organizational enhancement for improved

performance
Strategy:
 Fetch usually shorter than execution
 Prefetch more than one instruction?
 Any jump or branch means that prefetched
instructions are not the required instructions
 Add more stages to improve performance
23-Oct-16
10
Consider subdividing instruction processing

in two stages: fetch and execute
 When main memory not accessed, fetch next
instruction in parallel with execution of current
 While the second stage is executing, first stage
fetches and buffer next instruction
 This is called instruction prefetch or fetch
overlap
 This will speed up instruction execution
23-Oct-16
10
Two stage instruction pipeline
23-Oct-16
10
Factors that reduce effectiveness of two-stage

pipeline:
 Execution time longer than fetch time
 Conditional branch instructions
To gain further speedup, pipeline must have
more stages
23-Oct-16
10
Example: decomposition of instruction processing:

 Fetch instruction (FI)
 Decode instruction (DI)
 Calculate operands (i.e. EAs) (CO)
 Fetch operands (FO)
 Execute instructions (EI)
 Write result (WO)
Overlap these operations
23-Oct-16
10
Timing diagram for instruction pipeline operation
23-Oct-16
10
Several factors limit performance enhancement:

 Simultaneous memory access problem
 If the six stages are not of equal duration
 Conditional branch instruction – invalidates
several instruction fetches
 Interrupts
23-Oct-16
10
The effect of conditional branch
23-Oct-16
10
9
Logic to account
for branches and
interrupts:
23-Oct-16
11
Alternative Pipeline Depiction 0
23-Oct-16
11
Pipeline Performance 1
Measures of pipeline performance and relative

speedup
Cycle time τ of an instruction – time needed to
advance a set of instructions one stage thru the
pipeline (each column)
  max[ i ]  d   m  d 1 i  k
i
23-Oct-16
11
Where:
 τi = time delay of circuitry in the ith stage
 τm = maximum stage delay (delay thru stage
which experiences the largest delay)
 k = no of stages in the instruction pipeline
 d = time delay of latch
In general, time delay d is equivalent to a
clock pulse and τm >> d
23-Oct-16
11
Now, suppose n instructions are processed, with no

branches:
 Total time required for a pipeline with k stages:
Tk ,n  [k  (n 1)]
 First instruction – requires k cycles to complete
 Remaining (n – 1) instructions – require n – 1 cycles
 E.g. The ninth instruction completes at time
cycle 14:
14 = [6 + (9 – 1)]
23-Oct-16
11
Now, consider a processor with equivalent

functions but no pipeline:
 Assume the instruction cycle time is kτ
 For n instructions,
 cycle time with no pipeline = nkτ
 Speedup factor Sk:
 Ratio of cycle time with no pipeline, to cycle
time with pipeline; given as:
T1,n nk nk
Sk   
Tk ,n [k  (n  1)] k  (n  1)
23-Oct-16
11
Plot of Sk vs n 5
23-Oct-16
11
Plot of Sk vs k 6
23-Oct-16
11
Exercise: 7
Draw a space-time diagram for a five-stage

pipeline showing the time it takes to process
six tasks. Also determine the clock cycle with
which the last instruction completes.
For the above pipelined processor, determine
the speedup factor for 200 instructions.
23-Oct-16
11
Pipeline Hazards
RISC- Reduced Instruction Set Computer
CISC versus RISC Characteristics
23-Oct-16
11
The Control Unit 9
Issues control signals to:

 Cause data exchange with M and I/O modules
 Move data between registers
 Cause ALU to perform a specified function
 Regulate other internal operations
Execution of instructions is accomplished by effect
of control signals
 These emanate from CU to ALU, registers, and
system interconnection
23-Oct-16
12
The Control Unit 0
Operation of a computer in executing a program

consists of a sequence of instruction cycles
One machine instruction per cycle
E.g. basic cycles:
 Fetch cycle
 Occurs at beginning
 Indirect cycle – to fetch operands
 Interrupt cycle
 Execute cycle
23-Oct-16
12
The Control Unit 1
Microoperations:
 Each instruction is made up of a no of smaller
units (e.g. fetch, indirect, execute, interrupt)
 These again consist of series of steps - µops
 µops – Are atomic operations of processor
 E.g. fetch cycle:
t1: MAR  [PC]
t2: MBR  Memory
PC [PC] + I
t3: IR  [MBR]
23-Oct-16
12
The Control Unit 2
Several of µops can take place during one step

Movements should not interfere
Grouping of µops must follow two simple rules:
 Proper sequence of events must be followed
 Conflicts must be avoided
µops for other cycles: Reading Assignment!

23-Oct-16
12
The Control Unit 3
Functional requirements:
 Those functions that the control unit must
perform
 Defining these is basis for the design and
implementation of the control unit
 Three step process to characterize CU:
 Define basic elements of the processor
 Describe µops that the processor performs
 Determine function of CU to cause µops
23-Oct-16
performed
12
The Control Unit 4
Basic functional elements of processor:

 ALU
 Registers
 Internal data paths
 External data paths
 Control unit
Execution of a program consists of operations
involving these processor elements
23-Oct-16
12
The Control Unit 5
functional description of CU
Two tasks of CU:
 Sequencing: cause processor to step thru a
series of µops in proper sequence
 Execution: causing each µop to be
performed
It does these by use of control signals
 I/P &O/P control signals – external
specifications
23-Oct-16
12
The Control Unit 6
The inputs allow it to determine state of

system
Inputs to CU include:
 IR
 Flags
 Control signals from external sources
Outputs allow it to control behavior of system
Internally, it will have logic to perform
sequencing and execution
23-Oct-16
12
The Control Unit 7
General model of CU
23-Oct-16
12
The Control Unit 8
Inputs:
 Clock:
 for “keeping time”
 CU causes one µop to be performed for each clock
pulse
 Processor cycle time
 Instruction register:
 Opcode determines which µop to perform during
execute cycle
 Flags:
 To determine status of the processor and outcome
23-Oct-16
of previous operations (e.g. ISZ)
12
The Control Unit 9
Outputs:
 Control signals within the processor – two types:
 Those that cause data to be moved from one
register to another
 Those that activate specific ALU functions
 Control signals to control bus – also two types:
 Control signals to memory
 Control signals to I/O modules
All of these signals applied as binary inputs to
individual logic gates
23-Oct-16
13
The Control Unit 0
Control Unit Implementation

 Could be one of:
 Hardwired
 Microprogrammed
 Hardwired:
 CU is essentially a combinational circuit
 Inputs:
 Flags and control bus signals – directly used
 IR input – opcode used to issue d/f
combination of control signals for different
23-Oct-16
instructions
13
The Control Unit 1
Implementation …
 A unique logic i/p is produced for each opcode
by using decoder
 Clock – issues repetitive sequence of pulses –
for measuring duration of pulses
23-Oct-16
13
The Control Unit 2
Control unit with decoded inputs
23-Oct-16
13
The Control Unit 3
Control unit logic:

 Produces o/p signals (C0, C1, …) as a function of
i/p signal
 i.e. for each control signal, drive boolean
expression of that signal as a function of inputs:
 E.g.let C1 is a control signal that causes data
to be read from memory to MBR, which is a
µop of fetch cycle performed at clock T2
 Let P and Q define the different cycles: i.e.
PQ = 00 – fetch
23-Oct-16
13
The Control Unit 4
 PQ = 01 – execute, …
 Then the Boolean expression will be:
 C1 = P’Q’.T2
 So, for every memory read instruction, this same
process is repeated
23-Oct-16
13
The Control Unit 5
Microprogrammed control
 Hardwired :
 difficult to design
 Inflexible
 Alternative:
 Microprogrammed control implementation
 Control variables at any given time can be
represented by a string of 1’s and 0’s called
control word
 Control word can be programmed to perform
23-Oct-16 various and stored in memory
13
The Control Unit 6
A control unit whose binary control variables are

stored in memory is called microprogrammed
control unit
Each word in memory – microinstruction
 It specifies one/more microoperations
23-Oct-16
13
The Control Unit 7
Microprogram
 Program stored in memory that generates all the
control signals required to execute the instruction set
correctly
 Consists of microinstructions
Microinstruction
 Contains a control word and a sequencing word
Control Word - All the control information required
for one clock cycle
Sequencing Word - Information needed to decide
 the next microinstruction address
 Vocabulary to write a microprogram
23-Oct-16
13
8
THANK YOU!!!!
23-Oct-16

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Bahir Dar University

Faculty of Electrical and Computer

Computer Architecture and Organization

How the ALU is interconnected:

In binary number system, arbitrary numbers can be

In general, if n bit sequence of binary digits

Several alternatives to represent signed integers

Twos Complement Representation

Characteristics of twos complement representation

In general, for both +ve and –ve numbers,

The most –ve twos complement number that can

Converting b/n two different bit lengths

 For a bit pattern of 1 followed by n-1 zeros:

Addition proceeds as if the two nos were

If result is +ve, a +ve no in twos compl form is

(a) M = 2 = 0010 (b) M = 5 = 0101

(c) M = -5 = 1011 (d) M = 5 = 0101

(e) M = 7 = 0111 (a) M = -6 = 1010

Block diagram of Hardware for Addition and

Complex operation (both in HW and SW)

Partial products: when multiplier bit = 0,

A computer executes a program of instructions (or

The figure - depicts execution of a program which consists

Register transfer µops

Example: Implementation of controlled transfer

Block diagram Control P Load

Timing diagram t t+1

Bus and memory transfers

In general, a bus system will multiplex k registers of

 M = 1 => MΘB = B’; C=1

 E.g. 2) Binary incrementer:

HW implementation: bidirectional shift reg with

Arithmetic logic shift unit

Examples of instruction set

Elements of machine instruction:

 Result Operand Reference:

Source and result operands can be in one of three

4 bits 6 bits 6 bits

E.g. IAS instruction format:

opcode address opcode address

A computer should have set of instructions

Three types of numerical data:

Instruction Set Design:

 instruction format: instruction length (bits),

Number of opcodes varies widely from machine to

Addressing modes are the different ways in which the CPU

Operand is part of instruction

Address field contains address of operand

Memory cell pointed to by address field contains the address

Operand is held in register named in address field

c.f. indirect addressing

Pointer to Operand Operand

A processor can understand and execute

E.g consider the ff statement:

For more improvement, symbolic names –

This is called assembly language program

To do these things, it needs small internal

The CPU with the system bus

Internal structure of the CPU

CPU must have some working space (temporary

User visible registers: may be referenced by

General purpose registers:

Control and Status Registers: