 Subtraction with Complements

 Convenient to implemented with digital hardware

 The subtraction of two n‐digit unsigned numbers M - N in base r can be
done as follows:

1. Add the minuend M to the r’s complement of the subtrahend N. Mathematically,

M + (r n - N) = M - N + r n.
2. If M ≥ N, the sum will produce an end carry r n, which is to be discarded; what is
left is the result M - N.
3. If M < N, the sum does not produce an end carry and is equal to r n - (N - M),
which is the r’s complement of (N - M). To obtain the answer in a familiar form,
take the r’s complement of the sum and place a negative sign in front.

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 Example:
1) Using 10’s complement, subtract 64572 - 3250.
M = 64572
10’s complement of N = + 96750
Sum = 161322
Discard end carry 105 = -100000
Answer = 61322

2) Given the two binary numbers X = 1000101 and Y = 0100011, perform the
subtraction (a) X - Y and (b) Y – X by using 2’s complements.
(a) X= 1000101
2’s complement of Y = + 1011101
Sum = 10100010
Discard end carry 27 = -10000000
Answer: X - Y = 0100010
(b) Y= 0100011
2’s complement of X = + 0111011
Sum= 1011110
There is no end carry. Therefore, the answer is
2 Y - X = -(2’s complement of 1011110) =-0100010.
  Subtraction of unsigned numbers can also be done by means of the (r - 1)’s complement

Repeat Example 2 (the previous), but this time using 1’s complement.
(a) X= 1000101 Y = 0100011
1’s complement of Y = + 1011100
Sum = 10100001
End-around carry = + 1
Answer: X - Y = 0100010
(b) Y= 0100011
1’s complement of X = + 0111010
Sum= 1011101
There is no end carry. Therefore, the answer is
Y - X = -(1’s complement of 1011110) =-0100010.

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  Signed Binary Numbers
 In the binary system the sign of a number is denoted by the left-most bit.
o For a positive number the left-most bit is equal to 0.
o For a negative number the left-most bit is equal to 1.
• Therefore, in signed numbers the left-most bit represents the sign,
and the remaining n − 1 bits represent the magnitude.

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  Negative numbers can be represented in three different ways: signed-
magnitude, signed-1’s complement, and signed-2’s complement.
Signed-Magnitude Representation
 The sign bit is 0 or 1 for positive or negative numbers, respectively.
For example, if we use four-bit numbers, then +5 = 0101 and −5 = 1101
Signed-1’s Complement Representation
 In the 1’s complement scheme, an n-bit negative number, K, is obtained by finding the
1’s complement of its equivalent positive number, P.
For example, consider the number P=+5, represented in binary with eight bits.
P=00000101
If we convert +5 to a negative, we get −5 =K=11111010
Signed-2’s Complement Representation
 In the 2’s complement scheme, a negative number, K, is obtained by finding
the 2’s complement of its equivalent positive number, P.
 Using our eight-bit example, −5 =k= 11111011

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 The table below illustrates the interpretation of all 16 four-bit patterns in the
three signed number representations. Note that for both signed-magnitude
representation and for 1’s complement representation there are two patterns
that represent the value zero. For 2’s complement there is only one such
pattern. Also, observe that the range of numbers that can be represented with
four bits in 2’s complement form is −8 to +7, while in the other two
representations it is −7 to +7.

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 Arithmetic Addition
Addition can be performed in any of the three number representations.

2’s Complement Addition

o The addition of two signed binary numbers with negative numbers represented in signed ‐
2’s‐complement form is obtained from the addition of the two numbers, including their
sign bits. A carry out of the sign ‐bit position is discarded.

• Consider the combinations

The 2’s complement notation is highly suitable for the implementation of addition operations.
7 • Describe overflow.
  Arithmetic Subtraction
 Subtraction of two signed binary numbers when negative numbers are in 2’s‐
complement form is simple and can be stated as follows:
 Take the 2’s complement of the subtrahend (including the sign bit) and add it
to the minuend (including the sign bit). A carry out of the sign‐bit position is
discarded.
o In the subtraction M – N, M: minuend and N: subtrahend

 Subtraction operation can be

realized as the addition operation,
using a 2’s complement of the
subtrahend, regardless of the signs
of the two operands.

 Therefore, it should be possible to

use the same adder circuit to
perform both addition and
subtraction.

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  Binary Codes
 Any discrete element of information that is distinct among a group of quantities can be
represented with a binary code (i.e., a pattern of 0’s and 1’s).
 The minimum number of bits required to code 2n distinct quantities is n.
 Binary-Coded Decimal Code (BCD)

 In digital systems it is possible to represent decimal numbers simply by encoding each

digit in binary form. This is called the binary-coded-decimal (BCD) representation.
 10 digits to encode

necessary to use four bits per digit.

 Each digit is encoded by the binary pattern that represents its unsigned value.

 The binary combinations1010 through 1111 are not used and have no meaning in BCD.
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  A number with k decimal digits will require 4k bits in BCD.
 Example: Decimal 396 is represented in BCD as:
0011 1001 0110
each group of 4 bits representing one decimal digit.
 BCD Addition
• Example

• The addition of two n‐digit unsigned BCD numbers is carried out by adding
each digit in BCD and transferring the carry to the next higher significant
digit.

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  Gray Code
 Only one bit in the code group changes in going from one number to the
next.
 Used in applications which may produce an error or ambiguity during the
transition from one number to the next.

Reading:
 Conversion from binary to gray and vise versa
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 Application of gray code
  ASCII Character Code
 The standard binary code for the alphanumeric characters is the
American Standard Code for Information Interchange (ASCII),
which uses seven bits to code 128 characters.
 Error‐Detecting Code
 To detect errors in data communication and processing, an eighth bit
is sometimes added to the ASCII character to indicate its parity.
 A parity bit is an extra bit included with a message to make the total
number of 1’s either even or odd.
With even parity With odd parity
ASCII A = 1000001 01000001 11000001
ASCII T = 1010100 11010100 01010100
 In each case, we insert an extra bit in the leftmost position of the code
to produce an even number of 1’s in the character for even parity or an
odd number of 1’s in the character for odd parity.
 By checking the parity of each character, error can be detected.

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 Reference
Brown and Vranesic: Chapter 5
Thomas L. Floyd: Chapter 2

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