3.

Logic Gates and Logic Families

Discrete Realization of Logic Gates
 Transistor Switches
 MOSFET (metal oxide semiconductor field-effect transistor) is used
for implementing a simple switch.
• Two different types of MOSFETs
- NMOS: n-channel MOSFET
- PMOS: p-channel MOSFET

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 NMOS:
- Turned on when gate
terminal is High.
- The drain is
pulled down to
ground.

PMOS:
- Turned on when the
gate terminal is Low.
- The drain is
pulled up to VDD

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NMOS Logic Gates
 The earlier schemes for building logic gates with MOSFETs.

NOT gate

 When Vx = 0 V, the NMOS transistor is turned off.

No current flows through the resistor R, and Vf = 5 V.

 When Vx = 5 V, the transistor is turned on and pulls

Vf to a low voltage level.

Truth table:
x f
0 1
1 0

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 NAND gate

 If Vx1= Vx2= 5 V, both transistors will be on

and Vf will be close to 0 V.

 But if either Vx1 or Vx2 is 0, then no current
will flow through the series-connected
transistors and Vf will be pulled up to 5 V.

Truth table:
x1 x2 f
0 0 1
0 1 1
1 0 1
1 1 0

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 NOR gate

 If either Vx1= 5 V or Vx2= 5 V, then Vf will

be close to 0 V.
 Only if both Vx1 and Vx2 are 0 will Vf be
pulled up to 5 V.

Truth table:

x1 x2 f
0 0 1
0 1 0
1 0 0
1 1 0

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AND gate OR gate

Truth table:
x1 x2 f
0 0 0
0
Truth 1table:0
1 0 0 x1 x2 f
1 1 1 0 0 0
0 1 1
1 0 1
1 1 1
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CMOS Logic Gates
 CMOS: Complementary MOSFET.
- Combines NMOS and PMOS.
 pull-up network (PUN) is built
using PMOS transistors
 Pull-down network (PDN) is build
using NMOS.
 Either the PDN pulls Vf down to
Gnd or the PUN pulls Vf up to
VDD.

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 NOT gate

 When Vx = 0 V, transistor T2 is off and transistor T1 is

on. This makes Vf = 5 V, and since T2 is off, no current

flows through the transistors.
 When Vx = 5 V, T2 is on and T1 is off. Thus Vf = 0 V,

and no current flows because T1 is off.

Truth table:
x T1 T2 f
0 On Of 1
f
1 Of On 0
f

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 NAND gate

 Under static conditions no path exists for

current flow from VDD to Gnd.

Truth table and transistor states:

x1 x2 T1 T2 T3 T4 f
0 0 on on off off 1
0 1 on off off on 1
1 0 off on on off 1
1 1 off off on on 0

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 NOR gate

 The circuit for the NOR gate is derived from

the logic expression that defines the NOR
operation

Truth table and transistor state:

x1 x2 T1 T2 T3 T4 f
0 0 on on off off 1
0 1 on off off on 0
1 0 off on on off 0
1 1 off off on on 0

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 AND gate
- Built by connecting a NAND gate OR gate
to  Constructed with a NOR gate
an inverter. followed by a NOT gate.

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