IMU-2nd ME-UG11T3302 Analog Electronics and Communication

CMOS (complementary metal-oxide-semiconductor)

Common design metrics by which a logic design (digital) technology is evaluated include area (package
density), speed, power consumption, noise immunity, fan-in, fan-out etc. CMOS technology is used
predominantly to create digital circuitry. Primary advantages of CMOS technology are very low power
consumption, good noise immunity and good performance (speed).
The fundamental building blocks of CMOS circuits are P-type and N-type MOSFET transistors.
A P-type MOSFET can be modeled as a switch that is closed when the input voltage (VGS) is
low (0 V) and open when the input voltage is high (5 V).
A N-type MOSFET can be modeled as a switch that is closed when the input voltage (VGS)
is high (5 V) and open when the input voltage is low (0 V).
The basic idea for CMOS technology is to combine P-type and N-type MOSFETs such that there is
never a conducting path from the supply voltage (5 V) to ground. As a consequence, CMOS circuits
consume very little power.
The symbols for an nMOS transistor is shown in Figure below. In figures X represents digital input
voltage (VGS).

The symbols for a pMOS transistor is shown in Figure below.

The negation indicator or bubble appears as a part of the pMOS symbol. This is because, in contrast
to the behavior of an nMOS transistor, a path exists between S and D in the pMOS transistor for
input (VGS) equal to 0 (at value Low) and does not exist for input equal to 1 (at value H).

Page | 1
By: Dr. Dhiren P Dave
IMU-2nd ME-UG11T3302 Analog Electronics and Communication

CMOS Based logic implementation:

A static CMOS logic is a combination of two networks, called the pull-up network (PUN) and
the pull-down network (PDN) as shown in Figure below.

• The PUN and PDN networks are constructed in a mutually exclusive fashion such that one and only
one of the networks is conducting in steady state.
• The PDN is constructed using NMOS devices, while PMOS transistors are used in the PUN.
• NMOS devices connected in series corresponds to an AND function and NMOS transistors
connected in parallel represent an OR function.
• A series connection of PMOS conducts if both inputs are low, representing a NOR function A′.B′
= (A+B)′, while PMOS transistors in parallel implement a NAND (A′ +B′) = (A·B)′.
Transistor Switch Series Connected Parallel connected
Type↓ Type ↓ transistors Represent ↓ transistors represent ↓
NMOS NO AND logic OR logic
PMOS NC NOR logic NAND logic

• The complementary gate is naturally inverting, implementing only functions such as NAND, NOR,
and XNOR. The realization of a non-inverting Boolean function (such as AND, OR, or XOR) in
a single stage is not possible and requires the addition of an extra inverter stage.
• The number of transistors required to implement an N-input logic gate is 2N.

Page | 2
By: Dr. Dhiren P Dave
IMU-2nd ME-UG11T3302 Analog Electronics and Communication

Implementation of AND, OR and NOT gates using CMOS transistors:

NOT (Invertor): Y = A′

From the circuit, it can be seen that when A=0, the PMOS
transistor conducts and NMOS transistor acts as open switch.∴
Y=1 (VDD).

Similarly, when A=1, PMOS transistor acts as open switch and

NMOS transistor acts as closed switch. ∴ Y=0 (VSS)

AND: Y = AB

When A=B=1, NMOS transistors conduct (closed switch)

and hence Y = 1 (VDD).

When any or both of A or B equals 0, the corresponding

NMOS transistor act as open switch, while PMOS transistors
act as closed switch. Hence Y = 0 (VSS).

OR: Y=A+B

When any of A or B=1, NMOS transistors conduct

(closed switch) and PMOS transistors acts as open
switch. ∴ F=0. F is applied as input to invertor and
hence Y = 1 (VDD).

Similarly, when A=B=0, the corresponding NMOS

transistor act as open switch and PMOS transistors act
as closed switch. Hence F = 1 (VDD) and Y=0 (VSS).

Page | 3
By: Dr. Dhiren P Dave