Keep in Mind about MOS Device

NMOS device is ON when gate voltage applied Logic ‘1’ or Vdd

NMOS device is OFF when gate voltage applied Logic ‘0’ or Vss
PMOS device is ON when gate voltage applied Logic ‘0’ or Vss
PMOS device is OFF when gate voltage applied Logic ‘1’ or Vdd

1
Dr. Bellamkonda Saidulu, Assoc. Prof, Dept of EIE, CVRCE, HYD.
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 2
 CMOS LOGIC or COMBINATIONAL LOGIC
➢ The CMOS logic gates, also called static CMOS gates. Exp: inverter and NAND gates.
➢ A fully complementary CMOS gate has an nMOS pull-down network (PDN) to connect the
output to '0' (GND) and pMOS pull-up network (PUN) to connect the output to '1' (VDD).
➢ The pull-up and pull-down network in the inverter each consisted of a single transistor.
➢ The NAND gate used a series pull-down network and a parallel pull-up network.
➢ Two or more transistors in series are ON only if all of the series transistors are ON.
➢ Two or more transistors in parallel are ON if any of the parallel transistors are ON.

Fig.(b) Dept
Dr. Bellamkonda Saidulu, Assoc.Prof, CMOS LOGIC
of EIE, Output
CVRCE, HYD. 3
Fig.(a) CMOS LOGIC
 CMOS INVERTER
➢ Schematic diagram shows a CMOS inverter or NOT gate using one
nMOS transistor and one pMOS transistor.
➢
➢ The horizontal bar at the top indicates VDD and the triangle at the
bottom indicates GND.

➢ The input (A) is Logic '0,' nMOS is OFF, pMOS is ON,

➢ then output is pulled to VDD or Logic ‘1’. Schematic diagram Symbol

➢ when input (A) is Logic ‘1’ , nMOS is ON, pMOS is OFF,

then output node (Y) is pulled down to logic '0’.
= A¯

(c)Truth Table
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 4
(d)DC Characteristic Curve
 CMOS 2- NAND GATE
➢ Schematic shows a 2-input CMOS NAND gate.

➢ It consists of two series nMOS transistors between ‘Y’ and

GND and Two parallel pMOS transistors between ‘Y’ and
VDD.

➢ If either inputs A or B is '0,’ Schematic Symbol

➢ respective nMOS transistors will be OFF, breaking the path
from ‘Y’ to GND & respective pMOS transistor will be ON,
➢ which makes short path between VDD to Output node ’Y’
provides Logic ‘1’.

➢ If all inputs are Logic ‘1’,

➢ respective nMOS transistors will be ON, which makes short
path from Output node ’Y’ to GND provides Logic ‘0’.
➢ All pMOS are OFF which breaks the path VDD to Output
node ’Y’.

➢ X-input NAND gates are constructed using X-series nMOS (c)Truth Table
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 5
➢ transistors and X- parallel pMOS transistors. X- no.of
 CMOS 3- NAND GATE
➢ Schematic shows a 3-input CMOS NAND gate.
➢ It consists of 3 series nMOS transistors between ‘Y’ and GND
and 3 parallel pMOS transistors between ‘Y’ and VDD.

➢ If either inputs A or B is '0,’

➢ respective nMOS transistors will be OFF, breaking the path
from ‘Y’ to GND & respective pMOS transistor will be ON,
which provides Logic ‘1’.

➢ If all inputs are Logic ‘1’,

➢ respective nMOS transistors will be ON, which makes short (a) Schematic
path from Output node ’Y’ to GND provides Logic ‘0’.
➢ All pMOS are OFF which breaks the path VDD to Output
node ’Y’.
➢ 3-input NAND gates are constructed using 3-series nMOS
transistors and 3- parallel pMOS transistors. 3-no.of inputs.
A
B Y=(A.B.C)’
C
(b)
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. Truth Table 6
CMOS 2- NAND GATE CMOS 3- NAND GATE
Schematic diagram Schematic diagram

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 7

 COMPOUND GATE LOGIC
A compound gate is formed by using a combination of series and parallel switch
structures.
Ex: The function Y = ((A-B) + (C- D))’
This function is called AND-OR-INVERT-22, or (AOI) because it performs the NOR
of a pair of 2-input ANDs.
For the nMOS pull-down network(PDN), take the uninverted expression {{A •
B) + (C* D)) indicating when the output should be pulled to '0.’
'0.’
The AND expressions (A •B) and (C •D)may be implemented by series connections
of switches.
For the pMOS pull-up network(PUN), take the complementary connected switches.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 8

By DeMorgan's Law, this is equivalent to
interchanging AND and OR
operations.
Hence, transistors that appear in series in
the pull-down network must appear in
parallel in the pull-up network.
Transistors that appear in parallel in the
pull-down network must appear in series
in the pull-up network.
This principle is called conduction
Complements.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 9

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 10
 PASS TRANSISTOR
The strength of a signal is measured by how
closely it approximates an ideal voltage source.
the stronger a signal, the more current it can
source or sink.
The power supplies, or rails, ( VDD and GND)
are the source of the strongest ‘1’s and '0 s.

An nMOS transistor is an perfect switch when

passing a '0' and passes a strong '0.’
the nMOS transistor is imperfect at passing a
'1’, degraded or weak ‘1’.

A pMOS transistor has the opposite behavior,

passing strong ‘1’s but degraded '0’s.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 11

 When an nMOS or pMOS is used alone as an imperfect switch, we sometimes call a pass transistor.

Transmission gate

By combining an nMOS and a pMOS transistor in

parallel is termed as transmission gate or pass gate.

In a circuit where only a '0' or a '1' has to be passed,

the appropriate transistor (n or p) can be deleted,
reverting to a single nMOS or pMOS device.

Both the control input and its complement are

required by the transmission gate.
This is called double rail logic.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 12

 NMOS-PASS TRANSISTOR

nMOS transistors pass '0's well but ‘1’s poorly.

Figure. (a) shows an nMOS transistor with the gate and drain tied to VDD.
the source is initially at Vs = 0. Vgs > Vt„, so the transistor is ON and current
flows.

If the voltage on the source rises to Vs =VDD -Vtn, V falls to Vtn and the
transistor cuts itself OFF. Therefore, nMOS transistors attempting to pass a '1'
never pull the source above VDD - Vtn. This loss is called a threshold drop.

Figure. (b) Similarly, pMOS transistors pass ‘1’s well but ‘0's poorly.
If the pMOS source drops below |Vtp|, the transistor cuts off.
Hence, pMOS transistors only pull down to within a threshold above GND.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 13

 NMOS-PASS TRANSISTOR Continued………………

In Figure. c, As the source (S) can rise to within a threshold

voltage of the gate, the output of several transistors in series is no
more degraded than that of a single transistor.

In Figure. d, If a degraded output drives the gate of another

transistor, the second transistor can produce an even further
degraded output.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 14

 NMOS-INVERTER ANALYSIS

A basic requirement for producing a complete range of logic circuits is the

inverter.
This is needed for restoring logic levels, for Nand and Nor gates, and for
sequential and memory circuits of various forms .

The basic inverter circuit requires a input transistor source connected to

ground and a load resistor drain to the VDD·
The output is taken from the drain of input device and source of depletion
transistor.
Fig. NMOS INVETER with
Resistors are not conveniently produced on the silicon substrate; even modest
depletion as load
values occupy excessively large areas so that some other form of load
resistance is required.

A convenient way to solve this problem is to use a depletion mode transistor

as the load as shown in this Fig.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 15

 NMOS-INVERTER ANALYSIS Continued……
The currents Ids for both transistors must be equal.

• For the depletion mode transistor, the gate is connected to the source (Vgs = 0),
so it is always ON.

• In this configuration,
Pull up device is depletion mode transistor and
Pull down device is Enhancement mode transistor.

Fig. NMOS INVETER with

depletion as load

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 16

 NMOS-INVERTER ANALYSIS Continued……
• To obtain the inverter transfer characteristic,
• we superimpose the Vgs = 0 depletion mode characteristic curve on the family of curves for the
enhancement mode device.
• Noting that maximum voltage across the enhancement mode device corresponds to minimum voltage
across the depletion mode transistor.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 17

 NMOS-INVERTER ANALYSIS Continued……

• As Vin (Vgs) exceeds the Vtn then current begins to flow. The output voltage Vout thus decreases and the
subsequent increases in Vin will cause the p.d. transistor to come out of saturation and become resistive.
• The p.u. transistor is initially resistive as the p.d. turns ON.
• The point at which Vout = Vin, is denoted as Vinv.
• Vinv can be shifted by variation of the ratio of pull-up to pulldown resistances ( Zp.ulZp.d) where Z = L/W
ratio.

NMOS INVERTER transfer characteristics

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 18
 Other forms of PULL Ups as load for NMOS INVERTER

In NMOS inverter, load types or pull ups are four types. i.e.

1). Resistive load (RL) 2). Depletion mode 3). Enhancement mode 4). Complementary (PMOS)

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 19

Complementary (PMOS)

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 20

DETERMINATION OF PULL-UP TO PULL-DOWN RATIO (Zp.u/Zp.d) FOR AN nMOS INVERTER
DRIVEN BY ANOTHER nMOS INVERTER

Figure shows a inverter is driven from the output of another similar inverter.
Consider the depletion mode transistor for which Vgs = 0 under all conditions, and further assume that in
order to cascade inverters without degradation of levels we are aiming to meet the requirement.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 21

 Power Dissipation
• Static CMOS gates are very power-efficient because they dissipate nearly zero
power while idle.
• As transistor counts and clock frequencies have increased, power consumption
has skyrocketed and become primary design constraint.
• The instantaneous power P(t) drawn from the power supply is proportional to the
supply current i(t) and the supply voltage VDD.
• Power,
• The energy consumed over some time interval T is the integral of the
instantaneous power.
Energy,

• The average power over this interval is

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 22

 Power Dissipation Continued……
• Total Power dissipation in CMOS circuits are two types.
• Static power dissipation and Dynamic Power Consumption
• Static dissipation due to Pstatic= Istatic.VDD
✓ subthreshold conduction through OFF transistors
✓ tunneling current through gate oxide
✓ leakage through reverse-biased diodes
✓ contention current in ratioed circuits
Dynamic dissipation due to Pdynamic = α.Cload
Charging(0→1)
✓ Charging and discharging of load capacitances
✓ “Short-circuit" current while both pMOS and nMOS
Discharging(1-->0)
networks are partially ON.
Ptotal =Pstatic + Pdynamic
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 23
 Delay Estimation
• The 'wiring-up' of circuits "takes place through the various conductive layers which
are produced by the MOS processing steps.
• Therefore necessary to be aware of the resistive and capacitive characteristics of
each layer.
• Consider as sheet resistance Rs and a standard unit of capacitance Cg, help in
evaluating the effects of wiring and input and output capacitances.
• The delays associated with wiring, with inverters and with other circuitry may be
conveniently evaluated in terms of a delay unit ‘τ’.
Propagation delay: tpd = maximum time from the input crossing 50% to the output
crossing 50%
Contamination delay: tcd = minimum time from the input crossing 50% to the output
crossing 50%
Parasitic delay: The parasitic delay of a gate is the delay of the gate when it drives
zero load.
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 24
 Delay Estimation- RC Model
• The RC delay model treats transistors as switches in series with resistors.
• A unit nMOS transistor to have effective resistance R. An nMOS transistor of k
times unit width has resistance R/k.
• A unit pMOS transistor has greater resistance. i.e. 2R.
• R=L/W

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 25

 Logical effort (LE)
• Logical effort of a gate is defined as the ratio of the input capacitance of the gate to
the input capacitance of an inverter that can deliver the same output current.
• Logical effort indicates how much worse a gate is at producing output current as
compared to an inverter.
• Logical effort can be measured in simulation from delay vs. fanout plots.
• Inverter, NAND, and NOR gates with transistor widths chosen to achieve unit
resistance, assuming pMOS transistors have twice the resistance of nMOS
transistors .
• The inverter presents 3 units of input capacitance.
• The NAND presents 4 units of capacitance on each input, so the LE is 4/3.
• Similarly, the NOR presents 5 units of capacitance, so the LE is 5/3.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 26

 Logical effort (LE) Continued……..

NANDs are better than NORs because NORs

have slow pMOS transistors in series.
The effort tends to increase with the number of
inputs.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 27

 RATIOED LOGIC
• Ratioed logic is preferred to reduce the no. of transistors
required to implement a given logic function, at the cost of
reduced quality in function and extra power dissipation.
• The purpose of the PUN in CMOS logic is to provide a
conditional path between VDD and the output when the PDN
is turned off. Fig. (a) Generic CMOS Logic
• In ratioed logic, the entire PUN is replaced with a single
unconditional load device that pulls the output node to be
high(VDD).
• Any gate or logic with ratioed logic, which consists of an
NMOS pull-down network that realizes the logic function,
and a simple load device.

Ratio=Aspect ratio(W/L) of each device (PMOS, NMOS)

Fig. (b) Generic Ratioed Logic
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 28
 • Pseudo-NMOS logic requires N+1 no. of transistors. (2N for
Pseudo-nMOS CMOS logic).
logic • The sizing (W/L) of the load device relative to the pull-down
devices can be used to trade-off parameters such a noise
margin, propagation delay and power dissipation.
• The voltage swing on the output and the overall functionality
of the gate depends upon the ratio between the NMOS and
Wp/Lp PMOS sizes, So called ratioed.
• In order to make VOL as small as possible, the PMOS device
should be sized much smaller than the NMOS pull-down
devices. i.e. Wp/Lp < Wn/Ln (wider NMOS).
Wn/Ln • Unfortunately, this has a negative impact on the propagation
delay for charging up the output node since the current
provided by the PMOS device is limited.
• A major disadvantage of the pseudo-NMOS gate is the static
Example of RATIOED LOGIC power.
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 29
 Pseudo nMOS INVERTER-Analysis

(Wp/Lp)

The static power dissipation of pseudo-NMOS limits its use.

However, pseudo-NMOS still finds use in large fan-in circuits.
When area is most important, the reduced transistor count compared to complimentary
CMOS is quite attractive.
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 30
 Dynamic Logic Gate
• Pseudo NMOS requires N+1 transistors instead of 2N
in CMOS. But it has a drawback continuous static
power consumption.
• Dynamic logic gate is an alternate for Pseudo NMOS
to reduce the static power consumption.
• This logic requires an addition of a clock input(ø).
• This logic operates in 2 major phases: precharge and
evaluation, with the mode of operation determined
by the clock signal CLK (ø).

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 31

 Dynamic logic- Example
• Pre-charge Cycle(CLK=0): The output node Out is Pre-
charged to VDD by the PMOS transistor Mp.
• During CLK=0, the Evaluate NMOS transistor Me is off, so that
the pull-down path is disabled.
• Evaluation Cycle(CLK=1): The pre-charge transistor Mp is off,
and the Evaluation transistor Me is turned ON.
• The output is conditionally discharged based on the input
values and the pull-down topology.
• If the inputs are such that the PDN conducts, then a low
resistance path exists between Out and GND and the output is
discharged to GND.
• If the PDN is turned off, the pre-charged value remains stored
on the output capacitance CL.

Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 32

 • The logic function is implemented by the
NMOS pull-down network(PDN).
• The number of transistors is lower than in
the static CMOS: N + 2 versus 2N.
• It is non-ratioed. The size of the pre-charge
Important properties: device can be made large to improve the low-
Dynamic logic to-high transition time.
• It only consumes dynamic power. Ideally, no
static current path ever exists between VDD
and GND.
• The logic gates have faster switching speeds.
• Advantages: Increased speed and reduced
area.
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 33
 Domino Logic

• A Domino logic module consists of an n-type

dynamic logic block followed by a static inverter.
• During pre-charge, the output of the n-type dynamic
gate is charged up to VDD, and the output of the
inverter is set to 0.
• During evaluation, the dynamic gate conditionally
discharges, and the output of the inverter makes a
conditional transition from 0 →1.
• The static inverter has the additional advantage that
the fan-out of the gate is driven by a static inverter
with a low impedance, output, which increases noise
immunity.
Dr. Bellamkonda Saidulu, Assoc.Prof, Dept of EIE, CVRCE, HYD. 34