Lab 2 Logic Gates

Objectives
The following are objectives of this lab:

1. Find experimentally the values of the NAND, NOR and inverter gates for all states and
build accompanying truth tables.
2. Discover how NAND and NOR gates can be configured to build all other logic gates.

Materials Needed
1. 7400 quad 2-input NAND gate
2. 7402 quad 2-input NOR gate
3. 1.0 kΩ resistor
4. 7486 quad XOR gate

Project Statement
This lab involves a number of different configurations of NAND and NOR gates as well as the
XOR gate to prove the states of the various gates as we record the states in truth tables. A
typical truth table is the following table. It represents an AND table. Inputs and outputs are
represented as LOW or HIGH. The representation could as easily been L - H or 0 - 1. The
following truth table shows the truth table for an AND gate.

Inputs Output
A B X
LOW LOW LOW
LOW HIGH LOW
HIGH LOW LOW
HIGH HIGH HIGH

Measurement of the various gates for entry in a truth table is done by using a jumper including
a 1KΩ resistor for a 1 or by using a jumper directly to 0 V for a 0. The output state is measured
with a voltmeter. Remember the chart from Lab 1. A voltage of 2.0 to 5.0 registers a high
although most readings will be about 4.4 for a high and a voltage of 0.0 to 0.8 registers a low
for a chip. Most low readings will be about .15 V or in that range. Fig. 2-1 shows the voltage
levels of the TTL gate from Lab 1 while Fig. 2-2 shows the layout of a typical chip and the
measurement technique used to enter values in the truth table that follows:

Lab 2 Logic Gates 1

 Illegal logic levels
5 Max legal logic level
Fig. 2-1 TTL Voltage Levels
4
Volts Logic HIGH
3

2 Min valid input. HIGH = VIH = 2.0 V

Invalid range
1 Max valid input. LOW = VIL = 0.8 V
Logic LOW

0V 5V
-+ -+ 5V Fig. 2-2 Basic Layout to Test for
States of Truth Table
=1 1KΩ

=1 1KΩ
Vcc
0V
the
chip

=0
=0

DMM

(set to Volt)

Inputs Output Truth Table Measurement

A B X Techniques

DMM

0V =0
0V =0
.15V

5V DMM

0V =0
.15V

=1 1KΩ

5V DMM

0V =0
.15V

=1 1KΩ

5V 5V DMM

4.39V

=1 1KΩ =1 1KΩ

Lab 2 Logic Gates 2

The following represent diagrams of all standard digital gates both from the normal and the
ANSI/IEEE specifications.

ANSI/
Normal
IEEE Basic logic gates.

1
Inverter

1
Inverter

AND &

>=1
OR

&
NAND

>=1
NOR

=1
XOR

=1
XNOR

Most of these gates are shown with two inputs. Some gates may have more than two inputs
while some may only have one or two inputs. In the experiment to follow, we test the truth
tables for two gates: NAND and NOR. These two gates are the universal gates that can be used
to build any other gate from the list above. To determine if two logic circuits are equivalent,
the truth tables for the two must be identical for all conditions. If they are equal, the circuits
are functionally equivalent.

Pre-lab Question

1. Why is a gate considered a “universal gate”? What gates are considered universal
gates?

Lab 2 Logic Gates 3

Procedure

Logic Functions

1. Fill in all blanks for the 7400 quad 2-input NAND chip below. Do not forget to apply Vcc and
0 volts to pins 14 and 7 respectively. Test one of the NAND gates for all combinations of
input state. Use the technique listed above in Fig. 2-1 and 2-2.

NAND

Inputs Measured
Output
A B Output
Voltage
0 0

0 1

1 0

1 1

2. Repeat the above step for the 7402 NOR gate. Note that the inputs are no longer on pin 1
as in the 7400 above. Refer to the attached schematic for each gate not assuming the same
pin configuration for different gates. Notice that more than one gate is present and you are
able to use any of the four gates to fill in values for the table below:

NOR

Inputs Measured
Output
A B Output
Voltage
0 0

0 1

1 0

1 1

Lab 2 Logic Gates 4

3. For the circuits below, notice that the inputs are jumpered together. Wire the circuit and
complete the truth table:

NAND NOR

Measured Measured
Output Output
Input Output Input Output
Voltage Voltage
0 0

1 1

4. Complete the circuit below and then fill in the truth table. Notice that multiple gates can be
used from a single chip (one chip may be used to wire the two gates below).

Measured
Output
Input Output
Voltage
0

5. Complete the circuit below and then fill in the truth table. Again, notice that multiple gates
can be used from a single chip (one chip may be used to wire the two gates below).

Inputs Measured
Output
A B Output
Voltage
0 0

0 1

1 0

1 1

Lab 2 Logic Gates 5

6. Complete the circuits below and then fill in both truth tables.

&
A
&
A >=1 >=1
& B
B

Inputs Measured Inputs Measured

Output Output
A B Output A B Output
Voltage Voltage
0 0 0 0

0 1 0 1

1 0 1 0

1 1 1 1

7. The circuit below is to be wired as shown and the truth table filled in. Notice if the switch is
closed, the input is 0. If the switch is open, the input is 1. What is the equivalent gate for
this circuit?

5V

1KΩ 1KΩ

B
Output (x)

Inputs Measured
Output
A B Output
Voltage
0 0

0 1

1 0

1 1

Lab 2 Logic Gates 6

Review Questions
1. List the circuit above equivalent to an AND gate:

2. List the circuit above equivalent to an OR gate:

Conclusion:

Lab 2 Logic Gates 7

Use the following diagrams to wire your circuits:

Lab 2 Logic Gates 8