REVIEW FOR ARITHMETIC OPERATIONS

AND CHAPTER 3
Lecture (Class A): Tue(1A-2A), Wed(7A-8A)
Lecture (Class B): Tue(2B-3B), Wed(5B-6B)
Office Hours: Tue(4A-4B), Wed(8B-9A)

This material is for educational uses only. Some contents are based on the material provided by other paper/book authors and may be copyrighted by them.
 Negative Numbers
Binary Numbers

ɵ Three approaches
– Signed magnitude
– Signed-1’s complement
– Signed-2’s complement
ɵ All three approaches represent positive numbers in the same way
– Conversion of 4-digit binary code from/to decimal number
ɵ (1101)ଶ = 1 × 2ଷ + 1 × 2ଶ + 0 × 2ଵ + 1 × 2଴ = (13)ଵ଴
Divisor Dividend/Quotient Remainder
2 (13)ଵ଴
2 6 1
2 3 0
2 1 1
0 1
1
Signed Magnitude
ɵ Most significant bit (MSB) is the sign bit
– ɀSRVLWLYH –7 +0
– ɀQHJDWLYH –6 1111 0000 +1

–5 1110 0001 +2
ɵ Remaining bits are the number's magnitude
1101 0010
–4 +3
ɵ Arithmetic is cumbersome 1100 0011

ɵ Two representations for zero – 3 1011 0100 + 4

1010 0101
– +0 = 0000 –2 +5
1001 0110
– –0 = 1000 1000 0111
–1 +6
ɵ Ex. Four-bit number can represent 16 –0 +7
numbers, but through singed magnitude
representation only 15 numbers from -7 to 7

2
Complements
ɵ Diminished radix complement of N (n-digits code)
– (r-1)’s complement for radix r defined as (rn-1) - N
– 1’s complement for binary system (radix 2)
ɵ Radix complement
– r’s complement for radix r defined as rn-N
– 2’s complement in binary system (radix 2)
ɵ Subtraction is done by adding the complement of the subtrahend
ɵ If the result is negative, takes its 2’s complement

Radix (base) is the number of unique digits including the digit zero
• Decimal system: ‫ = ݎ‬10 including 0,1, … , 9
• Binary system: ‫ = ݎ‬2 including 0,1
3
Binary 1’s Complement
ɵ For r = 2, N = (01110011)2, n = 8 (8 digits)
– (rn-1) = 256 – 1 = (255)10 or (11111111)2
– The 1’s complement of N is given by (2n - 1 - N)
11111111 (rn-1)
– 01110011 N
10001100
ɵ The 1's complement is obtained by complementing each individual bit
(bitwise NOT) because
– 2n – 1 factor consists of all 1's
– 1 – 0 = 1 and 1 – 1 = 0

4
Signed-1’s Complement
ɵ Negative number: Bitwise complement of
positive number
– ɀ10 –0 +0
– ɀ–10 –1 1111 0000 +1
ɵ Arithmetic works –2 1110 0001 +2
– Ex. 6 - 1 = 0110 + 1110 = (1)0100 + “1” 1101 0010
–3 +3
= 0101 (5) 1100 0011
– When there is end carry, add “1” to the
one’s complement result to have the real – 4 1011 0100 + 4

answer 1010 0101

–5 1001 0110 +5
– The added ”1” is referred to as end-
around carry –6 1000 0111 +6
ɵ Still have two representations for zero –7 +7

ɵ Ex. Four-bit number in singed-1’s complement

system counts only 15 numbers from -7 to 7

5
Subtraction with 1’s Complement
ɵ For n-digit unsigned numbers M and N, find M - N in minuend (M)
base 2 - subtrahend (N)
– Add the 1's complement of the subtrahend N to difference
the minuend M
ɵ M + (2n - 1 - N) = M - N + 2n - 1
– Case 1: If M ൒ N 1011 (M=(11)10)
+ 1001 (1’s comp of N=(6)10)
ɵ The sum produces an end carry rn which is
10100 (Discard end carry 24)
GLVFDUGHGIURPDERYH0î1UHPDLQV
+ 1 (Add end-around carry)
– Case 2: If M < N Answer: 0101 (=(5)10)
ɵ The sum does not produce an end carry and, 1011 (M=(11)10)
from above, is equal to 2n - 1 - (N - M), the 1's +0011 (1’s comp of N=(12)10)
complement of (N - M)
1110 (No end carry)
ɵ To obtain the result - (N – M) , take the 1's Answer: െ 0001 (= െ(1)10)
complement of the sum and place a negative
sign to its left 1’s comp.

6
Binary 2’s Complement
ɵ For ‫ = ݎ‬2, ܰ = (01110011)2, n = 8 (8 digit), we have
– (‫ ݎ‬௡ ) = (256)10 or (100000000)2
ɵ The 2's complement of ܰ given by (2௡ െ ܰ)
100000000 (‫ ݎ‬௡ )
– 01110011 ܰ
10001101
ɵ The 2’s complement (‫ ݎ‬௡ െ ܰ) is equivalent to the 1's complement
plus 1, i.e., ‫ ݎ‬௡ െ 1 െ ܰ + 1 = ‫ ݎ‬௡ െ ܰ
– This relation can be used in designing hardware

7
Signed-2’s Complement
ɵ Negative number: Bitwise complement plus
one
–1 0
– ɀ10 –2 1111 0000 +1
– ɀ–10 –3 1110 0001 +2
1101 0010
ɵ Arithmetic works –4 +3
1100 0011
ɵ Only one zero!
– 5 1011 0100 + 4
ɵ Ex. Four-bit number in singed-2’s 1010 0101
complement system counts 16 numbers –6 1001 0110 +5

from -8 to 7 –7 1000 0111 +6

–8 +7

8
Subtraction with 2’s Complement
ɵ For n-digit unsigned numbers M and N, find M - N in minuend (M)
base 2 - subtrahend (N)
– Add the 2's complement of the subtrahend N to difference
the minuend M
ɵ M + (2n-N) = M - N + 2n
– Case 1: If M ൒ N 1011 (M=(11)10)
+ 1010 (2’s comp of N=(6)10)
ɵ The sum produces an end carry rn which is
10101 (Discard end carry 24)
GLVFDUGHGIURPDERYH0î1UHPDLQV
Answer: 0101 (=(5)10)
– Case 2: If M < N
ɵ The sum does not produce an end carry and, 1011 (M=(11)10)
from above, is equal to 2n - (N - M), the 2's +0100 (2’s comp of N=(12)10)
complement of (N - M)
1111 (No end carry)
ɵ To obtain the result - (N – M) , take the 2's Answer: െ 0001 (= െ(1)10)
complement of the sum and place a negative
sign to its left 2’s comp.

9
Exercise 1.
ɵ Write +6 and –6 as signed-2’s complement number
?
– +6 = 0110
– - 6 = 1010
?

ɵ Infer 4-bit number ‘1001’ which is assumed to be represented in the

following systems
– As unsigned number: 9 ?
– As signed magnitude system: -1?
– As signed-1’s complement system: -6?
– As signed-2’s complement system: - ?

10
Exercise 2.
ɵ Represent a signed number of -14 using 6 bit in three different ways
– Signed & magnitude: 101110
?

– Signed-1’s complement: 110001

?

– Signed-2’s complement: 110010

?

ɵ Given the numbers of A, B, and C, convert them from three

representations to decimal number
Signed magnitude Signed-1’s complement Signed-2’s complement
֜ Decimal number ֜ Decimal number ֜ Decimal number
A = 0011 3 ? 3 ? 3 ?
B = 0111 7 ? 7 ? 7 ?
C = 1100 -4 ? -3 ? -4 ?
D = 1011 -3 ? -4 ? -5 ?

11
Exercise 3. Instruction Format of MIPS
ɵ Three instruction formats with the length of 32 bits
R type OP rs rt rd sa funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

ɵ MIPS fields
– Opcode (OP): basic operation of the instruction
– rs: the first register source operand
– rt: the second register source operand
– rd: the register destination operand getting the result of operation
– sa: shift amount
– funct: specific variant of the operation in Opcode

12
Exercise 3. Instruction Format of MIPS
ɵ MIPS instruction
– add $t0, $s1, $s2
– $s1 + $s2 ֜ $t0
R type OP rs rt rd sa funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
000000 10001 10010 01000 00000 100000
$s1 $s2 $t0
0? 17
? ?
18 8
? 0? ?
32

ɵ Suppose register $s1 has the binary number

1111 1111 1111 1111 1111 1111 1111 1111

– Represent the (signed integer) value in $s1 ֜ െ 1? ଵ଴

– Represent the (unsigned integer) value in $s1 ֜ 4,294,967,295
? ଵ଴

13
Representing Big (and Small) Numbers
(1/2)
ɵ Scientific notation
–  × 1010 × 109 (normalized)
– Impossible to encode the value above in a 32-bit integer
ɵ Floating point representation
– Sign: one bit
– Fraction: a binary fraction with a non-zero leading bit
– Exponent: binary integer

֜ െ1ୱ୧୥୬ × ‫ × ܨ‬2ா

ɵ Still have to fit everything in 32 bits (single precision)

– More bits in the fraction (F) or the exponent (E) is a trade-off between
precision(accuracy of the number) and range(size of the number)
14
Representing Big (and Small) Numbers
(2/2)

ɵ The exponent may be represented in sign magnitude form

– ELWLVXVHGIRUVLJQDQGELWVIRUWKHPDJQLWXGH
– The exponent will range from –WR
ɵ To avoid having two representations for “zero”, one may use an excess
representation or biased format to represent the exponent
– The exponent has no sign in this format
– The range 0 to 255 of an 8-bit number is divided into two parts “0
WRµDQG´WRµDVVKRZQEHORZ

The exponent will effectively range from –127 to +128

15
Example: Floating Point Number

ɵ Largest floating point number

– 0.1111 … 1111 × 2ଵଵଵଵଵଵଵଵ
՚ 8 bits ՜ = 1 െ 2 ିଶଷ
× 2ଶହହିଵଶ଻
ൎ 3.4 × 10ଷ଼
՚ 23 bits ՜
ɵ Smallest floating point number
– 0.1000 … 0000 × 2଴଴଴଴଴଴଴଴
՚ 8 bits ՜
= 0.1 × 2଴ିଵଶ଻
ൎ 0.293 × 10 ିଷ଼
՚ 23 bits ՜

ɵ Example: Represent 52.21875 in 32-bit binary floating point format

– Ans: The 32-bit string used to store 52.21875 in a computer will thus be
01000010111010000111000000000000

– ?
52.21875 = 110100.00111 = .11010000111 × 2଺
– Normalized 23 bit fraction: .11010000111000000000000
– Excess representation for exponent: 10000101 because 127 + 6 = 133

16
IEEE Floating Point Standard 754-1985
ɵ IEEE floating point representation for binary real numbers for a 32-bit

– Sign, for which 1 bit is allocated

– Fraction (called significand in the standard) is allocated 23 bits
– Exponent is allocated 8 bits
ɵ As both positive and negative numbers are required for the exponent, instead of using a separate
sign bit for the exponent, the standard uses a biased representation
ɵ The value of the bias is 127
– “An exponent 0” means that – -LVVWRUHGLQWKHH[SRQHQWILHOG
– “An exponent 198” means that  -LVVWRUHGLQWKHH[SRQHQWILHOG
ɵ The exponents –127 (all 0s) and + 128 (all 1s) are reserved for representing special numbers
ɵ To increase the precision of the significand, the IEEE 754 Standard uses a normalized significand
– This implies that its most significant bit is always 1
– In the IEEE Standard, the significand is 24 bits long
ɵ 23 bits of the significand which is stored in the memory and an implied 1 as the most significant
24th bit
– Thus a floating point number in the IEEE Standard is
െ1ୱ × (1. ‫ × )ܨ‬2ாିଵଶ଻
the implied 1 as the most significant bit of the significand is
explicitly shown for clarity 17
Example: IEEE 754 Representation of 32-bit
Floating Point Number

ɵ Example: Represent 52.21875 in IEEE-32-bit floating point format

– Ans: The bit representation in IEEE format is
01000010010100001110000000000000
՚ 8 bits ՜ ՚ 23 bits ՜

– 52.21875 = 110100.00111 = ? 1.11010000111 × 2ହ

omitted

– Normalized 23 bit fraction(significand):

.10100001110000000000000
– Exponent : 10000100 because ‫ = ܧ‬132 ‫ ܧ ׶‬െ 127 = 5

18
Example: IEEE 754 Representation of 32-bit
Floating Point Number

ɵ Largest positive number

– 1.1111 … 1111 × 2ଵଵଵଵଵଵଵ଴
՚8 bits՜ = 2 െ 2ିଶଷ × 2ଶହସିଵଶ଻ ൎ 3.403 × 10ଷ଼
՚ 23 bits ՜
– If the result of a computation exceeds the largest number that can be stored in the computer,
then it is called an overflow
ɵ Smallest positive number
– 0.0000 … 0000 × 2଴଴଴଴଴଴଴ଵ
՚8 bits՜ = 1.0 × 2
ଵିଵଶ଻ = 2ିଵଶ଺ ൎ 1.1755 × 10ିଷ଼
՚ 23 bits ՜
ɵ When all the exponent bits are 0 and the leading hidden bit of the siginificand is 0, then the
floating point number is called a subnormal number
– Thus, one logical representation of a subnormal number is
െ1ୱ × (0. ‫ × )ܨ‬2ିଵଶ଻ (all 0s for the exponent)
– F has at least one 1 (otherwise the number will be taken as 0)
ɵ Largest positive subnormal number: 0.999999988 × 2ିଵଶ଺ which is close to the smallest normalized
number 2ିଵଶ଺
ɵ Smallest positive subnormal number: 2ିଶଷ × 2ିଵଶ଺ = 2ିଵସଽ
ɵ A result that is smaller than the smallest number that can be stored in a computer is called an
underflow
19
Exception Events in Floating Point
ɵ Overflow(floating point) happens when a positive exponent becomes
too large to fit in the exponent field
ɵ Underflow(floating point) happens when a negative exponent
becomes too large to fit in the exponent field

ɵ One way to reduce the chance of underflow or overflow is to offer

another format that has a larger exponent field
– Double precision takes two MIPS words

20
Exercise 4. Floating Point Representation
ɵ Example
– (െ0.75)ଵ଴ = (െ0.11)ଶ = (െ1.1)ଶ × 2ିଵ
= (െ1)ଵ × 1 + .1000 0000 0000 0000 0000 000 × 2(ିଵାଵଶ଻)ିଵଶ଻

1 0111 1110
exponent fraction
1000 0000 0000 0000 0000 000
126 (8 ܾ݅‫)ݏݐ‬ (23 ܾ݅‫)ݏݐ‬

ɵ Specify a decimal number which is represented as follows

1 1000 0001 0100 0000 0000 0000 0000 000
129 (8 ܾ݅‫)ݏݐ‬ (23 ܾ݅‫)ݏݐ‬
(െ1)ଵ × 1 + .0100 0000 0000 0000 0000 000 × 2ଵଶଽିଵଶ଻
ଶ ?
= െ1 × 1.25 × 2 = െ5

21
Floating Point Addition
ɵ Addition (and subtraction)

– Step 0: Restore the hidden bit in F1 and in F2

– Step 1: Align fractions by right shifting F2 by E1 - E2 positions
(assuming E1 ൒ E2) keeping track of (three of) the bits shifted out
– Step 2: Add the resulting F2 to F1 to form F3
– Step 3: Normalize F3 (so it is in the form 1.XXXXX …)
– If F1 and F2 have the same sign
ɵ F3 1 bit right shift F3 and increment E3 (check for overflow)
– If F1 and F2 have different signs
ɵ F3 may require many left shifts each time decrementing E3 (check for underflow)
– Step 4: Round F3 and possibly normalize F3 again
– Step 5: Rehide the most significant bit of F3 before storing the result

22
Floating Point Addition
ɵ Add

– Step 0: Hidden bits restored in the representation above

– Step 1: Shift significand with the smaller exponent (1.1100) right until its
exponent matches the larger exponent (so once)
– Step 2: Add significands
ɵ 1.0000 + (-0.111) = 1.0000 – 0.111 = 0.001
– Step 3: Normalize the sum, checking for exponent over/underflow
ɵ 0.001 x 2-1 = 0.010 x 2-2 = ‫ = ڮ‬1.000 x 2-4
– Step 4: The sum is already rounded, so we’re done
– Step 5: Rehide the hidden bit before storing

25
Floating Point Hardware

26
REVIEW FOR COMBINATIONAL AND
SEQUENTIAL LOGIC CIRCUITS
Lecture (Class A): Tue(1A-2A), Wed(7A-8A)
Lecture (Class B): Tue(2B-3B), Wed(5B-6B)
Office Hours: Tue(4A-4B), Wed(8B-9A)
Big Picture: From Compiler to Silicon

28
Big Picture: From Compiler to Silicon

High level language

Instruction set
architecture (ISA)

29
Digital Logic Gates

30
Sequential vs. Combinational
ɵ Combinational systems are memoryless
– Outputs depend only on the present inputs

Input System Output

ɵ Sequential systems have memory

– Outputs depend on the present and the previous inputs

Input System Output

Feedback 31
 Functional Blocks: Addition
Combinational Logic

ɵ Binary addition used frequently

ɵ Addition development
– Half-Adder (HA): a 2-input bit-wise addition functional block
– Full-Adder (FA), a 3-input bit-wise addition functional block
– Ripple Carry Adder, an iterative array to perform binary addition
– Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve
performance

32
Functional Block: Binary Half-Adder
ɵ A 2-input, 1-bit width binary adder that performs the following
computations: x 0 0 1 1
+y +0 +1 +0 +1
‘cout’ ‘sum’ 00 01 01 10
ɵ A half adder adds two bits to produce a two-bit sum
ɵ The sum is expressed as a sum bit ‘sum’ and a carry bit ‘cout’
‫ݔ‬
‫ݕ‬
0 1 sum = ‫ ݔ‬ᇱ ‫ ݕ‬+ ‫ ݕ‬ᇱ ‫ݔ‬
݉଴ ݉ଵ
0 1
݉ଶ ݉ଷ
1 1

‫ݔ‬
‫ݕ‬
0 1 cout = ‫ݕݔ‬
݉଴ ݉ଵ
0
݉ଶ ݉ଷ
1 1
Truth table K-map Simplified expression 33
 Implementation: Binary Half-Adder
ɵ We can draw different implementations of a binary half-adder
depending on the availability of XOR and NAND gates

x’
y cout
x x
sum y sum
x
y’ sum
x y
y cout cout

• sum = ‫ ݔ‬ᇱ ‫ ݕ‬+ ‫ ݕ‬ᇱ ‫ݔ‬ • sum = ‫ݕ۩ݔ‬ • sum = (‫ ݔ‬+ ‫)ݕ‬coutԢ
• cout = ‫ݕݔ‬ • cout = ‫ݕݔ‬ • cout = ((‫)ݕݔ‬Ԣ)Ԣ

34
Functional Block: Binary Full-Adder
ɵ A full adder is similar to a half adder, but includes a carry-in bit ‘z’
from lower stages
ɵ Like the half-adder, it computes a sum bit ‘sum’ and a carry bit ‘cout’
ɵ For a carry-in z = 0, it is the same ɵ For a carry-in z = 1
as the half-adder
z 0 0 0 0 z 1 1 1 1
x 0 0 1 1 x 0 0 1 1
+y +0 +1 +0 +1 +y +0 +1 +0 +1
cout sum 0 0 01 01 10 cout sum 0 1 10 10 11

35
Logic Optimization: Binary Full-Adder
z ‫ݔ‬
‫ݖݕ‬
00 01 11 10
0
݉଴ ݉ଵ
1
݉ଷ ݉ଶ
1
sum = ‫ ݔ‬ᇱ ‫ ݕ‬ᇱ ‫ ݖ‬+ ‫ ݔ‬ᇱ ‫ݖݕ‬Ԣ + ‫ ݕݔ‬ᇱ ‫ݖ‬Ԣ + ‫ݖݕݔ‬
݉ସ ݉ହ ݉଻ ݉଺
1 1 1

‫ݖݕ‬
‫ݔ‬ 00 01 11 10
0
݉଴ ݉ଵ ݉ଷ
1
݉ଶ
cout = ‫ ݕݔ‬+ ‫ ݖݔ‬+ ‫ݖݕ‬
݉ସ ݉ହ ݉଻ ݉଺
1 1 1 1

Truth table K-map Simplified expression

ɵ ‘cout’ is 1 if (i) x=y=1 or (ii) the sum of x+y (i.e., ‫ )ݕ۩ݔ‬is 1 and z=1
֜ cout = ‫ ݕݔ‬+ ‫ݖ ݕ۩ݔ‬
This term is carry propagate
This term is carry generate
36
Implementation: Binary Full-Adder
ɵ We can draw different implementations of binary full adders
sum = ‫ ݔ‬ᇱ ‫ ݕ‬ᇱ ‫ ݖ‬+ ‫ ݔ‬ᇱ ‫ݖݕ‬Ԣ + ‫ ݕݔ‬ᇱ ‫ݖ‬Ԣ + ‫ݖݕݔ‬ cout = ‫ ݕݔ‬+ ‫ ݖݔ‬+ ‫ݖݕ‬

37
Implementation: Binary Full-Adder
ɵ We can draw different implementations of binary full adders
sum = ‫ ݔ‬ᇱ ‫ ݕ‬ᇱ ‫ ݖ‬+ ‫ ݔ‬ᇱ ‫ݖݕ‬Ԣ + ‫ ݕݔ‬ᇱ ‫ݖ‬Ԣ + ‫ݖݕݔ‬ cout = ‫ ݕݔ‬+ ‫ ݖݔ‬+ ‫ݖݕ‬
= ‫ ݔ‬ᇱ ‫ ݕ‬ᇱ + ‫ ݖ ݕݔ‬+ ‫ ݕݔ‬ᇱ + ‫ ݔ‬ᇱ ‫ݖ ݕ‬Ԣ = ‫ ݕݔ‬+ (‫ݖ)ݕ۩ݔ‬
= ‫ ݕ۩ݔ‬Ԣ‫ ݖ‬+ ‫ݖ ݕ۩ݔ‬Ԣ
= ‫ݖ۩ ݕ۩ݔ‬
‫ݖݕ‬
Binary half-adder circuit ‫ݔ‬ 00
݉଴
01
݉ଵ
11
݉ଷ
10
݉ଶ
• sum = ‫ݕ۩ݔ‬ 0
݉ହ
1
݉଺
݉ସ ݉଻
• cout = ‫ݕݔ‬ 1 1 1 1

‫ݖݕ‬
‫ݔ‬ 00 01 11 10
݉଴ ݉ଵ ݉ଷ ݉ଶ
0 1
݉ସ ݉ହ ݉଻ ݉଺
1 1 1 1

38
Implementation: Binary Full-Adder
ɵ We can draw different implementations of binary full adders
sum = ‫ ݔ‬ᇱ ‫ ݕ‬ᇱ ‫ ݖ‬+ ‫ ݔ‬ᇱ ‫ݖݕ‬Ԣ + ‫ ݕݔ‬ᇱ ‫ݖ‬Ԣ + ‫ݖݕݔ‬ cout = ‫ ݕݔ‬+ ‫ ݖݔ‬+ ‫ݖݕ‬
= ‫ ݔ‬ᇱ ‫ ݕ‬ᇱ + ‫ ݖ ݕݔ‬+ ‫ ݕݔ‬ᇱ + ‫ ݔ‬ᇱ ‫ݖ ݕ‬Ԣ = ‫ ݕݔ‬+ (‫ݖ)ݕ۩ݔ‬
= ‫ ݕ۩ݔ‬Ԣ‫ ݖ‬+ ‫ݖ ݕ۩ݔ‬Ԣ
= ‫ݖ۩ ݕ۩ݔ‬

Half-adder Half-adder OR gate

x
y sum

cout
z
FA
Note that the 2nd implementation uses 2 half-adders and an OR
gate to implement the full-adder 39
 Functional Block: Binary Adder
ɵ Binary adder produces the arithmetic
sum of two n-bit binary numbers ‫݅ܣ‬ ܲ݅ ܲ݅۩‫݅ܥ‬
‫݅ܤ‬ ܵ݅
– Full adders connected in
cascade ‫݅ܩ‬ ‫ ݅ܩ‬+ ܲ௜ ‫ܥ‬௜
– The output carry from each full ‫ܥ‬௜ାଵ
adder connected to the input ‫݅ܥ‬
carry of the next full adder ith stage FA

• ܲ݅ = ‫ܣ‬௜ ۩‫( ݅ܤ‬carry propagate)

• ‫( ݅ܤ݅ܣ = ݅ܩ‬carry generate)
• ܵ݅ = ܲ݅۩‫݅ܥ‬
• ‫ܥ‬௜ାଵ = ‫ ݅ܩ‬+ ܲ݅‫݅ܥ‬

E.x.) Four-bit ripple-carry binary adder implemented from four 1-bit full adders 40
Example: 32-bit ALU
Critical path of n-bit ripple-carry adder
is n×CP (֜ carry lookahead adder)

41
 Functional Block: Binary Multiplier
Multiplication

ɵ Multiplication of binary numbers works exactly like

in decimal
‫ܤ‬1 ‫ܤ‬0 (multiplicand)

× ‫ܣ‬1 ‫ܣ‬0 (multiplier)

‫ܤ‬1‫ܣ‬0 ‫ܤ‬0‫ܣ‬0 (augend)

+ ‫ܤ‬1‫ܣ‬1 ‫ܤ‬0‫ܣ‬1 (addend)

‫ܥ‬3 ‫ܥ‬2 ‫ܥ‬1 ‫ܥ‬0

ɵ Since numbers are binary, the multiplication of ‫ܣ‬௜
(multiplier bit) with ‫ ݅ܤ‬can be done with AND
– When ‫ܣ‬௜ = 0, we add 0 to the partial product
– When ‫ܣ‬௜ = 1, we add the multiplicand to the
partial product

42
 Functional Block: Binary Multiplier
ɵ Multiplication of more binary bits
(multiplicand) ‫ܤ‬3 ‫ܤ‬2 ‫ܤ‬1 ‫ܤ‬0
(multiplier) × ‫ܣ‬2 ‫ܣ‬1 ‫ܣ‬0
(augend) 0 ‫ܤ‬3‫ܣ‬0 ‫ܤ‬2‫ܣ‬0 ‫ܤ‬1‫ܣ‬0 ‫ܤ‬0‫ܣ‬0
(addend) + ‫ܤ‬3‫ܣ‬1 ‫ܤ‬2‫ܣ‬1 ‫ܤ‬1‫ܣ‬1 ‫ܤ‬0‫ܣ‬1
‫ݔ‬4 ‫ݔ‬3 ‫ݔ‬2 ‫ݔ‬1 ‫ݔ‬0
+ ‫ܤ‬3‫ܣ‬2 ‫ܤ‬2‫ܣ‬2 ‫ܤ‬1‫ܣ‬2 ‫ܤ‬0‫ܣ‬2
‫ݕ‬4 ‫ݕ‬3 ‫ݕ‬2 ‫ݕ‬1 ‫ݕ‬0
‫ܥ‬6 ‫ܥ‬5 ‫ܥ‬4 ‫ܥ‬3 ‫ܥ‬2 ‫ܥ‬1 ‫ܥ‬0
‫ݔ‬4 ‫ݔ‬3 ‫ݔ‬2 ‫ݔ‬1 ‫ݔ‬0
ɵ For J multiplier bits and K multiplicand bits
– (JxK) AND gates and (J-1) K-bit adders to
produce (J+K) bits

43
Multiplication
ɵ Binary multiplication is just a bunch of shifts and adds

0 1 1 0 6 ଵ଴

0 1 0 1 5 ଵ଴

0 1 1 0
0 0 0 0
0 1 1 0
0 0 0 0
0 0 0 1 1 1 1 0 30 ଵ଴

44
 Long-multiplication Approach

6 ଵ଴ 0 1 1 0
5 ଵ଴ 0 1 0 1
0 1 1 0
0 0 0 0
0 1 1 0
0 0 0 0
0 0 0 1 1 1 1 0 30 ଵ଴

45
 Long-multiplication Approach

6 ଵ଴ 0 1 1 0
5 ଵ଴ 0 1 0 1
0 1 1 0
0 0 0 0 0 Prod=Prod+Mcand
0000+0110 ֜ Shift right Mult
0 1 1 0 1 0
0 0 0 0 1 1 0 Add in 32-bit ALU
0011+0000 ֜ Shift right
0 0 0 1 1 1 1 0 30 ଵ଴
Add in 32-bit ALU
0001+0110 ֜ Shift right

0011+0000 ֜ Add in 32-bit ALU

Shift right
Prod+Mcand ֜
46
Fast Multiplication Hardware

47
Multiplexing
ɵ Multiplexer is a digital building block for selecting from multiple inputs
and routing this input to the output, called as a data selector
– Data input: 2n lines
Control
– Control input: n-bit
S0 S1 Sn-1
– Output: 1-bit (a specific input)

‫ܫ‬଴
‫ܫ‬ଵ
Data 2n-to-1 MUX Output

‫ܫ‬ଶ೙ ିଵ

Example of block diagram of 2n-to-1 multiplexer

48
 Example: 2-to-1 Multiplexer
ɵ Illustration of 2-to-1 multiplexer

Output I0 0 S Y
Control I0
S Y Y 0 I0
1-to-2 decoder Data
I1 1 1 I1
I1
S
Logic diagram Block diagram Functional truth table

ɵ Easy to represent Y in SOP form

– Y = S’I0 + SI1
– The control signal(s) AND-ed with appropriate input

49
 Example: 4-to-1 Multiplexer
ɵ Illustration of 4-to-1 multiplexer

I0
S0
Control Data S1 S0 Y
S1 Output I0 00
I1 0 0 I0
I1 01
Y Y 0 1 I1
I2 10

I3 11 1 0 I2
I2
1 1 I3
2-to-4 decoder
S1S0
I3
Logic diagram Block diagram Functional truth table

ɵ The SOP for 4-to-1 multiplexer

– ܻ = ܵଵᇱ ܵ଴ᇱ ‫ܫ‬଴ + ܵଵᇱ ܵ଴ ‫ܫ‬ଵ + ܵଵ ܵ଴ᇱ ‫ܫ‬ଶ + ܵଵ ܵ଴ ‫ܫ‬ଷ
– The control signal(s) AND-ed with appropriate input
50
Arithmetic Logic Unit (ALU)
ɵ Functional description
– logical and function
– logical or function
– arithmetic add function
– arithmetic subtract function
– arithmetic slt (set-less-then) function
– logical nor function
– …
ɵ ALU control lines define a function to be performed on A and B

51
Functions of 32-bit ALU

ɵ Since this ALU operates on 32-bit operands, it is called 32-bit ALU

ɵ Result lines provide result of the chosen function applied to values of A and B
ɵ Zero output indicates if all Result lines have value 0
ɵ Overflow indicates integer overflow of add and subtract functions;
– for unsigned integers, this overflow indicator does not provide any useful
information
ɵ Carry out indicates carry out and unsigned integer overflow

52
Example: Design of 32-bit ALU (AND/OR)
ɵ A number of functions are Operation = ቊ
0, and
performed internally, but 1, or
only one result is chosen
for the output of ALU
ɵ 32-bit ALU is built out of 32
identical 1-bit ALU’s
– Adder, subtractor, etc

53
 Clock
Sequential Logic

ɵ Clocked sequential circuit

– Employs signals affecting the memory at only discrete instants of
time (i.e., clock or clk)
ɵ Clock signals are periodic signals used to control the behavior of a
circuit at discrete instances in time
ɵ Clock generator provides a periodic train of clock pulses
– Determine when computational activity occurs
– The 0 ՜ 1 transition is often called the rising edge of the clock
– The 1 ՜ 0 transition is often called the falling edge of the clock.
pulsewidth
1
clock
0
period
rising edge (0 ՜ 1 transition) falling edge (1 ՜ 0 transition) 54
Steady-State Abstraction
ɵ When the clock ticks, the output becomes available (Observe C)
ɵ Wait for another clock tick (Observe C again)
– Combinational circuit: C will stay the same
– Sequential circuit: C may be different

Output
A
Inputs System C
B
Settled value
Period
clock

ɵ The clock period must be long enough for all voltages to settle to a
steady state before the next state change
55
 Synchronous Clocked Sequential Circuit
ɵ Clocked sequential circuits are synchronous sequential circuits using
clock pulses to control storage elements
ɵ Flip-flops are the storage element (memory) in clocked sequential
circuits
– A flip-flop is a binary storage device capable of storing 1 bit

• Forming the next input to • Formed by the input to the

flip-flop before the circuit & the value stored in
occurrence of clock pulse flip-flop (FF)
• The speed at which • A change in state of FF is
combinational circuit initiated only by a clock pulse
operate is critical transition
• When a clock pulse is not
active, the feedback loop is
broken
56
How do we store information?
ɵ The key to build storage circuits is
feedback!
"stored bit"
ɵ Example: Two inverters can hold a bit
(as long as power is applied) t t+G t+2G
time
ɵ How do we change the stored bit?
– Store new information by
temporarily breaking the feedback
path
"remember"

"load"
"data" "stored bit"

57
Storage Elements
ɵ Most popular storage cells to build sequential circuits
– Latch: level sensitive storage element
– Flip-Flop: edge triggered storage element

ɵ Examples of latches
– SR latch, S’R’ latch, D latch (= gated D latch)

ɵ Examples of flip-flops (FFs)

– D-FF, D-FF with enable, Scan-FF, JK-FF, T-FF

58
Set-Reset (SR) Latch
ɵ Cross-coupled NOR gates (with active high inputs)
– Input: ‘S’ for set and ‘R’ for reset
ɵ Input (S=1, R=0) ֜ Output (Q=1, Q’=0) in the set state
ɵ Input (S=0, R=1) ֜ Output (Q=0, Q’=1) in the reset state

R Q Q
Reset R Q
Set S Q’
S Q'
Function table
S R Q
Logic diagram
Graphic symbol 0 0 hold
0 1 0 (reset)
1 0 1 (set)
1 1 forbidden (0) 59
 Behavior of SR Latch
1՜0 S R Q
0՜1՜0՜1
0 0 hold
0 1 0
1 0 1
0՜1՜0՜1 1 1 forbidden (0)
1՜0

Input (S,R) (0,1) (0,0) (1,0) (0,1) (1,0) (0,0)

Reset Hold Set Reset Set 100 Oscillate

R
S
Q
Q'

60
Glitch Sensitive SR Latch
ɵ Under normal conditions, both inputs of the latch remain at 0
ɵ Static 0 glitches can set/reset the latch
– Glitch on S input sets the latch
– Glitch on R input resets the latch

61
SR Latch with NAND Gates (S’R’ Latch)
ɵ Two cross-coupled NAND gates (with active low inputs)
– Input signals for S’R’ latch require the complement of those
values for SR latch
ɵ Input (S=0, R=1) ֜ Output (Q=1, Q’=0) in the set state
ɵ Input (S=1, R=0) ֜ Output (Q=0, Q’=1) in the reset state
ɵ Under normal conditions, both inputs of the latch remain at 1

Logic diagram Function table Graphic symbol

62
 Gated Latches
S’R’ latch
ɵ S’R’ latch with an additional control input (enable)
S
– Add extra NAND gates in front of S’R’ Latch. Q
ɵ When En=0, holds its current state En
– The inputs to the latch are both 1
Q'
– The S’R’ latch into its hold state R
ɵ When En=1, functions as the SR latch Logic diagram

– Inputs (S,R) reach the latch

– S=1 (and R=0) causes a set (Q=1)
– R=1 (and S=0) causes a reset (Q=0)
Function table of S R Q Function table of S R Q
SR latch 0 0 hold S’R’ latch 0 0 forbidden (1)
0 1 0 0 1 1
1 0 1 1 0 0 Function table of the gated latch
1 1 forbidden (0) 1 1 hold 63
 Data (D) Latch (Transparent Latch)
ɵ Aimed at eliminating the indeterminate state (both outputs are the same
value) in the SR latch by
– Ensuring that the inputs S and R are never equal to 1 at the same time
ɵ Construct a latch where S and R can never be the same value
– Still have the set and reset states
– Have a hold state by the control signal
– Avoid the undesirable cases (i.e., the outputs are the same and
breaking the complementation property)
S
D Q
Q
En

R Q'

Logic diagram Function table Graphic symbol

64
Potential Issues with Latches
ɵ Latches do not allow for precise control because of its level sensitivity
– Consider a D-latch with a clock signal connected to the control
input (enable)
– The output of the latch can change anytime while the clock is
high
ɵ This creates an interval in time over which the state or output of the
memory element can change rather that an instant in time at which
the state or output of the memory element can change
ɵ It would be better to only allow the output to change when the clock
edge makes a transition 0 ՜ 1 (rising edge triggering) or 1 ՜ 0 (falling
edge triggering)
֜ Enables more precise control!

65
Flip-Flops (FFs)
ɵ Recall that latches are level sensitive devices and do not give precise
control with respect to when their outputs change
ɵ Restrict changes only in the instance of time when some clock signal
makes a transition from either 0 ՜ 1 (rising edge triggering) or 1 ՜ 0
(falling edge triggering)
ɵ Flip-flops are storage elements that are edge-triggered

66
What does triggering mean?
ɵ Response to positive level (a latch) – a large window of time for output to
change

ɵ Positive edge triggering

– The input to the flip-flop just before the clock changes from 0 ՜ 1
causes the output to change just after the clock changes from 0 ՜ 1

ɵ Negative edge triggering

– The input to the flip-flop just before the clock changes from 1 ՜ 0
causes the output to change just after the clock changes from 1 ՜ 0

67
 Master-Slave DFF (Negative Edge-Triggered)
ɵ Consider a circuit constructed with two D latches (master and slave) and a inverter

Function table of D latch

ɵ The circuit samples the value of D just prior to the falling edge of the clock and
transfers it to the output Q just after the falling edge of the clock
ɵ While Clk=1 Function table of DFF
– Y will follow input D via the master latch, but Q will not follow Y (it is in hold with negative edge
state) and will hold its current value Clk Y Q
ɵ When Clk=0 (at the moment of change) 1 D hold
՝ hold D
– Y will be disconnected from D and will hold its current value
0 hold D
– Q will follow Y via the master latch ՛ D hold
ɵ A change in the output of the flip-flop can be triggered only at the transition 1 ՜ 0 68