AN 907: Enabling 5G Wireless

Acceleration in FlexRAN
for the Intel® FPGA Programmable Acceleration
Card N3000

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 Contents

Contents

1. About the 5G Wireless Acceleration Reference Design ................................................... 3

1.1. 5G User Image Features......................................................................................... 3
1.2. About the Intel PAC N3000..................................................................................... 4
1.2.1. Factory Image for 2x2x25 GbE.................................................................... 5
2. 5G User Image Description............................................................................................. 7
2.1. User Image Power Management.............................................................................. 7
2.2. 5G Channel Coder..................................................................................................8
2.2.1. 5G Channel Coder Throughput.....................................................................9
2.2.2. 5G LDPC-V Transmitter and Receiver Test Cases........................................... 11
2.2.3. 5G VRAN Universal Verification Methodology................................................12
2.3. Fronthaul IO....................................................................................................... 12
2.4. User Image Software............................................................................................13
3. Document Revision History for AN 907: Enabling 5G Wireless Acceleration in
FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000.................... 14

AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Send Feedback
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1. About the 5G Wireless Acceleration Reference Design

The 5G Wireless Acceleration reference design provides IP (Intel FPGA IP and software
drivers) to support fronthaul IO and 5G channel coding (forward error correction
(FEC)).

The Intel FPGA PAC N3000 provides an on-board PCIe switch that connects fronthaul
and 5G channel coding functions to a PCIe Gen3x16 edge connector. The Intel FPGA
PAC N3000 is a general-purpose acceleration card for networking.

Figure 1. Data flow for the user image, FEC, and Fronthaul IO

Intel Arria 10

FEC
LDPC LDPC MQ DMA PCIe Switch
Transmitter Receiver

2x25G (1 Active & 1 passive)

PCIE Connector
Intel
Intel
QSFP28 C827 2 x 25G Gearbox 2 x 40G
PHY+MAC MAC+PHY XL710
Timer

2x25G (1 Active & 1 passive)

Intel
QSFP28 2 x 25G 2 x 40G Intel
C827 Gearbox
PHY+MAC MAC+PHY XL710
Timer

1.1. 5G User Image Features

FEC features:
• Functionality independent of 25G I/O (look-aside model).
• Support for one physical function (PF) and 8 virtual functions (VFs) simultaneously
accessing acceleration.
• 64 queues supported equally split between uplink and downlink.
• Multiqueue high-performance DMA
• Hybrid automatic repeat request (HARQ) block
• LDPC transmitter with interleaving and rate matching.
• LDPC receiver with de-interleaving function and reverse rate matching.
• Load balancer distributes the pending requests to transmitter and receiver.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
 1. About the 5G Wireless Acceleration Reference Design
AN-907 | 2020.09.10

• Early termination CRC24B.

• Software enablement by baseband device (bbdev) API (targeted to upstream to
Data Plane Development Kit (DPDK).
• Function-level reset.

Fronthaul IO features:
• 25G MAC and 25G PHY IP connectivity to retimer and a quad small form factor
pluggable (QSFP28).
• 40G MAC and 40G PHY IP connectivity to Intel XL710 networking device.
• Gearbox to enable 25G connectivity to QSFP28.
• IEEE 1588 PTP support.
• Software enablement by Open Platform Acceleration Environment (OPAE), DPDK
and bbdev.

Related Information
• 5G LDPC-V Intel FPGA IP User Guide
• IEEE 1588 V2 Test: Intel FPGA Programmable Acceleration Card N3000

1.2. About the Intel PAC N3000

You enable the Intel PAC N3000 through six main firmware components. Intel also
provides a software package for the Intel PAC N3000. Intel creates and maintains five
of these firmware components, are not specific to the user image or application you
run on the N3000. These firmware components manage the board management
control and factory image and the interface configuration (PCIe and Ethernet).

The Intel PAC N3000 supports a user image. A remote system update (RSU) capable
page (page 1) in an on-board 1 Gb flash stores the user image. A non-RSU capable
page (page 0) of the same 1 Gb flash stores a fail over factory image..

AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Send Feedback
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1. About the 5G Wireless Acceleration Reference Design
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Intel develops and owns all of the following Intel PAC N3000 components (including all
updates) except the Intel® Arria® 10 flash page 1 user image:
• Intel MAX® 10 Nios flash.
— Fixed configuration.
— RSU capable.
— Intel loads the binary image.
• PCIe software.
— Intel flashes the binary images.
— Fixed configuration for PCIe configuration.
— Not RSU capable.
• Intel C827 retimer.
— Intel flashes the binary EEPROM.
— Power-up configuration initialization by Intel Arria 10 soft Nios processor
through Intel MAX 10.
— Fixed configuration for transceiver.
— Encrypted.
• Intel XL710.
— Intel flashes the binary images.
— Fixed configuration for transceiver configuration.
— RSU capable.
• Intel Arria 10 flash factory image page 0.
— Intel flashes the binary images.
— Not RSU capable.
• Intel Arria 10 flash page 1 user image.
— RSU capable.
— Intel provides the top-level reference design under a software license
agreement.
— Contains multiple encrypted IP blocks provided under a software license
agreement.
— You own the production image and design.

Related Information
• Intel® FPGA PAC N3000 AFU Developer Guide
• Intel® FPGA PAC N3000 Data Sheet
• Security User Guide: Intel FPGA Programmable Acceleration Card N3000
• Intel Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card
N3000

1.2.1. Factory Image for 2x2x25 GbE

Page 0 of the flash contains the factory image. This image tests and diagnoses the
Intel PAC N3000.

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The factory image:

• Tests the image that enables PCIe, Ethernet, and memory diagnostics:
— PCIe near-end loopback testing
— Memory testing using DMA reads and writes
— Ethernet loopback test
• Enables the RSU for the user image in flash

If the user image update fails, the Intel PAC N3000 restarts with the factory image,
you can then reload the user image.

Figure 2. Factory Image Block Diagram for 2x2x25 GbE

EEPROM EEPROM
Intel Arria 10 FPGA

Ethernet Wrapper Ethernet Wrapper

External 25G PHY 25G MAC 40G MAC 40G PHY XL710-BM2
QSFP Retimer
Loopback 25G PHY 25G MAC 40G MAC 40G PHY 2x40 PCIe
x8
Avalon-ST
External 25G PHY 25G MAC 40G MAC 40G PHY
QSFP Retimer XL710-BM2
Loopback 25G PHY 25G MAC 40G MAC 40G PHY
2x40 PCIe PCIe
CSR CSR CSR CSR x8 PCIe x16
Avalon-MM Avalon-MM Switch Edge
PCIe
Connector
x16
Ethernet Wrapper PCIe
Ethernet Wrapper PHY Group Gen3x8
PCIe Loopback (NLB) PHY Group
Memory Test (DMA) External Memory Status
Memory Test (DMA) NIOS PKVL CTRL PCIe
Memory Test (DMA) Intel MAX 10 SPI/OSPI Gen3x8
Memory Test (DMA) MAC ROM
NIOS AFU Features FME Features
PKVL

Host Software
SPI/QSPI DDR4 DDR4 DDR4 QDRIV 2xPCIe Test (OPAE fpgadiag / NLB)
Controller Controller Controller Controller Controller Memory Test (OPAE fpgabist)
MAC ROM Test
Ethernet Loopback Test
MDIO NIOS MAC DDR4 DDR4 DDR4 QDRIV Image Update
I2C Flash ROM Memory Memory Memory Memory BMC Test (via PCIe Connector SMBus)
Intel Software Packet Generator
SMBus Intel MAX 10 Mailbox (Temperature, Voltage)
IRQ MAX 10
Ethernet Wrapper Configuration and Status
A10 Image
Flash

AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Send Feedback
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2. 5G User Image Description

The user image performs fronthaul IO and 5G channel coding. Contact Intel for the
user image.

Figure 3. 5G User Image

EEPROM EEPROM Intel Arria 10 FPGA

Ethernet Wrapper Ethernet Wrapper

PCIe
External QSFP C827 25G PHY 25G MAC 40G MAC 40G PHY XL710 x8
Loopback

Decompression
Compression/
25G PHY 25G MAC Av ST 40G MAC 40G PHY 2 x 40

Mux
UPL
CSR PCIe
External C827 25G PHY 25G MAC 40G MA 40G PHY x8
QSFP XL710
Loopback 25G PHY 25G MAC 40G MAC 40G PHY PCIe
2 x 40
x16 PCIe
CSR CSR PCIe
Switch x16
Av MM Not Urgent Edge
Connector
AFU Private Features PCIe PCIe x8
UPL Gen3 x8
Av MM Ethernet Wrapper CCI-P MUX
Ethernet Wrapper PCIe PCIe x8
Gen3 x8
ETH Group
ETH Group SMBus
External Memory Status
NIOS C827.SPI CTRL
NIOS MAC ROM HARQ LDPC Encoder Decoder
C827 FME Private Features & Surrounding Blocks Host SW
BBDev
Memory Test (OP AE fpgabist)
SPI/QSPI I2C DDR4 DDR4 DDR4 QDRIV MAC ROM Test
CTRL Controller Controller Controller Controller Controller Eth lbk Test sw (sw set C827,

VC Diagnostic Tests
FPGA PHY and XL710 lbks)
MDIO A10 Image Update
Nios MAC DDR4 DDR4 DDR4 QDRIV
Flash ROM Memory Memory Memory Memory BMC Test (Via PCIe Connector SMBus)
I2C
Intel SW Packet Generator (e.g. TRex)
IRQ MAX 10 MAX10 Mailbox (Temp, Voltage, etc.)
A10 Image MAX10 Mailbox (Temp, Voltage, etc.)
Flash
Eth Wrapper Config / Stats

2.1. User Image Power Management

On-board power monitoring restricts the board temperature to 100°C. In the event of
reaching this limit, the board is automatically shut down. The user image power
consumption and thermal profile must fit within this envelope.

For different situations with different functions, the power consumptions are different.
As a reference point, the raw power consumption of the FPGA for the 5G user image is
about 60 W @ 100°C junction temperature. The Intel PAC N3000 card power
consumption is about 100 W.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
 2. 5G User Image Description
AN-907 | 2020.09.10

2.2. 5G Channel Coder

Send and receive code blocks for the encoder and decoder over PCIe to or from the
host using the descriptor format defined in the Data Plane Development Kit (DPDK)
and the baseband device. Contact Intel for the descriptor format.

The channel coders queue and process these blocks based on the load balancing
decisions.

Figure 4. 5G Channel Coder

PCIe SR-IOV (Gen3 x 8)

Avalon ST TLP Bus

TLP adapter
HARQ Debug Interface Write
DDR4 Code
Blocks
Bridge Commands
Code
32 Encoder & Blocks UL Code Avalon ST Avalon ST
Avalon ST Width Adapter & Demux

from HARQ UL FEC

Avalon ST Width Adapter & Mux

Decoder Queues Host Block Width Width
Adapter Combine Accelerator Adapter
FIFO

64-queue DMA Load

Balancer
Avalon ST DL FEC Accelerator Avalon ST
DL Code Width Width
Block Adapter & Adapter &
IP
FIFO Demux DL FEC Accelerator Mux
Encrypted IP

Reference Design

The downlink FEC accelerator consists of the 5G LDPC-V transmitter and the uplink
FEC accelerator consists of the 5G LDPC-V receiver. The input to the downlink FEC
accelerator is 32-bit data and the output data is 32-bit wide. For more information on
the 5G LDPC-V transmitter and receiver, refer to the 5G LDPC-V Intel FPGA IP User
Guide.

Figure 5. Transmitter Signals

This figure does not show the Avalon streaming interface signals
clk Top-level Design
rstn
i_Idpc_paras o_source_data
i_sink_data Code LDPC
Block CRC Encoder Rate matcher
32 32 384 32

AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Send Feedback
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Figure 6. Receiver Signals

This figure does not show the Avalon streaming interface signals

.
clk Top-level Design
rstn o_ldpc_metrics
i_Idpc_paras o_source_data
i_sink_data Derate HARQ LDPC Code Block
matcher (Cleartext) Decoder CRC
16x 32x 32x 32 32
LLR LLR LLR
_W _W _W

DDR
SDRAM Avalon Memory-Mapped Interface

Related Information
• Data Plane Development Kit Website
• Baseband Device Library
• 5G LDPC-V Transmitter Signals
• 5G LDPC-V Receiver Signals
• 5G LDPC-V Intel FPGA IP User Guide

2.2.1. 5G Channel Coder Throughput

The Intel FPGA PAC N3000 5G channel coder accelerator contains two encoders and
one decoder. The throughput depends on the traffic model.

For a single encoder, the clock rate, code block size (base graph number, lifting
factor), code rate affect the throughput.

Figure 7. Downlink throughput for BG1

The figure shows the downlink throughput with different parameters for BG1 (2 encoder engines).
14

12

10

8
Gbps

0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
Code Rate

Zc=192 Zc=256 Zc=384

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Figure 8. Downlink throughput for BG2

The figure shows the downlink throughput for BG2 with different parameters (2 encoder engines).

12

10

Gbps 8

0
0.2 0.3 0.4 0.5 0.6 0.7 0.8
code rate

Zc=128 Zc=192 Zc=256 Zc=384

For a single decoder, the clock rate, code block size (base graph number, lifting
factor), code rate, and literation number affect the throughput.

Figure 9. Uplink throughput for BG1

The figure shows the uplink throughput with different parameters for BG1 (iteration number is 6).
4

3.5

2.5
Gbps

1.5

0.5

0
0.3 0.4 0.5 0.6 0.7 0.8 0.9
code rate
Zc=192 Zc=256 Zc=384

AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Send Feedback
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Figure 10. Uplink throughput for BG2

The figure shows the uplink throughput with different parameters for BG2 (iteration number is 6).
3

2.5

2
Gbps
1.5

0.5

0
0.2 0.3 0.4 0.5 0.6 0.7 0.8
code rate

Zc=128 Zc=192 Zc=256 Zc=384

2.2.2. 5G LDPC-V Transmitter and Receiver Test Cases

The tables show some test case examples of the LDPC transmitter and receiver, not a
complete list. Each test case uses different values or sizes for base graph, Zc value, K’
value, code rate, Qm, E value, k0 value, ON/OFF code block CRC

Table 1. Test Cases for the Downlink

test case BG Zc K' Code Rate Qm E K0 CRC

0 0 10 184 1/3 1 300 0 ON

1 0 20 400 1/2 4 520 0 ON

2 0 40 800 3/4 4 900 600 ON

3 0 10 184 8/9 1 260 180 OFF

4 0 4 88 2/3 1 80 0 OFF

5 0 5 104 2/3 4 100 120 OFF

6 1 240 2352 1/2 1 2800 0 ON

7 1 256 2520 1/3 2 3200 2048 ON

8 1 9 88 1/3 8 96 117 ON

9 1 80 720 1/3 8 864 1200 OFF

Table 2. Test Cases for the Uplink

test case BG Zc K' Code Rate Qm E K0 CRC

0 0 10 216 1/3 2 280 330 ON

1 0 20 440 1/2 6 504 440 ON

2 0 40 880 3/4 6 882 0 ON

3 0 10 216 8/9 2 240 0 OFF

4 0 4 80 2/3 2 80 32 OFF
continued...

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5 0 5 96 2/3 6 102 0 OFF

6 1 240 2400 1/2 6 2802 0 ON

7 1 256 2560 1/3 4 3200 256 ON

8 1 9 80 1/3 8 96 54 ON

9 1 80 800 1/3 8 840 1600 OFF

Related Information
5G LDPC-V Intel FPGA IP User Guide

2.2.3. 5G VRAN Universal Verification Methodology

The vRAN universal verification methodology (UVM) simulation test environment for
the 5G channel coder incorporates the transmitter or receiver and the DMA
subsystem. The test environment does not include the preverified transaction layer
packet (TLP) adapter.

The tests randomly select 2,000 test patterns from 110,000 test patterns to test the
decoding function and randomly selects 2,000 test patterns from 110,000 test
patterns to test the encoding function. The tests also test the randomization (and
functional coverage) of system scenarios such as HARQ, physical and virtual function
(PF and VF) access, queue flushing, and reset. The reference design includes the UVM
test plan, 5G_LDPC_Test_Plan.xls.

Figure 11. UVM Tests

2.3. Fronthaul IO
The user image fronthaul IO is a simple passthrough pipe between 40GbE with
1588/PTP and 25GbE with 1588/PTP.

You can add customized IP based on the packet process between 40GbE and 25GbE,
e.g. compression and decompression IPs for O-RAN.

AN 907: Enabling 5G Wireless Acceleration in FlexRAN: for the Intel® FPGA Send Feedback
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2. 5G User Image Description
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Figure 12. Fronthaul IO

25GbE Compression IP Packet Classifier

MAC/PHY 25GbE 40GbE
Gearbox MAC/PHY
Packet Classifier
Decompression IP
IP
Customized IP
Reference Design

2.4. User Image Software

The user image requires software components and drivers, which support the
descriptor format and physical function drivers. The user image software supports the
DPDK BBDev API, FlexRAN, and OS/Orchestration.

Figure 13. User Image Architecture

VM0 VM1
Application Application

DPDK AE VF Driver DPDK AE VF Driver

vfio vfio
... ...

Control Application VF VF

DPDK AE API
User Space DPDK AE PF Driver KVM Hypervisor

Kernel Space vfio

Hardware PF

FPGA

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3. Document Revision History for AN 907: Enabling 5G

Wireless Acceleration in FlexRAN for the Intel® FPGA
Programmable Acceleration Card N3000
Document Changes
Version

2020.09.10 • Added figures to 5G Channel Coder Throughput.

• Updated Receiver signals figure.
• Updated Factory Image for 2x2x25 GbE.
• Removed O-RAN Compression and Decompression

2020.01.30 Initial release.

Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.