FPGA Implementation of a FEC Decoding

Subsystem for a DVB-S2 Receiver

Denise C. Alves1 , Cesar G. Chaves1 , Eduardo R. de Lima1,2 , Gabriel S. da Silva1 , Augusto F. R. Queiroz1
1
Eldorado Research Institute, Campinas, SP, Brazil
{denise.alves, cesar.arroyave, eduardo.lima, gabriel.silva, augusto.queiroz}@eldorado.org.br
2
PhD Candidate at Technical University of Valencia

Abstract—This paper presents the implementation of a FEC II. T HE FEC S UBSYSTEM

decoding subsystem for a DVB-S2 compliant receiver. The FEC
decoder is composed by three blocks: De-interleaver, LDPC and The main function of the FEC decoding subsystem in the
BCH decoders, and its main goal is correcting the bits that DVB-S2 receiver is restoring the useful bits that were encoded,
were corrupted by the channel during transmission. The DVB- transmitted and corrupted by the satellite channel. This is
S2 standard defines several coding schemes and interleaving achieved by three concatenated blocks, 1) De-interleaver, 2)
methods for protecting the data, and all the configurations
were considered in this implementation. This work presents the
LDPC decoder and 3) BCH decoder, which are presented in
structure and functionality of the FEC subsystem, the platform Fig. 1.
that was assembled for measuring its performance, and the FPGA
synthesis and BER performance results.

I. I NTRODUCTION
The Second Generation Digital Video Broadcasting System
for Satellite broadcasting and unicasting (DVB-S2) has been
consolidated as one of the most common choices worldwide Fig. 1. FEC decoding subsystem block diagram
regarding Digital TV (DTV). It achieves about 30% of capacity
gain over DVB-S (its predecessor standard), under the same
Although the output of the FEC subsystem in the transmit-
transmission conditions. DVB-S2 has been specified around
ter are hard-bits, i.e. bits that assume ‘0’ or ‘1’ values, the input
three key concepts: best transmission performance, total flexi-
to the corresponding subsystem in the receiver are soft-bits, i.e.
bility and reasonable receiver complexity that allows different
integer number representing probabilities that are associated
modulations (QPSK, 8-PSK, 16-APSK and 32-APSK) and
to the bits inside the frame. Those probabilities represent how
error protection levels (1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5,
likely a given bit is ‘0’ or ‘1’ and that kind of information is
5/6, 8/9, and 9/10) to be used on a frame by frame basis [1].
mandatory for the LDPC Decoder.
The DVB-S2 standard takes advantage of its improved
Forward Error Correction (FEC) subsystem to achieve a near The decoding process is executed in a frame-by-frame ba-
Shanon limit [2] performance. It is composed by the De- sis. The received symbols are soft-demapped and the outputted
Interleaver, the Low Density Parity Check Code (LDPC) soft-bits are rearranged by the De-interleaver according to the
[3] decoder and the Bose-Chaudhuri-Hocquenghem (BCH) method presented in the DVB-S2 standard documentation [1].
decoder [4]–[6]. The key characteristics, which allow quasi- The rearranged frame follows the format presented in Fig. 2.
error free operation near (0.6 to 1.2 dB) Shannon limit, are: 1) The BBFRAME section contains the useful bits while the
very large LDPC block length (64800 bits for Normal Frame LDPCFEC and the BCHFEC sections contain the parity bits
and 16200 bits for Short Frame); 2) large number of iterations that were added by the encoders before transmission.
on LDPC; and 3) the concatenation with the BCH code.
This paper presents, in details, the FEC decoding subsys-
tem that is going to be integrated in the DVB-S2 compliant re-
ceiver that has been introduced in [7]. This work also includes
FPGA prototyping results, the BER performance achieved Fig. 2. DVB-S2 FECFRAME
by this implementation, and the platform used for evaluating
its performance. The remainder of the paper is organized as
it follows: Section II details the FEC decoder. Section III The LDPC decoder receives the rearranged FECFRAME,
explains the setup used to evaluate the performance of the FEC corrects most of the erroneous bits and discards the LDPCFEC.
decoding subsystem. Section IV presents the achieved results. Next, the BCH decoder corrects the remaining errors (up to
Section V summarizes related work. And finally, Section VI 12 according to the frame type and code rate) and removes
concludes the paper. the BCHFEC. Finally, the decoded useful data, BBFRAME, is
forwarded to the following modules of the DVB-S2 receiver.
This work was supported by the IC-Brazil Program of the Ministry of Science,
Technology and Innovation (MCTI), under the grant 550467/2011-4. The De-interleaver, the LDPC and BCH decoders will be
978-1-4799-6848-0/14/$31.00 2014
c IEEE explained in subsections A, B and C, respectively.
A. De-Interleaver
The interleaving scheme is frequently used in digital com-
munication to improve the performance of FEC coding. Its
main objective is spreading the errors that often occur in burst,
so that those errors present a more uniform distribution in the
decoder input [8], as illustrated in Fig. 3.
Fig. 3. De-interleaver error spreading
The De-Interleaver block rearranges the data that has been
arranged in a non-contiguous way into its original sequence. In
order to achieve this, the input data must be written and read
in a specific way, so the storage is made based on a structure
of c columns and r rows. In the de-interleaving process, each
received bit (or the associated soft-bit) is written row-wise
and read out column-wise, reversing the interleaving process,
as shown in Fig. 4.
Fig. 4. De-Interleaving Scheme
The number of rows and columns of the adopted structure
depends on the DVB-S2 modulation format. The whole process
is not applied to the QPSK modulation due to the robustness
of this modulation.
B. LDPC Decoder
The LDPC Decoder is responsible for decoding a sequence
of bits inside a frame, based on the soft-bits that carry channel
information. Those soft-bits are the quantized version of the
P (xn =0|yn )
Log Likelihood Ratios LLR(xn ) = log P (xn =1|yn ) , which
express how likely a given bit is ‘0’ or ‘1’, so that the more
positive the LLR is, more likely the bit is ‘0’, and in the same
way, the more negative the LLR is, more likely the bit is ‘1’.
For decoding LDPC codes, the Minimum-Sum algorithm, a
simplification of the Belief-Propagation (BP) based on LLRs
[9], was implemented with a layered decoding [10] approach.
The basic idea of this iterative algorithm is exchanging mes-
sages between Variable Nodes (VNs), corresponding to the
received bits/symbols, and Check Nodes (CNs), correspond-
ing to the parity-check equations, in order to calculate new
probabilities.
In layered decoding, a VN is represented by its Soft-output
(SO) value, that is nothing else than the LLR that is frequently
updated during the iterations, and one iteration is split into
sub-iterations, one sub-iteration for each layer made of one or
several CNs. Assuming that Ln is the initial LLR of bit n,
Qn is the LLR (or SO) of bit n considering all the messages
exchanged so far, Qnm is the message sent by VN n to CN
m, Rmn is the message sent by CN m to VN n, and N (m)\n
is the set of VN’s connected to CN m excluding n, the steps
of the layered decoding algorithm are:
1) Initialization: Qn = Ln , Rmn = 0
2) VN message calculation: Qnm = Qn − Rmn old

3) CN update: Rmn = f (Qn m ), f or n ∈ N (m) \ n
new
4) SO update: Qnew n = Qnm + Rmn new
5) Decision: if all the VNs satisfy the check equations,
a codeword was detected, so finalize algorithm; if
the maximum number of iterations was reached, the
decoding failed, so finalize algorithm; otherwise go
to step 2 for the next iteration.
Using the Minimum-Sum derivations, the function f (.),
corresponding to the CN update step, can be expressed in two
ways, with α and β being configurable parameters:
• Offset Min-Sum:
 
  
Rmn ≈ sign(Qn m ) max min|Qn m | − β, 0
 n
n
• Normalized Min-Sum:
 
  
Rmn ≈ sign(Qn m ) min

|Qn m | /α.
n
n
For connecting the VNs to the CNs, a parity-check matrix
is defined, and the same matrix must be used by both encoder
and decoder. For each one of the 21 frame configurations (con-
sidering the combination of 11 code rates and 2 frame lengths),
the DVB-S2 standard defines a different coding scheme, which
makes the LDPC feature the most complex part of a DVB-S2
FEC subsystem [11]. Although their contents are different, the
parity-check matrices follow a well defined structure based
on an address table and a code rate dependent constant, but
they can be rearranged so that they are composed of shifted
Identity sub-matrices, which makes the parallelization of the
decoding algorithm easier. Given that the parity-check matrix
is defined as H = [A | B], with A connecting the parity-
check equations to the information bits, and B connecting the
equations to the parity bits, the rearranged H matrices in DVB-
S2 are exemplified by Fig. 5.
Fig. 5. Structure of the rearranged H matrix
 Each shifted Identity sub-matrix connects a Check Node
Group (CNG) to a Variable Node Group (VNG), and each
group is composed of P = 360 nodes. The B side of H
presents the same format for all frame lengths and code rates,
while the A side varies for each configuration, as well as the
number of CNGs (q) and information VNGs (i). The paral-
lelism of a hardware-implemented decoder can be achieved
by processing all the CNs of a given CNG at the same time.
One BP iteration is split into q sub-iterations, one for each
CNG (layer), and a sub-iteration consists in updating all the
VNs connected to the CNs inside current CNG.
The structure of the standard matrices allows a parallelism
of 360, i.e. 360 logic elements executing the message update
calculations at the same time, without interfering in the results
of each other. The LDPC decoder implemented in this work
supports two levels of parallelism, 180 and 360, which can be
chosen according to the hardware resources available for the
project, concerning both logic and memory. Fig. 6 presents
the LDPC Decoder diagram, with emphasis on the memory
banks and on the logic elements that parallelize the decoding
algorithm.
Fig. 6. LDPC Decoder data flow
The update steps of layered decoding are executed by the
Check Node and Variable Node Processing Units (CNPUs
and VNPUs), one CNPU-VNPU pair for each CN inside the
CNG that is being updated. In addition to those processing
units, there are other logic elements responsible for receiving
the initial LLRs, shifting the messages in each sub-iteration
according to the H matrix configuration, controlling memory
access, checking the parity at the end of each iteration and
transmitting the decoded bits. For the parity-check matrices,
one ROM block is used, and for the BP messages, three
RAM banks, two for the SOs (SOM0 and SOM1) and one
for the CN messages (CNM). The two SO Memory banks are
alternately used to receive the initial LLRs of next frame and
to update the SOs of current one, so that while a given frame
is being decoded by the update and check modules, the LLRs
of the next one can be buffered by the Soft-bit Rx sub-block.
More details about the architecture of the implemented LDPC
Decoder can be found in [12].
C. BCH Decoder
The BCH-Decoder uses the BCHFEC bits for recovering
the original BBFRAME, with a t error correction capacity of
up to 8, 10 or 12 errors according to the code-rate and frame
type. This is accomplished by following Algorithm 1.
Algorithm 1 BCH decodification
Input: R: FECFRAME without LDPCFEC bits.
Output: C: Recovered BBFRAME .
1: C = BBFRAME part of R.
2: Calculate syndromes S.
3: if S = 0 then
4: Determine the Error Locator Polynomial σ.
5: Find the roots of σ.
6: Swap the bits of C that correspond to the
Galois inverse of the root.
7: end if
8: return C
Based on Algorithm 1, the BCH decoder was designed as
illustrated in Fig. 7, where the BCH Control Unit contains a
finite state machine to orchestrate each step of the decodifi-
cation process and a Memory Buffer stores the FECFRAME
until the Polynomial Roots Finder is ready to signalize which
of the bits of the frame have been swapped.
Fig. 7. Internal architecture of the proposed BCH decoder
As mentioned in [13], the calculation of syndromes (S)
can be done by considering the received frame as a poly-
nomial R(x), and substituting the first 2t α elements of the
Galois fields established for normal and short FECFRAMEs
in [1] (i.e. GF(216 ) and GF(214 ), respectively), as expressed
in Si = R(αi ), where i ∈ {1, · · · , 2t}. For the Syndromes
Calculator, the design detailed in [14] was implemented. The
Key Equation Solver is commonly based on the Berlekamp-
Massey (BM) algorithm, and in this work was adopted the
Simplified inversion-free BM (SiBM) (Algorithm 2) with the
corrections made in [15]. This variation is optimized for
binary codes and avoids the complexity of GF invertions [16].
The Polynomial Roots Finder is based on the Chien Search
algorithm, but since the DVB-S2 uses 21 shortened BCH
codes, it was used the variant from [17] illustrated by Fig. 8,
where β = 2Kbch − Nbch − 1.
Fig. 8. Shortened Chien Search
Algorithm 2 Simplified inverse-free Berlekamp-Massey The reason for using the constellation points instead of the
Input: t: Error correction capacity. mapped symbols, that could also be obtained from the offline
S: 2t Syndromes calculated for the received FECFRAME. database, was that the chosen configuration (Memory+Mapper)
Output: σ: Error Locator Polynomial. would save memory resource, since the symbol representation
1: κ(0) = 0, γ(0) = 1 (in-phase and quadrature components) requires much more
2: δi (0) = θi (0) = Si ∀ i ∈ {0, 1, 2, ..., 2t − 2} bits than a concatenation of bits that varies from 2 (QPSK
3: δ2t−1 (0) = θ2t−1 (0) = 0, δ2t (0) = θ2t (0) = 1
modulation) to 5 (32-APSK).
4: for r ← 0 to t − 1 do
5: δi (r + 1) = γ(r)δi+2 (r) + δ0 (r)θi+1 (r) The error source for the Bit Error Rate (BER) measurement
∀ i ∈ {0, 1, 2, ..., 2t} is an external Noise Generator, which provides a complex
where δ2t+1 (r) = δ2t+2 (r) = θ2t+1 (r) = 0 baseband noise through two separate channels, one for each
6: if δ0 (r) = 0 and κ(r) ≥ 0 then
7: θi (r + 1) = δi+1 (r)
symbol component. Those components are analog-to-digital
∀ i ∈ {0, 1, 2, ..., 2t} \ {2t − 2 − 2r, 2t − 3 − 2r} converted and then passed to the system as the noise, which is
8: γ(r + 1) = δ0 (r) incorporated to the signal by the adder. The target Signal-to-
9: κ(r + 1) = −κ(r) Noise Ratios (SNRs) are adjusted by attenuating or amplifying
10: else the amplitude of the generated noise through a combination of
11: θi (r + 1) = θi (r) external attenuators and internal multiplier.
∀ i ∈ {0, 1, 2, ..., 2t} \ {2t − 2 − 2r, 2t − 3 − 2r}
12: γ(r + 1) = γ(r) The SNR values are calculated by the SNR Estimator block.
13: κ(r + 1) = κ(r) + 1 As it can be seen in Fig. 10, the SNR Estimator has the Power
14: end if Signal sub-block, which is instantiated twice. The instances
15: θi (r + 1) = 0 ∀ i ∈ {2t − 2 − 2r, 2t − 3 − 2r} are responsible for providingthe signal and noise powers
16: end for 2 2
calculated by Px = |x| = Ix2 + Q2x = Ix2 + Q2x . This
17: σi = δi (t) ∀ i ∈ {0, 1, 2, ..., t}
18: return σ
process is repeated an specific amount of times, accumulating
the results and averaging them, in order to avoid abrupt
variations and make the final result more reliable.
III. FPGA P ERFORMANCE M EASUREMENT S ETUP
In order to measure the performance of the FEC subsystem,
a verification platform was designed as presented in Fig. 9.

Fig. 10. SNR estimator internal architecture

The last step of the estimation process is obtaining the

relation between both averaged powers SN R = Ps /Pn .
For this calculation, a CORDIC IP is used, and to avoid
underflow/overflow problems, the numerator is scaled and
suited so that the output of the CORDIC can fit within the
expected range.
Based on the received symbols and on the estimated linear
SNR, the Soft-demapper calculates the soft-bits and then the
FEC subsystem processes the data in a frame-by-frame basis.
As the De-interleaver must receive a complete frame before
starting the deinterleaving process, a FIFO is instantiated
Fig. 9. FPGA performance measurement setup
between this block and the Soft-demapper in order to buffer
the frame. Afterwards, the FEC output is compared with the
data read from the Payload Memory by the Error Calculator
The stimulus and output references come from a database
to calculate the Bit Error Rate (BER).
that was generated by a DVB-S2-compliant transmitter model.
This database contains the data (in bit or symbol format)
processed by each step of the transmission flow.
Inside the FPGA, there are two memory blocks: the Code-
word Memory, which contains the constellation points that
must be converted into symbols by the Symbol Mapper; and
the Payload Memory, which contains the payload (the same
mapped bits excluding the parity bits) that must be used
as reference for checking the FEC output. The data stored
in each memory correspond respectively to the interleaved
FECFRAME and the BBFRAME presented in Section II. Fig. 11. Error Calculator internal architecture
 The Error Calculator is composed by two parts: the Data factor β being 1, and for the other code rates, it was the
stream synchronization and the Bit comparison, as presented in Normalized Minimum-Sum with α = 2 (realized in hardware
Fig. 11. The first part stores the FEC output and the Reference by a shift operation). The combination of external attenuators
output separately into two buffers and aligns them in order to and internal scaling factor was arranged so that the required
avoid the comparison of non-correspondent bits. The second SNRs could be properly set.
part compares the two streams and counts the mismatches
found within the specified Amount of samples. When this value For all code rates, the test was executed by accumulating
is reached, the Sample Counter signalizes that the output of the errors in 1011 useful bits (discarding the parity bits). This
Mismatch Counter is valid. Afterwards, the BER is calculated number was calculated considering that the standard defines
by dividing the Amount of errors by the Amount of samples. It QEF performance as a Packet Error Rate (PER) of 10−7
is worth to notice that since the SNR Estimator takes some time [1], and each packet is composed by 188 bytes (1504 bits).
for delivering a valid estimation, the Error Calculator begins Therefore, one erroneous packet in 107 is equivalent to one
the calculation with the first bit of the second valid frame. erroneous bit in 1.504 × 1010 , which results in a BER of order
10−10 . Once the test was executed for all code rates at the
IV. I MPLEMENTATION R ESULTS target SNRs, the SNR values were gradually decreased to draw
the Bit Error Rate (BER) curves presented in Fig. 12.
The FEC modules presented in Section II were imple-
mented using the VHDL hardware description language and LDPC + BCH Bit Error Rate
-4
10
properly verified through the combination of two tools: GNU 3/5
2/3
3/4
Octave [18], for implementing golden models, and GHDL [19], 10-5 5/6
8/9
for RTL simulations. The functional verification was executed 10-6
9/10
3/5(standard)
for each module individually and also for their integration. For 2/3(standard)
3/4(standard)
5/6(standard)
physical verification, the FEC subsystem was integrated with 10-7
8/9(standard)
9/10(standard)
the platform presented in Section III, and the entire structure

BER
10-8

was synthesized for the Stratix IV GX FPGA development kit

10-9
from Altera [20]. The resource usage is detailed in Table I.
10-10
TABLE I. FPGA PROTOTYPING RESULTS FOR A LTERA’ S S TRATIX IV
-11
10
DSP elements
Entity Comb ALUTs Registers Memory bits
18-bit / 18x18 / 36x36
10-12
Main platform elements 5 6 7 8 9 10 11
Config RAM 39 108 88 0/0/0
Es/No
Stimulus RAM 55 38 64800 0/0/0
Mapper 89 30 0 0/0/0
Fig. 12. BER performance
Noise scalers 0 0 0 4/2/0
SNR estimator
Monitoring RAM
2328
40
1997
120
45
100
4/2/0
0/0/0
At the SNR points established by the standard (drawn in the
Reference RAM 56 36 58192 0/0/0 bottom of Fig. 12), the BER was zero for code rates 3/5, 5/6,
Error Counter 334 275 0 0/0/0 8/9 and 9/10, 10−10 for 3/4, and 10−7 for 2/3. Assuming that
FIFO
IP’s (part of the receiver)
87 68 393216 0/0/0
the maximum tolerable BER must be in the order of 10−10 ,
Soft-demapper 821 259 0 6/3/0 as previously presented, the gain of the implemented FEC can
Deinterleaver
LDPC Decoder
275
56615
106
58923
388800
4234976
8/0/2
0/0/0
be calculated by the difference between the SNR established
BCH Decoder 9146 1250 58192 0/0/0 by the standard and the SNR value that delivered, during the
Others (debug, glue logic etc) 764 2715 23168 0/0/0 test, a BER equal to zero or in the order of 10−10 . The gain
Total 70649 65925 5221577 22 / 7 / 2
was not calculated for code rate 2/3. Table II summarizes the
error performance results.
The objective of using this platform was not only verifying
the functionality of the implemented FEC subsystem, but TABLE II. QEF PERFORMANCE REQUIREMENTS AND ACHIEVEMENTS
also measuring its performance for AWGN channel over a
SNR range. Nevertheless, the test does not take into account Mode Target Es /N0 (dB) Es /N0 with Performance
tolerable error gain (dB)
real world impairments such as timing, frequency and phase 8PSK 3/5 5.5 5.23 0.27
errors. The DVB-S2 standard [1] defines the target Es /N0 for 8PSK 2/3 6.62 not found not calculated
Quasi-Error-Free (QEF) performance in each operation mode 8PSK 3/4 7.91 7.91 0
(modulation and code rate). For converting the variable Es /N0 , 8PSK 5/6 9.35 8.67 0.68
which considers single sided noise power spectral density, 8PSK 8/9 10.69 9.39 1.60
into the real SNR, which is based on double-sided noise, the 8PSK 9/10 10.98 9.6 1.38
formula SN R(dB) = Es/N o(dB) + 3 was used.
In this work, six code rates were tested: 3/5, 2/3, 3/4, For code rates 3/5, 5/6, 8/9 and 9/10, the standard require-
5/6, 8/9, 9/10, all of them for normal-length frames. The ments were met with a reasonable slack, keeping the error
modulation was 8-PSK. The LLRs were quantized by the rate equal to zero for SNR values smaller than the target ones.
Soft-demapper into 6 bits, and inside the LDPC decoder, they For code rate 3/4, there was no gain, since the error was in the
could be extended to 7 bits. The CN messages (also called order of 10−10 (still tolerable) at the target SNR (7.91 dB). The
in the literature “extrinsic” messages) were quantized into 5 test for code rate 2/3 dit not achieve the standard requirement,
bits. For smaller code rates (3/5 and 2/3), the LDPC decoding since the BER was in the order of 10−7 (not acceptable). This
algorithm was Offset Minimum-Sum with the quantized offset is an issue that must be analized in future works.
 V. R ELATED WORKS
This section presents some works that have been previously
developed, however the task of comparing results is not simple
since the referenced papers used different tools or methodolo-
gies to present performance and synthesis results. Therefore
the goal of this section is not to indicate the best solution, but
introduce some approaches that are available in the literature.
Paper [11] presents a FEC IP for DVB-S2 that reduces
clock frequency and memory consumption while offering the
same throughput achieved in previous works. It proposes a
variation for the Minimum-Sum algorithm and presents the
BER curves for QPSK and 8-PSK. The synthesis result is
compared to the ones presented by the authors of [21]. In
[22], the goal is optimizing the number of quantization bits
for the LDPC decoder synthesized for a Xilinx FPGA. The
paper details the LLR and message quantization and presents
some BER curves, but it does not indicate the modulation
either the target SNR. Therefore, it is not clear whether the
standard performance requirements are achieved. In [23], a
new method is proposed for adapting the normalization factor
of the Minimum-Sum algorithm in order to improve error
performance. It presents the hardware architecture and proves
via computer simulations that the proposed method delivers a
better BER curve, but it does not present synthesis results.
There are still other works focusing on throughput and low
power, as [21], [24], but in general, most of the papers present
BER performance based on computer simulations, different
from this work, which provides error performance analisys
based on tests executed in hardware.
VI. C ONCLUSION
This paper presented the implementation of a FEC sub-
sytem for a DVB-S2 compliant receiver, as well as the syn-
thesis and error performance results. The novelty of this work
is proposing, in adition to the FEC architecture, a verification
platform that includes the Design Under Test and the other
components used for inserting real noise and computing errors,
in order to speed up the process of identifying the best hard-
ware setup (quantization, LDPC decoding algorithm parame-
ters etc.) for each operation mode (frame length, modulation
and code rate) available in the DVB-S2 standard. Except for
the case of code rate 2/3, the implementation meets the QEF
performance requirements by achieving error rate equal to zero
at the target SNRs for most of the code rates available in 8-PSK
modulation. Moreover, for the highest code rates, it delivers a
reasonable gain over those requirements, being the maximum
gain of 1.6 dB obtained for code rate 8/9. For future works,
the cases of code rates 2/3 (requirement not achieved) and
3/4 (tolerable error rate), which presented errors at the target
SNR points, will be investigated in order to improve the error
performance in those operation modes. Furthermore, the other
modulations will be tested as well.
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