A High-Performance 16-Bit Architecture With 32-Bit Migration 28000 ™16 Bit CPU's Z80,000™ 32 Bit CPU's Inthe office, in the factory, even in thehhome--every day the ‘number of people using microprocessors grows. Andevery ‘day, these poople dream of new applications and better systems. Systems thal are faster, more reliable, easier to Use, and yet cost less. ‘To the designer, this vision of the future means building systems with more processing power, communications interfaces, efficient use of large memories, and software that is both more sophisticated and more reliable. To get these systems to market quickly and with minimal devel- ‘opment costs, the designer needs powerlul building blocks-circuils and software designed to work together. Ziog’s 78000 Family was bom of this vision. Using advances in VLSI technology, the wealth of experiance with 16-bit architecture and the overwhelming success of its8 it microprocessor family, Zlog conceived the 28000 Famiy as a bold ancwor 10 the neods of the system designer. ‘The Established Leader Zilog 280 CPU has become synonymous with high- performance, low-cost computing. Its system-oriented instruction se, eficient use of package and pins, broad range of peripherals, and extensive hardware and software support have earned it frst place in the 8-bit world, Used in applications that range from intelligent {terminals to powerful microcomputer systems and device controllers, the 280, Ziog’s embodiment of the ‘bit solution, has become the standard of the industry. 16 Bits and Beyond With this successful pracedent leary in ind, Zilog de- ‘idedto extend the 280 tradition to 18 and 32bits. Thenew processors place the power of 16 and 32 bits in the Gesigner's hands. Like the Z80 they create a way o apply advanced architectural concopts fo solve the real world problems of high performance microprocessor users. They also pave the way for new, compatible industry standards in the 16- and 32-bit CPUs, in peripherals andin software. By drawing onthe architecture of minicomputers and mainframes, Zilog looked for and found a break- through, the 28000 Farmily ‘A broad range of processing power and the need to ‘manage vast amounts of memory are inherent in 16- and 32-bit systems. But small systems and real-time pertorm- _ancemustnotbepenalizedby these tacts. twas essential, therefore, that each device be designed as an integral part ‘of a family concept “The 28000 Family is built around a defined set ol intercon- nections and protocols called the Z-BUS, 0 circuit con- ‘nections for present and future family members are allcom- patible. Memory management, OMA transfer, and ox- {ended processing have all been planned from the begin- ring. Atthe low end, 280 users cannow intertaceto 16-and ‘32-bitprocessors by using the new highly integrated 2280 PU, a 16-bit CPU that has 280 code on ZBUS. Atthe high ‘end 28000 users can now integrate to the 280000 22-bit microprocessors and sillrun their 16-bit software. A high ‘speed, shared parallel bus, the Z-BUS provides all func- tions with @ communication interface, as Figure 1 ius trates. Figure 1. Z-BUS Connects All FunctionsSystem Flexibitty. Even the smallest 28000 systems offer high throughput and eany programming far superior to any existing micro- processor allamative. In mic-range applications, 28000 components otfer very powerful solufons to the design Problems of word processing, infoligent terminals, data, communications, instrumentation, and process conto. In acomplexnetworkofmulliple processors, smari peripheral components, and a distributed memory configuration, the 28000 Family provides pertormanco and versaity ex- ‘ceeding thatof much arger-andtarmore expensive micro- Processors. Higher Throughput ‘Tho powerful instruction set, high execution speed, regular architecture, and numerous special features ofthe Z8000 microprocessors dramaticaly increase system through put. Inteligent 28000 peripheral controllers and extended processing units unburden the CPU and boos! throughput even further. ‘The processing power ol the Zilog 28000 16-bit micropro- ‘cessor can be boosted beyond its intrinsic capability by Extended Processing Architecture. Simply stated, EPA allows the 28000 CPU to accommodate up to four Ex- tended Processing Units (EPUs), which perform spocial- ized functions in parallel with the CPU's main instruction execution stream, as Figure 2 illustrates. ‘The use of extended processors to boost the main CPU's performance capability has been proven with large main- frame computers and minicomputers. In these systems, specialized functions such as array processing, special inpuvoutput processing, and data communications proo- essing are typically assigned to extended processor hard- ware. These extended processors are complex computers in their own right ‘An Unmatched CPU “The 78000 microprocessor is not usta wider data path, more regstrs, more data types, more adoressing modes, more insructions, and more addressing space. It brings bigmachine concepts tothe lovel of components lis general-register architecture avoids bottlenecks associ- ‘ated with dedicated or implied registers. Special features ‘suppor parallel processors, operating systems, compilers, and the implementation of virtual memory ‘The Z8000 CPUis also a very fast machine. Is through: utis groator than that of any other 16-bit microprocessor with comparable clock speeds. And the Z8000 CPU is available wth speeds ranging fromamoderate 6 MHz clock tale that allows you the choice of slow-access, low-cost ‘memories to a high-speed 10 MHz clock rate for high- performance systems. From the three versions of the 28000 microprocessors, youcan select the onebest suited to your needs: the 28001 for large memory applications, the 28002 for small memory applications, or the Z160 for the low cost, medium memory size applications. Peripheral Problem Solvers ‘The 28000 Peripherals offer more than simple answers to the basic needs of a microcomputer system. Complicated system tasks that previously required burdensome MS! Grcuitry can now be handled offline. Even such highty specialized functions as data encryption/decryption are performed by Zilog peripherals. These mulitunction pe- fipherals are extensively programmable so each can be precisely tailored tots application. Each can be made to perform complex, inteligent tasks on its own--to unburden the CPU, reduce bus traffic, and increase system through put Counting, ting, and parallel VO, for example, are made 2asy by the 28036 Z-ClO Counter and Parallel VO Circuit with its three 16-bit counterRimers and three 8-bit parallel WO ports. It can even function as a programmable inter. ‘pt prionity control. Ease of implementation characterizes the interlace be- twoon the 16-bit, mutiplexed 28000 CPU and ts 2-BUS peripherals. The Z-BUS ensures not only thal commumnica- tions betweon Family members are consistently simple, but also that the resolution of interrupt prioties requires minimal CPU involvement. o ga Figure2. Typical Extended Processor Configuration=). Data communications are detty handled by the ZB030 Z- SCC Serial Communications Controler; a dual-channel ‘mult-protocol component that suppor all popular com- ‘munications formats. Now also available in CMOS, Direct memory access is supported by the 28016 DTC ‘Transfer Controller, a fast dual-channel device thal en- ‘hances memory and VO dala transfers within stand-alone Processor or parallel processor environments, Elements of asynchronous parallel processing systems are interconnected by the 28038 FIFO unit, a surprisingly flexible device whose butfer depth can be expanded with- ‘ut mit using the 28060 FIFO Butfer Unit. ‘The 28068 Z-DCP Data Ciphering Processor, supporting three standard ciphering options and key parity checking, Provides encryption and decryplion of dala where needed. ‘The Z:DCP can input, output, and encipher simultane ‘ously. ‘The Z8010 Z-MMU Memory Management Unit provides flexibly in code segmenter page ralocation and sophisti- cation in memory protection rarely found in the micropro- cessor world, This device encourages modular software development-a critical factor as programs reach new levols of complexity. Universal Peripherals, Extend the Range of Applications to increase the range of ‘applications forts peripheral, Zilog selected certain of the ‘multiplexed Z-BUS-compatible 28000 Peripherals to be roducedin.a second bus version: anon-multiplexed 16-bit CPU-compatibie line, called the Z8500 Universal Periph ‘ral. The 28536 CIO, 28530 SCC, and thé 208516 DTC are al "Universal" versions f their 28000 counterpartsand ‘as such incorporate the same extensive features to por: form the same impressive functions. The 28038 Z-FIO, andby extension the 28060 FIFO, are compatible with both bus versions, and so endow both Families with their multiple strengths, ‘Toholp meetthe timing requirements ofboth Zilog andnon- Zilog microprocessors, the 28581 CGC Clock Generator and Controller has been added to the ZB500 Universal Peripherals group. The CGC outputs drive the Z80 and 8000 CPUs clock inputs directly; no bus intertace is required. Selective dlock-stretching abilities provide a variety of timing outputs to make this a versatile chip suitable for VLSI and LSI devices. Table 1 summarizes the ‘28000 CPU and peripheral offering. ‘Simply put, the 28000 Family offers more for less money. ‘The 28000 microprocessors give mid-range minicomputer performance al microprocessor cost. At component prices, 28000 peripheral controllers perform complex system functions thal previously required an entire PC board. Figure 3. 28000 Interface‘The 32-bit Migration Ziog has now comploted the migration from the 16-bit to the 32-bit CPU, withthe 280,000 and 280320 or the 2320. ‘Software compalibe othe 28000 CPUs, the 280,000 and 320 provide flexibility atthe cost ota 16-bit CPU. Oriented {othe applications in which high throughput is required, its fie of 18 general-purpose 32-bit registers handles bytes, words, and long words wilh equa facity. The rch instruc: tion set combines powerful addressing modes and opera- tions in @ manner that aids assemibly-language coding of {ime-citcal applications, and sil provides the compiete- ‘ness desirable for officent compile-gonerated code. ‘The 2320 CPU canbe configured under software contralto Use 16-bit logical addresses (ideally suited for high-speed controller applications) or 32-bit addresses (lor large-5ys- temtasks). The 32-bitaddress modes support both alinear addressing space and an allemative segmented address- ing space, which are selected by the user according to the application's requirements. ‘Other system features include System and Normal modes of operation, a sophisticated trapping mechanism, a high- performance bus stucture, and builtin mutiprocessor ‘support with global memory access arbitration signals for ‘easy requost and acknowledge handshaking. ‘An on-chip cache and memory management unit (MMU), ‘coupled with a sophisticated instruction pipetine, enable the 2320 to execute instructions at arate of up to one in- struction per processor cycle. The 256-byte cache pro- vides an automatic butfering mechanism to hold the most recently fetched instructions and data on the chip. Thus, subsequent references to theso items do not require lengthy memory transactions butinstead can be fetched in a single processor cycle. ‘The memory management unit on the chip contains allthe information needed to translalo the most recently used logical addresses generated by the CPU into the physical ‘addresses used by the memory system. With each ad- dress translation, access attibutes are automatically ‘checked to determine whether or not the access is permit ted. The MMU can be used fo implement a virtual memory ‘orcan be disabled entirely for applications thal do not need ‘memory management. Peripheral Support. The 2320 uses Zlogs Z-BUS so the entre 28000 failyof circuits are available for use wit it. Multfunction Z-BUS peripherals are extensively programmable, so each can be precisely tailored to an application Z-BUS Component interconnect ‘The Z-BUS is a high-speed parallel shared bus that links the 28000, 2320 microprocessor families and Extended Processing Units with tne peripherals needed to implement ‘complete systems. Through a common communications intertace, Z-BUS peripherals and CPUs support the fllow- ing types of transactions Data Transier. 16 or 32 bits of data can be moved between bus controllers (such asa CPU) and associ ated peripherals. Interrupts. Interrupts can be generated by peripher- als and serviced by CPUs over the bus. Resource Control. A daisy chain priority mechanism ‘supports distributed management of sharedresources which includes peripheral devices and the bus itsel Thehearlofthe7-BUSisasetot mulliplexedaddress/data lines and the signals that control these ines. Multiplexing data and address onto the same ines makes more efficient use of pins and faclitates expansion ofthe numberof data and address its. Mutiplexing also alows straiht-lorward addressing of a peripherals intemal rogisters, which greatly simplifies YO programming. ‘Adaisy-chained prirty mechanism resolves intemupt and resource requests thus allowing distributed contol ofthe bus and eliminating the need for separate priority contro tors. ‘The resource-control daisy chain also allows wide physical ‘separation of components, Furthermore, 2-BUS is asynchronous in the sense that peripherals need nt be sychronized with the CPU clock ‘All §ming information is provided by Z-BUS signals. ‘As a result of a common hardware interface and protocol, Users can be assured that adequate system support for their 28000 or 2320 system design is readily availabe for the Z-BUS peripherals and Extended Processing Units:ae ==) pus masTan Figure 4. Z-BUS SignalsTABLE 78000 PRODUCT OFFERING PartNo Device Name Description ‘Speed 20800172 8001 16-bit Intomal/Exiernal CPU, 16x 6.10 Za002 16-bit General Purpose Registers 16-bit CPU 8M Byte Addressing 708160 z160 16-bit intenal/E xtemal CPU, 16x 6.10 v ‘16-bit CPU 16-bit General Purpose Registors ‘2M Byte Addressing 80320 z320 32-bit InternalExternal CPU, 32x 80000 80K 32-bit General Purpose Registers 8,10 VG 32-bit CPU 4G Byte Addressing 08010 wmu Provides Dynamic Memory Segment 6.10 Pp Rotocation of Blocks from 256 to 65,532 Bytes, Protection Features 708016 pre 2 Independent, Multi-functional 48 PY 708516 ‘Channels that Control Memory ‘Translers up to 6M Byte/sec 08030 sco 2 Independent, Full Duplex Channels, 468 POVCL 208690 ‘Transfer Rates from 010 1.5M bits/sec, Syne & Asynchronous Modes 708036 clo 2 Independent 8-it General Purpose 46 POVCL 208596 Devices, satisfies most Counter/Timeor ‘and Parallel VO needs 08038 FIO 128 byte, Asyne, Bidirectional FIFO +8 DP.VCL Butter with VO Control Logic on Board 708060 FIFO 128 x 8-bit Memory, Bidirectional MB/sec PC ‘Asynchronous Dala Transfer Capability 08068 bcp Enerypts and Decrypt Data 4 Pp Using Three Standard Ciphering Modes 208881 cece 2 Independent 20 MHz Oscilators 6.10 POL ‘Output Directly to 280, 28000 and other CPUs zB0cs0 = CMOSZ-SCC CMOS Version is Pin 68,10 Pvc Compatible with the Standard NMOS DeviceTABLE - 1 Z8000 PRODUCT OFFERING (Cont) Package a PartNo Device Namie Description ‘Speed Zesc20 ‘cos sec. (CMOS Version is Pin 68,10 Pvc ‘Compatible with the Standard NMOS Device 07654 765A Floppy Disk Controller (FDC) 8 Py Floppy Disk interfaces Microprocessors to Control up to Four Floppy Disk Drives z72208 ‘72208 High-Performance Graphics Display 8 v Controller interfaces with Micro- processors to Generate Displays 05980 scsi (CMOS, Asynchronous SCSI Protocol 1.OMBisec = P.V Packages: P=Plastic DIP, V=PLCC, C=Ceramic, D=Cerdip, G=Pin Grid Array, Lel.CC, “=Available while 4 MHz supply laste