*“ZILOG INC WE D October 1988 FEATURES '§ Ful2bit architecture and implementation 18 4G bition) byes of cirectly addressable memoryineech ‘lfour adress spaces, |= Linear orsegmanted aderass space | Vitual memory management integrated wih CPU "= On-chip cachememory 1 General purpose register file wih sien S2-bi registers 1 Nine general addressing modes ‘= Numerous data types include bt, bt fed, logical vale, Signed inogar and sing ee mi 9984043 0021795 & mm ou NLaNaeee eee ts tikes ees 2320™ CPU 1 Regular use of operations, aderessing modes, and data ‘ypesininstructon eet '= System and normal modes of operation wih separate tacke 1 Sophisicatedintewupt and tap handling |= Softare isa binary-compatibi extension of 280008 ‘software, totaly compatbe withthe 280,000 "Small low cost 68:pin plastic leaded chip carior ‘package for surface mount applications |= Hardware is compatible with other Z:8US@ bus ‘components with muttploxed address end data 1 Mainframe pertormance at a micro price GENERAL DESCRIPTION ‘Tho 2320 CPU isan advanced, high-end 92-bit Microprocessor that integrates the ‘architecture of ‘mainframe computer into a single chip. While maintaining full compattoily with 28000. family ‘sofware and ‘hardware, the 2320 CPU offore greater power and Alexbity in both ts arcitectur and Interface capabily. ‘Operating systems and compilers are easly developed in the 2320 CPUS high-quality environment, and. the hardware interface provides for connection to a wide ‘ately of systom eoritguration, ‘Adddressos in the 7320 CPU are 22 bits. This allows Gioct addressing of 4G bytes In each of four addross spaces: systom-mode data, systemmode instucton, ormaFmode dala, and normalode Instuction. The PU supports three modes of address representation, ‘The 16-bit compact addresses are compatible. wit 28000 nonsegmented modo. The 32-bit eegmented Addresses include both 16-bit ots, which Is compete with 28000 segmented modo, and 24-bit occ. In Aaddlion, a ful 92-bit linear adaress space ls provided. ‘The CPU featuros a generatpuppese registor fe with sideen 92-bit registers and nino operand addressing choices for compact representation or for tll 82-bit addressing. The inetructon set can operato on bit, bit field, Topical value, signed integer, unsigned interger, ‘adéress, sing, stack, and packed decimal byte data ‘ypes. Logical and aithmatio instructions operated on bles (@ bis), words (16 bls) and longwords (32 bis). ‘The Extended Processing Arcitactre (EPA) supports tighy regular in combining operations, data types, and ‘addressing modes. High-ovel fanguage compilation is supportd with instuctions for procedure linkage, arty ‘index calculation, and bounds checking.” Other Instructions provide operating system functions such as ‘system call and contel ef mematy management ‘hore ere two main operating modes, system’ and ‘ormal, supported by separate slacks, Usor programs ‘operate in notmal ‘mode, while sensiive peratng system functions are performed in system modo. This Protects critical parts of tho operating system from user ‘access. in addlion, some instructions are priveloged, ‘and execute ony in system mode. Memory managoment funcions protect both system memory from. User ‘Programs, and user momory from olher users. Vecored onvectored, and nonmaskable inforupls support Featline operating systems+ ZILOG INC ‘Memory managmement is fly integrated with the CPU; fo extemal support circuitry Is necessary. A paging ‘address translation “mechanism is implemented, Registre in the CPU point to address transation tables {cated in memory; the most recenty used table enties are kopt in a Translation Lookaside Butler (TLB) inthe GPU. The CPU performs logical to physical address lwanstation and access protection for each memory foterence. When a logical memory referenoo causes translation or protection violation, the stale of be CPU ie automaticaly restored to restart the instruction. VO ports {Gan be referenced ether by desieatad instuctione or by {he memory managemont mechanism mapping logioa ‘momery addresses to VO port addresses, Extensive trapping facilis, such a¢ integer overton, ‘Subrange out of Bounds, and subscript out of bounds, catch common run-ime error, Software debuggers can tse trace and breakpoint traps. Privileged netucton {taps and memory protection vciation taps cecure the ‘peraing system from user programming error or imischlet. The overiow stack’ allows recovery from cothorwiea fatal errors WED 3984043 0011796 8 mm T-49-17-07 ‘The CPU has ful 32.0 intomal address and data paths, External, 32 pins tine-multipex the address and data, The Interface is compatible with the complete ne of ‘ZBUS peripherals. The hardware. interface leatures {16-bit oF 32-bit memory data path and programmable Wall states. Burst trnstore and an on-chip cache for Inatructions_and data help develop ‘high-performance systems. “The intertaco™ supports" mul Configurations with interlocked memory references and {wo types of bus request protocols. The system designer an ‘talor the 2320 based syetom’ to ‘cost ‘and Performance needs, 'n summary, the 2320 GPU meets and supasses tho foquirements of medium and high-end mitoprocesser systems forthe 1960s. Softare program development ie easly “accomplished with the CPU's. sophisticated architecture, The highly pipelined design, on-enip each, ‘and external interface suppor systems ranging fom dedicated controtrs to maintrame ‘computors. Whi Zilog continues to develop support for the 2320 CPU, £28000 peripherals and dvelopment software are tly compatible with this latest in Ziog's ine of bigh-portormance microprocessor. REGISTERS ‘The 7320 CPUls a reqistercvented processor cfeing sinteen 32-bit gonerat purpose regstre, @ Sab Progra Courter (PC), & 16-bit Fag and Control Word (FCM) and nna other specia purpose registers, a ‘The general-purpose register fle (igure 1) contains 64 ‘bles of storage. The fist 16 bytes ALO.RHO,.RL7.AH?) an be used a8 accumulators for byte dela, The frat 16 words (RO.Rt,..P¥8) can be used 08 accumulators for ‘word deta as indexrepisters(xcopt 0), or for memory ad {eas0sin compact mode except RO), Ari longuord regi. {er (RRO,RR2,.j. AO) can be used as an accumulator or longwoed data, an index regieter in linear or segmented ‘mode (except RAO), or for mamory addresses in near or Segmented ‘mode (except ARO). Quadword rogitere (R00,R4,...028)can be used a accumuistorstor Mult ‘ly, Divide, and Extend Sign ineructens. This unique regis {er organization allows bytes and words of data to 60 ‘manipuated convenient whl leaving most of tre regi ‘ie teeto hold addresses, courtre, and any cher data, ‘Two egistors are dedicated tothe Stack Pointor(SP) and Framo Pointer (FP) used by Call, Enter, Ext, and Return fand #14 the Frame Pointer. In linear or segmented ‘ode, RA‘ isthe Stack Pointer and RA2 Is the Frame Pointer, (ss seu sor Figure 1. GeneratPurpose Register Fite 6ZILOG INC WE D ‘CACHE “The OPU implements a cache mecharism to keep on-chip ‘copies of tho most recent referenced memory localons (Figure 12). The CPU examines the cache on memory {etches to determine the addressed daa relocatedin the ‘cache. Ite informatonisinthe cache (ahi, thenthe CPU {etches rom the cache, and no vansaction is necessary on ‘he external tarface tho nformation satin the cache ‘miss, thanthe CPU performs a memory read vansacton| {etch ine missing information “The.cache stores dataln blocks of 16 bytes. Each data word in the cache has an associated valcsty bit to indicate ‘whether or notthe words avaidcopy of hecorresponding ‘main memory location. The cache contain 16 blocks, pro- viding 258 bytes of etorage. “The cache is fuly associative, 90 that a block currently needed and missing in the cache can replace ary block in the cache. Moreover, won a block miss occurs, he least [ae ee Figure. 2. Cache Orgentzation mm 9584043 0011797 7 mm 7-49-17-07 ‘ecenty used (LRU) blockin the cache is replaced. When a ‘cache miss eccurs onan instructon fetch, the CPU fetches themissig insruction rom memory and preetchas the a: lowing wordsin he block using aburst transaction, Whena ‘cache miss occurs on an operand fetch, the CPU felch the missing daa tom memory. (The CPU uses burt a actions onl forfetching operands when more than onedala transfer is necessary: longword operands on a 1:bit bus, unaligned operends, sing instuctons, Load Multiple in stucions,andloading Program Situs) On stoce references, the dota is writen to memory (sore througt), and ifthe reference isin the cache, the datas ‘so wtf tothe cache. the store reference miseesin the teach, the cache is unalecte. Software has some conta! over the cache. The cache can be selectively enabled for instruction and data references by bits C and CD inthe SCCL conto register The memory ‘management mechanism aliows cacheing to be inhibited forindvidual pages. The cache instruction can be used to invaite all nformationin the cach. ‘The cache hes an option, controled by bit CR in SCCL, to Inhibit look replacement on a miss. Tis option can be sed to lock ied locations into the cache fr fat, onchip accots. Todo this, tho cacho i st enabiod for Bock re- placomont of data relerences only. Sooctod blocks aro read, io the cache. The block replacement algocthmis hen dis- fabled, while the cache is enabled for instuction and dala relerences. PIN DESCRIPTIONS ‘The CPU has 58 signal ines and adilonal power supply. cconrections. Pin functions are shown in Figure 38, Bc. ADg-AD3:.. Address/Data (Bidirectional, active High, ‘Stato, These 22 lings are time-muliplened to tanslee ad- ‘fess and dala. At the beginning of each transaction the lines are divan withthe 32-b% address. Aer the adcress ‘has beon civen, the lines are used to Wanslar one oF more ‘yfe9, words, or onguords of data FS. Adeass Strobe Output, activ Low, tate The faling ‘edg0 ofS Indicates tho beginning of a trensaction ‘and shows thal the address and ST's, are valid, AW, BLM, BWC, and BRST arevaldon the sing edge of AS, BLY; BWIL. Byte, Longword/Mord: Byte, Word/Long- word (Output, State). These two lines specity the. dala ‘wansler size, Lae se Won Hh er tow Hon Word High low Langword tow Low Fesened BRST. Sut Output, active Low, 3sato). A Low on tis ino indicates thatthe CPU is performing a burst ante, Le, ‘huitiple Data Stobes folowing a single Address Suobe. [BRSTA, Burst Aoknowedge (put, active Low), A Low on this ine incites that the responding device can support burat vansere. [BUBACR. Bus Aoknowiedge Output, active Low) ALow on this ine incioales that the CPU has relinquished contel of {he local bus n response toa bus request. ‘BUSREG. Bus Request (Inout, active Low). A Low on this lneingicatsthatabusrequestorhas obtained ris tyingto blah contol fhe local bus.ZILOG INC 17E D mm 9984043 0011798 1 mm ‘CLK. Clock fnpuy). This iste clock used to generate ll (cPUtiming. BB. Data Strobe (Output, active Low, tate). OSis used for timing deta transfers. EPUABORT. EPU Abort (Output; active High). A High on this ne indeates that the CPU. is aborting ‘exection of an EPA instruction, typically because. an Address Translation trap has occured EPUBBY. EPU Busy (input, acve Low). A Low on this ine Indicates that an EPU is busy This Enis used to synctvo- "ize the operation ofthe CPU with an EPU during execution ‘ofan EPAinsiucton, ‘GRER, Global Acknowledge (input, active Low). A Low on, this in inieats the CPU has been granied conta ofa ‘iobal bus ‘GREG. Goba! Request Output, athe Low, 3stte). A Low Conthisine indicates the CPU has abtaned oistrying to ob- tain controlof a global bus. TE. Input Enable (Quip, active Low 3-tae). A Low on this lino can be used to enabie bates onthe AD ines to ive foward the CPU, RW. Non-Mashable Intrrpt (Inout, Ego activated). A ‘Hihto-Low tanetion on tis tine requests @ nonmaskable inter. RVI. Non-Vectord intept ft, active Low) A Low on this ine requests a non-vectoed interrupt ress | cowrnet| {E. Output Enabie (Output, active Low, 2state). A Low on this ne can be used fo enable buffers on the AD lines to ‘ive away rom the CPU. 7-49-17-07 RESET. Reset (put, actve Low). A Low on this ine resets the CPU, RSPe-RSP}, Response (pu). These lines encode the re- sponse to ransactions inate bythe CPU. Note that RSP, and RSP, can be connected egehe fo Z:BUS WAT timing, ASPo SP) expanse High Hah Reaay ow High Bustier Hoh tow Busey low low Wat RAW, Reacts (Output, Low = Wite, stale). This signal incicates the drecton of data anton. ‘Tp. Status (Cutout, active High, state). These ines speciy the kind of tansacton occuring onthe bus. (See Table) BB. Substrate Bias Generator (Output, for intenal basing only Vi. vectored iterupt (input, active Low). A Low on ising ‘requests a vectored inter. Jeter = za20 cpu sums ee Figure 32, in Functions aZILOG INC 2E Do mM 9964043 0021799 3 mw T-49-17-07 SEFESEPS SPE SE SEES prsesess Pereueeseuea FSS L EL OOP SS Figures.ZILOG INC ABSOLUTE MAXIMUM RATINGS: \Votagos on al inputs and outputs WE D mm 9984043 0011800 & mm T-49-17-07 ‘Stresses greater thanthoselisted under Absolule Maximum Ratings may cause permanent damage tothe device, Tis |g a atrese rating only: operation of the device al any with especttoGND ~0.3Vt0 +7.0V _conaltion above those Inccated in he operational sections ‘Operating Ambient ‘ofthese specications isnot implied. Exposure to abeotte “Temperature +++ 1-868 orfing information maximum ling conditions for ecended poiodemayatfect Storage Tomperatie | =85°Ct0 + 150°C device reliably, ‘STANDARD TEST CONDITIONS ‘The DC charactorisies bolow apply for the following standard test condtions, unless otherwise noted. All vatages are referenced fo GND (0M) Posive cuet flows nothereterencedpn 7 "sia ‘alae operating emperaure ranges ae: MS = 0°C to +70°C, +4,75V < Voc < +5.26V 7 sume 8 tll oad capactance (0. pactance, of 100 pmax +4 DC CHARACTERISTICS Symbol Perm ue Wax Unit Condition Vox Gekingt igh alae 30 Yoo +03 Diventy Bana Cock Gereraor Vox Glokingt tow tage soa 08 V__Diventy xen Cock Generar Vek owt Hgh tage 20 Weot03 Vv Ve ipstLow tape -09 oe v Vor Odpatignvetge 2a Vos 8009 Vo. Output Votage 06 Ves +40mA Me Input Leakage £100 WA 4K Vy 42.4V lee Yoo Spy Curent 700 mA MHz Clock Frequency oC Supply Curent 800 mA_1ONHz Clck Frequency 8ZILOG INC B7E D MM 9984043 0011801 6 mm = T-49-17-07 ‘AC CHARACTERISTICS oe oes ‘Number _ Symbol rameter Min Max Min Max 1 tee Poeck Gvea Time 125 100 «500 2 heh ‘wean gh) 52 0 3 he weet tow) 82 ey Oo 4 Poteck Fall Time ry 10 5% PoteckAige Time 0 10 6 Tee) Picco Bus Fat a a7 7 TeAG) ‘Atos Vd to POlock Setup Time ° 0 8 Tac) Potock to Adore Feat “ 0 8 TaxoR) Aes Valid to Rod Data Reqd Va (ingle mamory ‘ead timing wit one wat witout walt 260) cost sot 0 Te0RO) ead DatatoPOtock Soup Tine 20 wy Te08~ DBttoadiess Active 9st Tot 2 Teciowy Poteet Write Data Vals 65 6 13 TORQ) Feed Dai eld to Poleck Hels Time 5 8 Mw TROADH ead Dal aldo DSt Hold Tine ° ° 18 TeOWOS) Wit DalaValidto DB 1Oslay sot asst 16 TeOWDSW) —__WitData Valid o BS wht) Deay sot sst 7 TeCAS Poteck io Datey ca cy Tes) Stu Visto Poet Setup Tene ° ° 8 TeCASH PCleckt oF # Delay 50 50 2% TaASIOR) Bt Feed Data Roques Valine memory read ‘timing wit one walt: without wats 20) aot s20t 21 Tens) DSt1oAS Doty est 2601 2 WAS BE wiain (omy 110r ast 23 Teas) BB tio cdioss Not Active Delay 88t rot 24 TaagosA) ‘Address FeatioDS (ead) Oelay ° ° 25 TeBa(BUS) ‘ue Feat BUSACK' Delay ° 9 2% TaSIOSR) —_—_—AStto DE (Reag)Dotay 9st rot 27 TaDSAIDA) __DB Read) oReadData Required Val (angle memory "2d timing with one wat whout wate 20) ast zat 2 Teci08) Poicekt oS tDeay * 50 a) Stowe Data tot vata 8st rot 31 Tacos) Potock 1 BS fd) Delay 2 50 @ WOSR ‘BS (Read Wath (Low) sale memory rd ing wih one ‘wat without walt 85) 360t 2st 33 TeOSM) Piock to BB (ie) 4 Detay * 50 34 WOSW ‘BBotay tn Low) 251 185t 35 TabsioA) 1BS{/0)$toRead Data Roques Vs ost ot 28 Taoqos otock to BS (0) Delay 80 50 “Gh innanzacordn So Fetus 1 A races, ‘Ores tne cepencent characte.ZILOG INC U7E Do mm 9984043 0022802 T mm : T-49-17-07 ‘AC CHARACTERISTICS* (Coninuec) ns tome Number Symbol Parameter Min Mx Min Max 7 wos! BEqo}wian tow) 5t 1881 98 TEASOSA) “FB TioDB (Acknowedvo) Doty est rt 3 Tec(osa) otek 8 chro Ooty 0 0 40 TeOSADR) DB (Actnovledge) to Read DataRequedVald170t aot ne) POtck to Status Vaid Delay o «0 a TEAS) ‘See Veo Demy ar sor 43 TAG) FRESE io Piece Setup Tina 2 20 nc) FFEBET oPock Hold Time 2 2s 4s Twin RT Wh ow 6st sot «wm awn gh Bot 1901 7 TaN) ‘Wil vio PCat Seu Tine ~ «o 3 WG VLR ioPoickt Seu Tine 0 “ “TMG LRM oP Cock Hol Tine 20 2 0 “et URW tom 36st ea0t 51 THBREOIO) —_BUSFET change oPCiockt Setup Tine “0 0 2 WwaREO BUSES wan ow) 36st ‘sot 58 TREREOC) ——-BUSFETtoPvakt Hold Tine 20 20 54 THCIMOK) Peck BUSACK t Day 6 rs 85: TUCKBACK) —_—_—POoek to BUSACK Delay & “6 7 Tact) Pvc oIE Tey es es 5 TecteD Poiock oT Deley 6 6 59 TABRETAC) ——_BRRTA1oPOeckt Setup Tine 25 5 © TeEPUBSY) —_EFUBBYi0PCck Setup Time » 2 81 TRARSTAC) BSH lo PoecktHoldTime 8 5 ©2 __THEPUBSYC) —_EPUBSY 1oPClook* HoldTine 8 a 2 TeRSAC) SP Ghago 9 POaektSatup Tne » 20 4 TARO) SPt0POeckt Hts Tine 5 5 65 TaEI0=) ‘DEChange to Change Delay 205t 270t 68 WaACK BAER wit ow) 36st 220 61 TeGACKC) BEER Chango toFCockt Seip tine “ “ 68 TWOACKC) —_—_TATR a PClckt Hold Tine 0 20 @@ Te0j0en PO}ek io GEVOeay % ~ 7 TeC{OEH Folock to tOoay Py 0 1 TIBAST) POLE OBFST Dey 6 es 72 TECIBASH) -—_POLck to BASTYDetsy 65 6 78 THOIGREG ——_—FOLck to SFEGS Delay 0 2 %4 _T6OIGREO) Fock o URED Delay 2 # “nnsnsanosaconga Sa Fosaie 6 AC arta ‘Oe yletiecepandontcnrcrce,ZILOG INC UE D FOOTNOTES TO AC CHARACTERISTICS Wa al En 3 Taam eno Woe ono» —n % o9 sno Tay +009 oe $2 Yewes 1~wbW eoDeW oe aoa d= Te) — TNE Boma See - Taibo Toe ee awe focue 3 tye rainy +ng ~ ee Basen te -Tave) shaban “ae 2 Tanon st — eae — TRE Beno Nota * ant a & om” Tat % Moon _ iat anon = rest) TORE TS 3 not feo ctee 2 Taso) Tonto) + e009 - ‘2 Towon Hace one ‘2 tava)” ota) tao one wan feces @ nemo ia oe & Taecs eet «een @ ack Tee reo eae 9984043 0011803 1 mm T-49-17-07ME 9584043 0011804 3 mm T-49-17-07 “Timing measurements aremade at thetoloning volages. High av 20v 20v avZILOG INC 17E Dom 9984043 0012321 7 mm PACKAGE INFORMATION T-40-20 a tee Ht [| T at 18 in Coram Package Cg sew lam = eae (it BET get gael Oba 10Pin Plastic PackageZILOG INC VE Dom 99a4043 COL2312 9 mm T4020 PACKAGE INFORMATION (Continued) fis 7 ne anak Sal y TIIITT TTY \ ——_ | am | a =e ve fi | Th wt eh rey as a 40-PinDustin-Line Package (OP), Peto. NOTE: Pastag reno eines. T comer milnars, nti by 25.4 62ZILOG INC 27E D mm 9984043 0022313 0 mm T=40-2O PACKAGE INFORMATION (Continued) 40.PinDualin-Line Package (IP), Ceramic 44Pin Paste Chip Cacer POC) 563: ZILOG INC U7E D M@ 9984043 0022314 2 mm Hees! 02216) PACKAGE INFORMATION (Continued) 48-Pin Dusbin-Line Package (OIF), PlatoZILOG INC U7E DMM 9984043 0012315 4 mm —— T= 90-20 PACKAGE INFORMATION (Continued) gosh ttt? 68-Pin Plastic Chip Carrier (PCC) we aH feectes a fo ° 8 8 8 3 8 8 8 3 o>, 24-Pin Gea Arey (POA), ‘View toward PC Board 5 Bottom View |NoTE-Pectape dimension se gienninnes.Toconven omnes, yy 264 565