Ouwe UMC UM6264 Series 8Kx 8 CMOS SRAM Features ‘© Single +5 volt power supply © Access times: 70/100/120 ns fax.) © Current Standard version Operating: 90 mA imax.) Standby: 2 mA (erax.) Low power version: Operating: 90 mA [max.) Standby: 100uA (max.) = Fully static operation, no clock or refreshing required General Description The UM6264 Is a high-speed, low-power 65,596-bit static. random access memory organized as 8,192 words by @ bits and operates on a single Syolt power supply, It is built using UMC’s high performance CMOS process Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Directly TTL compatible: Ali inputs and outputs Common 1/0 using three state ourput Outout enable and two chip select inputs for easy application Data retention voltage: 2V (min. for low power version Available in 28 pin DIP, SOP, or Skinny DIP packages {See ordering information) Two chip select inputs are provided for power dawn and device select, and an output enable input is included for easy interface Data retention is quaranteed at a poner supply voltage slow a5 2V for the low power version Pin Configuration Block Diagram . : —Vee me Row |” 256 x 256 ——cnD 7 e [DECODER] » MEMORY ARRAY : | | cmeurr Woe 14 1__] ee os ae cs & CONTROL ot curt 2-36Oume UM6264 Series Description Recommended DC Operating Conditions (Ta = 0°C 10 70°C) Designation Description Fe ~ Ave Tadress Tout Symbol] Paramewr | Wins | Te. | Max onal ve Write Enable Vee | Supply Vonage | 45 [50 [ 55 | V OE Output Enable GND_| Ground o,ofo ty Gi Chip Select Von) eons a 2 as We | v Ss Chip Select Voltage ov NC. No Connection va | inet “ea! o bwoalv Or ~ WOs Data Input/Output Voltage Veo Power Supply EV) C_| Output Load = [100 | oF NO Ground Trt [Sumitted | -[-)1]- Absolute Maximum Ratings * *Comments: Veg t© GND IN, IN/OUT Volt to GND Operating Temperature, T, opr Storage Temperature, Tsty ‘emperature Under Bias, Tyios Power Dissipation, P Soldering temp. & time DC Electrical Characteristics ~08V 10 +7.0V -0.8V t0 Veg +0.5V ofc 10 470°C 58°C to 125°C 10°C t0 485°C 1.0W/SOP 0.7 260°C, 10 see Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device ‘These are stress ratings only, Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification js not implied and exposure to absolute maximum rating conditions for extended periods may affect device cc: Niability (Tp = 0°C 10 #70°C, Veg = BY # 10%, GND = OV) ‘UMEzea7O7 | UMEREATOLT Parameter tort Tora Unit Test Conditions Mine Max. | Mins Wax eo — 2 |- 2 wr | iy = GND tO Vee ale : Tis Vin OFS Vin igot | Quset stan - 2 |- 2 wr | or OE = Vy of WE= Vy, : Vio * GND t0 Voc ve | Aste Power ~~ Te go} ma | OY C= Yin Supaly Curent to = OMA Min, Cycle, Duty = 100% tees | Dynamic Oreretig | go |= 90° | mA | Ep = Vy. CS2= Vin : yo = 0mA Te ane ce 3 mA [C81 = Vin OFS = Vi | > Voc ON. C8: > Vog 02 A 2 - 01 mA 2 cc 801 | standby Power | Vin > Veo -0.2V or Supply Current Vn < 0a S, S02V, CS, <02V | 'se2 - 2 - on mA | Vay ® Veg —0.2V oF Vin < 02 vipat Low - - Vou] Sue - oa | - o4 | ov Jig 4ma Output High ~ 2 ~ - Vou ete 2a - 24 eS v lon = 1.0 maOume UM6264 Series Truth Table Mode es, WE nt [#4 x Standby x x Output Disabled v 4 ead L 4 Waite L = Note X°H or L. Capacitance (T., = 25°C.1= 10MHe) ‘Symbol Test Conditions Cit Gyo" Tnpuy/Output Capacitance —! “This parameter is sampled and not 100% tested AC Characteristics (Vog = 5V + 10%, T, UM626442/12L_| Unit 1s 1s ai Guaneun ‘Ums264707700 | ume2ee-10/100 Max ead Oye Toad yao Tino 7 "ekrss Roaass Te 70 Chip Sect Access 70 Time 70 anpat Eraa to Oatbut Vand B Chip Selection v0 = Output in Low Z Ez Output Erabieto Our = Chip Desstection B Output in High 2 = ‘Output Diablo to Output in Hh Z 3% aout Hold from Address Crane = Write Gye Tee [Wei Orde Tare ‘ew [Chip Section to Ea oT Wie e tas [ Adare: Seta Tine = Taw | Adress Vaid to End oT Wo = tye Wie Pus With S Twn | Write Recovery Tine [Fane | Write © Outout in High 2 % tow | Data to Write Time Overlap 5 ‘on [Dra Fold rom We Tine ‘uz | Output Disable to Output in HART x [Sb osaat Rohe tam enor Notes: teuz. tong and tyiiz are defined as the time at which the outputs achieve the open circuit condition and are not re ferred to output w®ume UM6264 Series ing Waveforms (Continued) Read Cycle 1!".24) Pour, Read Cycle 2(7.2.4.6) as cuz Sour Read Cycle 3!1-4.7.8) cs Pour Read Cycle 4°! Address Notes: 1, WWE ishigh for READ cycle, _ 2. Deviee i continuously selected TS; = Vy_ and CSy = Viy 3. Address valid prior to or coincident with & transition tow. 4, 08= Vi. 8. Transition is measured # 500mV from steady state, This earameter is sampled and not 100% ested 6. CSy ishich 7. GS is low. 8. Addres valid prior to or coincident with CS transition highOume UM6264 Series Timing Waveforms (Continued) Write Cycle 1 —— *« ———4 Aare fron fsa o} Write Cycle 2'6) ‘on we a a Notes: 3. tag is measured from the address valid to the beginning of write. 2, Avvrite occurs during the overlap (typ) of @ low CS; ,a high CS, and a low WE 3, twa, is measured from the earliest of C5, or WE going high or CS going iow to the end of write cycle 4, uring this prio ‘ot be applied, 5. If tha CS, tow transition oF the CS high transition occur simultaneously with thei low transition or after the WE transition, outputs remain ina high impedance state 1/0 pinsare in the output state s0 that the input signals of opposite phase to the outputs must 6. OF is continuously low (OE # V;,) 7. Dou isthe same phase of write data ofthis write cycle 8. Dour isthe read data of next address 9. HES is low and CS, is high during this period, 1/0 pins are in the output state. Tho data input signals of opposite phase to the outputs must nat be applied to 1/0 pins 10, Transition is messured ¢ 5O0m\ from steady state, This parameter is sampled and not 100% tested 11. toy i measured from the later of CS, going low or CS going high to the end of write, 2-40Oume UM6264 Series AC Test Conditions For Access Time: 7Ons For Access Times: 100/120 ns Inout ise ond Fa Tine rs Sere Inputend Ouput Input a Outout Timing Reterence Levels uv Timing Reference Levels iv cet Sef 28 [Loses tons [sera __| S10m2 8602 1 ee I “Including scope and jig *Inciuding scope and jig *v 10009 wot ae i “Including scope and jg. Figure 1. Output Load Data Retention Characteristics Figure 2. Output Load (T= 0°C to +70°C; L version only) Figure 3. Output Load for teuz. Torz: tow: tonz: wz and tow Symbor Parmer Twin. [Max [Une est Conditions @, > Veg ~00V. Vor, | 20 } 55 v Voc for Data | (8; > Veg -0.2V or CS, < 0.2 Vor2 | Retention [a0 | ss |v | cs Veg -02V leepy - | wo | wa | cs > vee-02v Qataeenton Vin > Veo -02V or Vyy < 0.2 tent Veo =30V, 65; <02V, GS, <02 a ~ lw | jog = 30V, Cy SOW, CS, SOD 2 Vin > Veo =02V or Vig € 0.2 Chip Deselect to a ‘con Data Retention Time 2 - ns : = —| see Retention Wavetorm operator Reo we | ns “tag ~ Read Cycle Time 2-41Oume UM6264 Series Low Ve¢ Data Retention Waveform (1) (CS, Controlled) Data Retention Mode Gi > von—0av Low Ve Data Retention Waveform (2) (CS; Controlled) ata Retention Mode cS; <02v Characteristic Curves “ 115) Tapse Voc 450 13 1.0 ‘Sunol Carn ‘Norra 19 ry — Sispr Voluge Vee Ambien Tempest °C) 2-42Oume UM6264 Series Characteristic Curves (Continued) 115, 60 5 Tare ve | aio 10 = oes oo So am ton as ee = 7% soo Vo Ye Anwen Tegan) taste T vec qv 3 00 7 Fain #2 oss F210 086 | 1 oso an 00 as oe ee Ordering Information Pun Tecan Tene] Operating Curent] Standby Curent . ut No. Ans) ‘Max. (mA) | Max. (mA) 626470 00 2 ZBL bi | —owezer700——] 0 oi 28 OIF Me2oan.70 0 90 2 28.0 | —aveatain7o0 | 90 om ZBLSOP | —~owexeaic70 | 30 2 ZBL Skin | uMexbaR-70L 30 ot [280 Skinny OREZEE TO 30 | 2 7a OF TMEZSETOL 30 ci ZBL OF OME2OaN-TO woo 3 z aL SOP UM6264M-10L 90 on 28L SOP, OWER6aK-10 30 2 ZBL Skinny Owe26aK TOL 3 a 2BL Skinny UM6264-12 90 2 28L DIP. yon 120 30 ot [et oF OWEZBANTTD tw 30 Z BL SOP ‘UM6264M-12L ~ 90 Ot ‘28L SOP ise 3 z EL Skin TREAT a ar 7a semmr] 2-43