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TPA3110D2-Q1
SLOS794B – SEPTEMBER 2012 – REVISED SEPTEMBER 2015
Navigation) PLIMIT
OUTNR FILTER 8W
PBTL
• ADAS Noise Generation for Blind Spot Detection,
Security and Alarm Systems Fault
SD PVCC 8 to 26V
• Professional Audio Equipment (Performance
Amplifiers, Premium Microphones)
• Aerospace and Aviation Audio Systems
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3110D2-Q1
SLOS794B – SEPTEMBER 2012 – REVISED SEPTEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 14
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 15
3 Description ............................................................. 1 8 Application and Implementation ........................ 18
4 Revision History..................................................... 2 8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 18
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 25
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 26
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 26
6.3 Recommended Operating Conditions...................... 4 10.2 Layout Example .................................................... 27
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 28
6.5 DC Characteristics .................................................... 5 11.1 Device Support .................................................... 28
6.6 DC Characteristics .................................................... 5 11.2 Documentation Support ....................................... 28
6.7 AC Characteristics .................................................... 6 11.3 Community Resources.......................................... 28
6.8 AC Characteristics .................................................... 6 11.4 Trademarks ........................................................... 28
6.9 Typical Characteristics ............................................. 7 11.5 Electrostatic Discharge Caution ............................ 28
7 Detailed Description ............................................ 13 11.6 Glossary ................................................................ 28
7.1 Overview ................................................................. 13 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 14 Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ............................... 1
PWP Package
28-Pin HTSSOP With PowerPAD™ IC Package
Top View
SD 1 28 PVCCL
FAULT 2 27 PVCCL
LINP 3 26 BSPL
LINN 4 25 OUTPL
GAIN0 5 24 PGND
GAIN1 6 23 OUTNL
AVCC 7 22 BSNL
AGND 8 21 BSNR
GVDD 9 20 OUTNR
PLIMIT 10 19 PGND
RINN 11 18 OUTPR
RINP 12 17 BSPR
NC 13 16 PVCCR
PBTL 14 15 PVCCR
Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled), TTL
1 SD I
logic levels with compliance to AVCC.
Open drain output used to display short circuit or DC detect fault status. Voltage compliant to
2 FAULT O AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin.
Otherwise, both short circuit faults and DC detect faults must be reset by cycling PVCC.
3 LINP I Positive audio input for left channel, biased at 3 V.
4 LINN I Negative audio input for left channel, biased at 3 V.
5 GAIN0 I Gain select least significant bit, TTL logic levels with compliance to AVCC.
6 GAIN1 I Gain select most significant bit, TTL logic levels with compliance to AVCC.
7 AVCC P Analog supply
8 AGND — Analog signal ground, connect to the thermal pad.
High-side FET gate drive supply. The nominal voltage is 7 V. GVDD should also be used as
9 GVDD O
a supply for the PLIMIT function.
Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit.
10 PLIMIT I
Connect directly to GVDD for no power limit.
11 RINN I Negative audio input for right channel, biased at 3 V.
12 RINP I Positive audio input for right channel, biased at 3 V.
13 NC — Not connected
14 PBTL I Parallel BTL mode switch
Power supply for right channel H-bridge. Right channel and left channel power supply inputs
15 PVCCR P
are connect internally.
Power supply for right channel H-bridge. Right channel and left channel power supply inputs
16 PVCCR P
are connect internally.
17 BSPR I Bootstrap I/O for right channel, positive high-side FET
18 OUTPR O Class-D H-bridge positive output for right channel
19 PGND — Power ground for the H-bridges
20 OUTNR O Class-D H-bridge negative output for right channel
21 BSNR I Bootstrap I/O for right channel, negative high-side FET
22 BSNL I Bootstrap I/O for left channel, negative high-side FET
23 OUTNL O Class-D H-bridge negative output for left channel
24 PGND — Power ground for the H-bridges
25 OUTPL O Class-D H-bridge positive output for left channel
26 BSPL I Bootstrap I/O for left channel, positive high-side FET
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage AVCC, PVCC –0.3 30 V
–0.3 VCC + 0.3 V
SD, GAIN0, GAIN1, PBTL, FAULT (2)
Interface pin < 10 V/ms
VI
voltage PLIMIT –0.3 GVDD + 0.3 V
RINN, RINP, LINN, LINP –0.3 6.3 V
BTL: PVCC > 15 V 4.8
Minimum load
RL BTL: PVCC ≤ 15 V 3.2
resistance
PBTL 3.2
Continuous total power dissipation See the Thermal Information Table
TA Operating free-air temperature –40 125 °C
TJ Operating junction temperature (3) –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series
with the pins, per application note SLUA626.
(3) The TPA3110D2-Q1 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Brief SLMA002 for more information about using the TSSOP thermal pad.
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
6.5 DC Characteristics
TA = –40°C to 125°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 24 V 32 50 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 24 V 250 400 µA
VCC = 12 V, IO = 500 mA, High side 240
rDS(on) Drain-source on-state resistance mΩ
TJ = 25°C Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
ton Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 μs
GVDD Gate drive supply IGVDD = 100 μA 6.4 6.9 7.4 V
tDCDET DC detect time V(RINN) = 6 V, VRINP = 0 V 420 ms
6.6 DC Characteristics
TA = –40°C to 125°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV
differentially)
ICC Quiescent supply current SD = 2 V, no load, PVCC = 12 V 20 35 mA
ICC(SD) Quiescent supply current in shutdown mode SD = 0.8 V, no load, PVCC = 12 V 200 µA
VCC = 12 V, IO = 500 mA, High side 240
rDS(on) Drain-source on-state resistance mΩ
TJ = 25°C Low side 240
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
tON Turn-on time SD = 2 V 14 ms
tOFF Turn-off time SD = 0.8 V 2 μs
GVDD Gate drive supply IGVDD = 2 mA 6.4 6.9 7.4 V
Output voltage maximum under PLIMIT
VO V(PLIMIT) = 2 V; VI = 1 VRMS 6.75 7.90 8.75 V
control
6.7 AC Characteristics
TA = –40°C to 125°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mVPP ripple at 1 kHz,
KSVR Power supply ripple rejection –70 dB
Gain = 20 dB, inputs AC-coupled to AGND
PO Continuous output power THD+N = 10%, f = 1 kHz, VCC = 16 V 15 W
THD+N Total harmonic distortion + noise VCC = 16 V, f = 1 kHz, PO = 7.5 W (half-power) 0.1%
65 µV
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk VO = 1 VRMS, Gain = 20 dB, f = 1 kHz –100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C
6.8 AC Characteristics
TA = –40°C to 125°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
200 mVPP ripple from 20 Hz–1 kHz,
KSVR Supply ripple rejection –70 dB
Gain = 20 dB, inputs AC-coupled to AGND
PO Continuous output power THD+N = 10%, f = 1 kHz; VCC = 13 V 10 W
THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power) 0.06%
65 µV
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz –100 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
fOSC Oscillator frequency 250 310 350 kHz
Thermal trip point 150 °C
Thermal hysteresis 15 °C
10 10
Gain = 20 dB Gain = 20 dB
VCC = 12 V VCC = 18 V
ZL = 8 Ω + 66 µH ZL = 8Ω+ 66 µH
1 1
0.1 0.1
PO = 5 W PO = 10 W
PO = 1 W
0.01 PO = 0.5 W 0.01
PO = 2.5 W PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G001 G002
Figure 1. Total Harmonic Distortion vs Frequency (BTL) Figure 2. Total Harmonic Distortion vs Frequency (BTL)
10 10
Gain = 20 dB Gain = 20 dB
VCC = 24 V VCC = 12 V
ZL = 8 Ω + 66 µH ZL = 6 Ω + 47 µH
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
1 1
0.1 PO = 10 W 0.1
PO = 5 W
PO = 1 W
PO = 0.5 W
0.01 0.01
PO = 2.5 W
PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G003 G004
Figure 3. Total Harmonic Distortion vs Frequency (BTL) Figure 4. Total Harmonic Distortion vs Frequency (BTL)
10 10
Gain = 20 dB Gain = 20 dB
VCC = 18 V VCC = 12 V
ZL = 6 Ω + 47 µH ZL = 4 Ω + 33 µH
THD − Total Harmonic Distortion − %
1 1
PO = 10 W
0.1 0.1 PO = 10 W
PO = 1 W
0.01 0.01
PO = 1 W
PO = 5 W
PO = 5 W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G005 G006
Figure 5. Total Harmonic Distortion vs Frequency (BTL) Figure 6. Total Harmonic Distortion vs Frequency (BTL)
f = 20 Hz f = 1 kHz f = 20 Hz
0.1 f = 1 kHz
0.1
0.01
0.01
f = 10 kHz
0.001 f = 10 kHz
0.01 0.1 1 10 50 0.001
PO − Output Power − W 0.01 0.1 1 10 50
G007
PO − Output Power − W
Lighter color represents thermally limited region. G008
Figure 7. Total Harmonic Distortion + Noise vs Output Figure 8. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
10 10
Gain = 20 dB Gain = 20 dB
THD+N − Total Harmonic Distortion + Noise − %
f = 1 kHz
f = 1 kHz
f = 20 Hz
0.1 0.1
0.01 0.01
f = 20 Hz
f = 10 kHz f = 10 kHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 50
PO − Output Power − W PO − Output Power − W
G009 G010
Figure 9. Total Harmonic Distortion + Noise vs Output Figure 10. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
10 10
Gain = 20 dB Gain = 20 dB
THD+N − Total Harmonic Distortion + Noise − %
VCC = 18 V VCC = 12 V
ZL = 6 Ω + 47 µH ZL = 4 Ω + 33 µH
1 1
f = 1 kHz f = 1 kHz
f = 20 Hz
0.1 0.1
0.01 0.01
f = 20 Hz
f = 10 kHz
f = 10 kHz
0.001 0.001
0.01 0.1 1 10 50 0.01 0.1 1 10 50
PO − Output Power − W PO − Output Power − W
G011 G012
Figure 11. Total Harmonic Distortion + Noise vs Output Figure 12. Total Harmonic Distortion + Noise vs Output
Power (BTL) Power (BTL)
ZL = 8 Ω + 66 µH ZL = 4 Ω + 33 µH
12 25
PO − Output Power − W
10
20
8
15
6
10
4
5
2
0
0 0 1 2 3 4 5 6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 VPLIMIT − PLIMIT Voltage − V
G014
VPLIMIT − PLIMIT Voltage − V
G013 Note: Dashed lines represent thermally limited regions.
Figure 13. Maximum Output Power vs PLIMIT Voltage (BTL) Figure 14. Output Power vs PLIMIT Voltage (BTL)
40 100 30
Gain = 20 dB
ZL = 8 Ω + 66 µH
35 50 25
Phase
30 0
PO − Output Power − W
20
25 −50
THD = 10%
Gain − dB
Phase − °
Gain 15
20 −100
THD = 1%
15 −150 10
CI = 1 µF
Gain = 20 dB
10 −200
Filter = Audio Precision AUX-0025 5
VCC = 12 V
5 VI = 0.1 Vrms −250
ZL = 8 Ω + 66 µH 0
0 6 8 10 12 14 16 18 20 22 24 26
−300
20 100 1k 10k 100k VCC − Supply Voltage − V
G016
f − Frequency − Hz
G015 Note: Dashed lines represent thermally limited regions.
Figure 15. Gain/Phase vs Frequency (BTL) Figure 16. Output Power vs Supply Voltage (BTL)
25 100
Gain = 20 dB
90 VCC = 12 V VCC = 18 V
ZL = 4 Ω + 33 µH
VCC = 24 V
20 80
PO − Output Power − W
70
THD = 10%
h − Efficiency − %
15 60
50
THD = 1%
10 40
30
5 20
10 Gain = 20 dB
ZL = 8 Ω + 66 µH
0 0
6 8 10 12 14 16 18 0 5 10 15 20 25 30 35 40
VCC − Supply Voltage − V PO − Output Power − W
G017 G018
Note: Dashed lines represent thermally limited regions. Note: Dashed lines represent thermally limited regions.
Figure 17. Output Power vs Supply Voltage (BTL) Figure 18. Efficiency vs Output Power (BTL)
h − Efficiency − %
h − Efficiency − %
60
60
50
50
40
40
30
30
20
20
Gain = 20 dB 10 Gain = 20 dB
10 LC Filter = 22 µH + 0.68 µF ZL = 6 Ω + 47 µH
RL = 8 Ω 0
0 0 5 10 15 20 25
0 5 10 15 20 25 PO − Output Power − W
G019
PO − Output Power − W
G032 Note: Dashed lines represent thermally limited regions.
Figure 19. Efficiency vs Output Power (BTL With LC Filter) Figure 20. Efficiency vs Output Power (BTL)
100 100
90 VCC = 12 V 90
VCC = 12 V
80 80
VCC = 18 V
70 70
h − Efficiency − %
h − Efficiency − %
60 60
50 50
40 40
30 30
20 20
Gain = 20 dB
10 LC Filter = 22 µH + 0.68 µF 10 Gain = 20 dB
RL = 6 Ω ZL = 4 Ω + 33 µH
0 0
0 5 10 15 20 25 0 3 6 9 12 15 18
PO − Output Power − W PO − Output Power − W
G033 G020
Figure 21. Efficiency vs Output Power (BTL With LC Filter) Figure 22. Efficiency vs Output Power (BTL)
100 2.6
2.4
90
2.2 VCC = 18 V
VCC = 12 V
80 2.0
ICC − Supply Current − A
70 1.8
h − Efficiency − %
1.6
60 VCC = 12 V
1.4
50 1.2 VCC = 24 V
40 1.0
0.8
30
0.6
20 0.4
Gain = 20 dB Gain = 20 dB
LC Filter = 22 µH + 0.68 µF 0.2 ZL = 8 Ω + 66 µH
10
RL = 4 Ω 0.0
0 0 5 10 15 20 25 30 35 40
0 5 10 15 20 25 PO(Tot) − Total Output Power − W
G021
PO − Output Power − W
G034 Note: Dashed lines represent thermally limited regions.
Figure 23. Efficiency vs Output Power (BTL With LC Filter) Figure 24. Supply Current vs Total Output Power (BTL)
2.0 −60
Crosstalk − dB
VCC = 12 V
1.6 −70
−80
1.2 Right to Left
−90
0.8 −100
−120
0.0
0 5 10 15 20 25 30 −130
PO(Tot) − Total Output Power − W 20 100 1k 10k 20k
G022
f − Frequency − Hz
Note: Dashed lines represent thermally limited regions. G023
Figure 25. Supply Current vs Total Output Power (BTL) Figure 26. Crosstalk vs Frequency (BTL)
0 10
Gain = 20 dB Gain = 20 dB
Vripple = 200 mVpp VCC = 24 V
KSVR − Supply Ripple Rejection Ratio − dB
−20 ZL = 8 Ω + 66 µH ZL = 4 Ω + 33 µH
THD − Total Harmonic Distortion − %
1
−40 PO = 5 W
PO = 0.5 W
−80
0.01
−100 PO = 2.5 W
−120 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G024 G025
Figure 27. Supply Ripple Rejection Ratio vs Frequency Figure 28. Total Harmonic Distortion vs Frequency (PBTL)
(BTL)
10 40 100
Gain = 20 dB
THD+N − Total Harmonic Distortion + Noise − %
VCC = 24 V 35 50
ZL = 4 Ω + 33 µH
Phase
1 30 0
f = 1 kHz
25 −50
Gain − dB
Phase − °
Gain
0.1 20 −100
15 −150
CI = 1 µF
0.01 10 Gain = 20 dB
−200
Filter = Audio Precision AUX-0025
f = 20 Hz VCC = 24 V
5 VI = 0.1 Vrms −250
f = 10 kHz ZL = 8 Ω + 66 µH
0.001 0 −300
0.01 0.1 1 10 50 20 100 1k 10k 100k
PO − Output Power − W f − Frequency − Hz
G026 G027
Figure 29. Total Harmonic Distortion + Noise vs Output Figure 30. Gain/Phase vs Frequency (PBTL)
Power (PBTL)
80
30 VCC = 18 V
PO − Output Power − W
70
VCC = 12 V
25
h − Efficiency − %
THD = 10% 60
20
50
THD = 1%
15 40
10 30
20
5
10 Gain = 20 dB
0 ZL = 4 Ω + 33 µH
6 8 10 12 14 16 18 20 0
VCC − Supply Voltage − V 0 5 10 15 20 25 30 35 40 45
G028
PO − Output Power − W
Note: Dashed lines represent thermally limited regions. G029
Figure 31. Output Power vs Supply Voltage (PBTL) Figure 32. Efficiency vs Output Power (PBTL)
2.8 0
2.6 Gain = 20 dB Gain = 20 dB
ZL = 4 Ω + 33 µH Vripple = 200 mVpp
−40
1.8
1.6 VCC = 12 V
1.4 −60 VCC = 12 V
1.2 VCC = 18 V
1.0
−80
0.8
0.6
−100
0.4
0.2
0.0 −120
0 5 10 15 20 25 30 35 40 45 20 100 1k 10k 20k
PO − Output Power − W f − Frequency − Hz
G030 G031
Figure 33. Supply Current vs Output Power (PBTL) Figure 34. Supply Ripple Rejection Ratio vs Frequency
(PBTL)
7 Detailed Description
7.1 Overview
The TPA3110D2-Q1 is AEC-Q100 qualified with a temperature grade 1 (-40°C to 125°C), HBM ESD
classification level H2, and CDM ESD classification level C2. This automotive audio amplifier also features
several protection mechanisms as follows:
• DC Current Detection
– The TPA3110D2-Q1 protects speakers from DC current by reporting a fault on the FAULT pin and turning
the amplifier outputs to a Hi-Z state when a DC current is detected. The PVCC supply must be cycled to
clear this fault.
• Short-Circuit Protection and Automatic Recovery
– The TPA3110D2-Q1 has short circuit protection from the output pins to VCC, GND, or to each other. If a
short circuit is detected, it will be reported on the FAULT pin and the amplifier outputs will be switched to a
Hi-Z state. The fault can be cleared by cycling the SD pin.
• Thermal Protection
– When the die temperature exceeds 150°C (±15°C) the device enters the shutdown state and the amplifier
outputs are disabled. The TPA3110D2-Q1 recovers automatically when the temperature decreases by
15°C
GVDD
PVCCL
BSPL
PVCCL
OUTPL FB
LINP PGND
PWM
Gain
PLIMIT Logic
Control GVDD
LINN PVCCL
BSNL
PVCCL
OUTNL FB
OUTNL FB
FAULT
Gate
Drive OUTNL
SD
TTL
Buffer
GAIN0 SC Detect
Gain PGND
GAIN1 Control
DC Detect
Ramp Biases and Startup Protection
Generator References Logic Thermal
Detect
PLIMIT
PLIMIT Reference UVLO/OVLO
GVDD
PVCCL
BSNR
AVDD
PVCCL
AVCC LDO
Regulator
GVDD
Gate
Drive OUTNR
GVDD
OUTNN FB OUTNR FB
RINN
PGND
Gain PWM
PLIMIT Logic
Control
GVDD PVCCL
RINP
BSPR
PVCCL
OUTNP FB
Gate
Drive OUTPR
TTL PBTL PBTL Select
PBTL Buffer Select OUTPR FB
AGND
PGND
7.4.3 SD Operation
The SD pin can be used to enter the shutdown mode which mutes the amplifier and causes the TPA3110D2-Q1
to enter a low-current state. This mode can also be triggered to improve power-off pop performance.
7.4.4 PLIMIT
The PLIMIT pin limits the output peak-to-peak voltage based on the voltage supplied to the PLIMIT pin. The peak
output voltage is limited to four times the voltage at the PLIMIT pin.
Vinput
TPA3110D2-Q1
Power Limit Function
Vin=1.13VPP Freq=1kHz RLoad=8W
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply
connected to PVCC. This virtual rail is four times the voltage at the PLIMIT pin. This output voltage can be used
to calculate the maximum output power for a given maximum input voltage and speaker impedance.
2
ææ RL ö ö
çç ç ÷ x VP ÷÷
è RL + 2 x RS ø
POUT = è ø for unclipped power
2 x RL (1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT (10%THD) = 1.25 × POUT (unclipped)
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
100 kΩ
Control 1 28
SD PVCCL
System 1 kΩ
2 27
FAULT PVCCL
1 mF 3 26 0.22 μF
LINP BSPL FB
1 mF 4 25
LINN OUTPL 1000 pF
5 24
GAIN0 PGND
6 23
PVCC 10 Ω
GAIN1 OUTNL 1000 pF
7 22
AVCC BSNL FB
1 mF 0.22 μF
TPA3110D2-Q1
8 21 0.22 μF
AGND BSNR FB
1 mF 9 20 1000 pF
GVDD OUTNR
1 mF
10 kΩ 10 19
PLIMIT PGND
10 kΩ
1 mF 11 18
RINN OUTPR 1000 pF
Audio 12 17 FB
RINP BSPR
Source 1 mF
0.22 μF
13 16
NC PVCCR
100 μF 0.1 μF 1000 pF
14 15
PBTL PVCCR
GND
29
PowerPAD
PVCC
Figure 36. Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting
PVCC
100 kΩ
Control 1 28
SD PVCCL
System 1 kΩ
2 27
FAULT PVCCL
3 26
LINP BSPL
0.47 μF
4 25
LINN OUTPL
5 24
GAIN0 PGND
6 23 FB
AVCC GAIN1 OUTNL
7 22 1000 pF
PVCC AVCC BSNL
10 Ω
TPA3110D2-Q1
1 mF 8 21
AGND BSNR
1000 pF
1 mF
9 20
GVDD OUTNR
FB
10 19
PLIMIT PGND
0.47 μF
1 mF 11 18
RINN OUTPR
Audio 12
BSPR
17
RINP
Source 1 mF
13 16
NC PVCCR
(1) 100 μF 0.1 μF 1000 pF
100 kW 14 15
AVCC PBTL
GND
PVCCR
29
PowerPAD
PVCC
(1) A 100-kΩ resistor is needed if the PVCC slew rate is more than 10 V/ms.
Figure 37. Stereo Class-D Amplifier With PBTL Output and Single-Ended Input
70
FCC Class B
60
50
Limit Level - dBmV/m
40
30
20
10
0
30M 230M 430M 630M 830M
f - Frequency - Hz
8.2.2.3 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional Class-D amplifier needs an output filter is because the switching waveform
results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple
current is large for the traditional modulation scheme because the ripple current is proportional to voltage
multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is
half the period for the traditional modulation scheme. An ideal LC Filter is needed to store the ripple current from
each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both
resistive and reactive, whereas an LC Filter is almost purely reactive.
The TPA3110D2-Q1 modulation scheme has little loss in the load without a filter because the pulses are short
and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making
the ripple current larger. Ripple current could be filtered with an LC Filter for increased efficiency, but for most
applications the filter is not needed.
An LC Filter with a cutoff frequency less than the Class-D switching frequency allows the switching current to
flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 39. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1 C2
2.2 mF
15 mH
OUTN
L2 C3
2.2 mF
Figure 40. Typical LC Output Filter, Cutoff Frequency Of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 41. Typical Ferrite Chip Bead Filter (Chip Bead Example)
Zf
Ci
Zi
Input IN
Signal
The –3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 2.
1
f =
2p Zi Ci (2)
-3 dB
1
fc =
2p Zi Ci
fc (3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
1
Ci =
2p Zi fc (4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 μF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the DC level there is held at 3 V, which is likely higher than the source DC level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create DC offset
voltages and it is important to ensure that boards are cleaned properly.
OUTP
OUTN
No Output
OUTP
OUTP-OUTN 0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN 0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP-OUTN 0V
-PVCC
Speaker 0A
Current
Figure 42. The TPA3110D2-Q1 Output Voltage and Current Waveforms into an Inductive Load
10 Layout
SD PVCCL
FAULT PVCCL
LINP BSPL
GAIN1 OUTNL
GVDD OUTNR
RINN OUTPR
Audio input
RINP BSPR
NC PVCCR
PBTL PVCCR
Connect to ground
plane layer To PVCC
supply
Smaller high
frequency Via
decoupling
capacitors Copper trace/pour
Large bulk
decoupling
Thermal pad
capacitor
11.4 Trademarks
SpeakerGuard, PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Sep-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPA3110D2QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TPA3110Q1
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2015
• Catalog: TPA3110D2
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Feb-2019
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 28 PowerPAD TSSOP - 1.2 mm max height
4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/A
www.ti.com
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