Architecture & Organization —Processor - memory

• Architecture is those attributes visible to the – data transfer between CPU and main memory
programmer —Processor - I/O
• Instruction set, number of bits used for data – Data transfer between CPU and I/O module
representation, I/O mechanisms, addressing —Data processing
techniques. – Some arithmetic or logical operation on data
• e.g. Is there a multiply instruction? —Control
• Organization is how features are – Alteration of sequence of operations
implemented – e.g. jump
• Control signals, interfaces, memory technology. —Combination of above
• e.g. Is there a hardware multiply unit or is it Interrupts
done by repeated addition? • Mechanism by which other modules (e.g. I/O) may
Structure & Function interrupt normal sequence of processing
• Structure is the way in which components relate to each • Program
other. — e.g. overflow, division by zero
• Function is the operation of individual components as part • Timer
of the structure. — Generated by internal processor timer
Function — Used in pre-emptive multi-tasking
• All computer functions are: • I/O
• Data processing — from I/O controller
• Data storage • Hardware failure
• Data movement — e.g. power failure, memory parity error
• Control Interrupt Cycle
Program Concept • Added to instruction cycle
• Hardwired systems are inflexible • Processor checks for interrupt
• General purpose hardware can do different — Indicated by an interrupt signal
tasks, given correct control signals • If no interrupt, fetch next instruction
• Instead of re-wiring, supply a new set of control • If interrupt pending:
Signals — Suspend execution of current program
What is a program? — Save context
• A sequence of steps — Set PC to start address of interrupt handler routine
• For each step, an arithmetic or logical operation — Process interrupt
is done — Restore context and continue interrupted program
• For each operation, a different set of control Multiple Interrupts
signals is needed • Disable interrupts (approach #1)
Function of Control Unit —Processor will ignore further interrupts whilst
• For each operation a unique code (opcode) is processing one interrupt
provided —Interrupts remain pending and are checked after first
—e.g. ADD, MOVE interrupt has been processed
• A hardware segment accepts the code and —Interrupts handled in sequence as they occur
issues the control signals • Define priorities (approach #2)
Components —Low priority interrupts can be interrupted by higher
• The Control Unit (CU) and the Arithmetic and priority interrupts
Logic Unit (ALU) constitute the Central —When higher priority interrupt has been processed,
Processing Unit (CPU) processor returns to previous interrupt
• Data and instructions need to get into the Connecting
system and results need to get out • All the units must be connected
—Input/output (I/O module) • Different type of connection for different type of unit
• Temporary storage of code and results is —Memory
needed —Input/Output
—Main memory (RAM) —CPU
Instruction Cycle Memory Connection
• Two steps: • Receives and sends data
—Fetch • Receives addresses (of locations)
—Execute • Receives control signals
Fetch Cycle —Read
• Program Counter (PC) holds address of next —Write
instruction to fetch Input/Output Connection(1)
• Processor fetches instruction from memory • Similar to memory from computer’s viewpoint
location pointed to by PC —Receive data from computer
• Increment PC —Receive data from peripheral
—Unless told otherwise —Send data to peripheral
• Instruction loaded into Instruction Register (IR) —Send data to computer
Execute Cycle Input/Output Connection(2)
• Processor interprets instruction and performs • Receive control signals from computer
required actions, such as: • Send control signals to peripherals
• Receive addresses from computer Timing
—e.g. port number to identify peripheral • Co-ordination of events on bus
• Send interrupt signals (control) • Synchronous
CPU Connection —Events determined by clock signals
• Reads instruction and data —Control Bus includes clock line
• Writes out data (after processing) —A single 1-0 is a bus cycle
• Sends control signals to other units —All devices can read clock line
• Receives (& acts on) interrupts —Usually sync on leading edge
Buses —Usually a single cycle for an event
• There are a number of possible interconnection systems Arithmetic & Logic Unit
• Single and multiple BUS structures are most • Does the calculations
common • Everything else in the computer is there to
• e.g. Control/Address/Data bus service this unit
• e.g. Unibus • Handles integers
What is a Bus? • May handle floating point numbers
• A communication pathway connecting two or • May be separate FPU (maths co-processor)
more devices Integer Representation
• Usually broadcast (all components see signal) • Only have 0 & 1 to represent everything
• Often grouped • Positive numbers stored in binary
—A number of channels in one bus —e.g. 41=00101001
—e.g. 32 bit data bus is 32 separate single bit channels. • No minus sign
Data Bus • No period
• Carries data • Sign-Magnitude
—Remember that there is no difference between ―data‖ • Two’s compliment
and ―instruction‖ at this level Sign-Magnitude
• Width is a key determinant of performance • Left most bit is sign bit
—8, 16, 32, 64 bit. • 0 means positive
Address bus • 1 means negative
• Identify the source or destination of data • +18 = 00010010
• e.g. CPU needs to read an instruction (data) • -18 = 10010010
from a given location in memory • Problems
• Bus width determines maximum memory —Need to consider both sign and magnitude in
capacity of system arithmetic
—e.g. 8080 has 16 bit address bus giving 64k address Space. —Two representations of zero (+0 and -0)
Control Bus Benefits
• Control and timing information • One representation of zero
—Memory read/write signal • Arithmetic works easily
—Interrupt request • Negating is fairly easy
—Clock signals —3 = 00000011
Single Bus Problems —Boolean complement gives 11111100
• Lots of devices on one bus leads to: —Add 1 to LSB 11111101
—Propagation delays Negation Special Case 1
– Long data paths mean that co-ordination of bus use can • 0 = 00000000
adversely affect performance • Bitwise not 11111111
• Most systems use multiple buses to overcome • Add 1 to LSB +1
these problems • Result 1 00000000
Bus Types • Overflow is ignored, so:
• Dedicated •-0=0
—Separate data & address lines Negation Special Case 2
• Multiplexed • -128 = 10000000
—Shared lines • bitwise not 01111111
—Address valid or data valid control line • Add 1 to LSB +1
—Advantage - fewer lines • Result 10000000
—Disadvantages • So:
– More complex control • -(-128) = -128 X
Bus Arbitration • Monitor MSB (sign bit)
• More than one module controlling the bus • It should change during negation
• Only one module may control bus at one time Range of Numbers
• Arbitration may be centralised or distributed • 8 bit 2s compliment
Centralised Arbitration —+127 = 01111111 = 27
• Single hardware device controlling bus access -1
—Bus Controller — -128 = 10000000 = -2
—Arbiter 7
Distributed Arbitration • 16 bit 2s compliment
• Each module may claim the bus —+32767 = 011111111 11111111 = 2^15 - 1
• Control logic on all modules — -32768 = 100000000 00000000 = -2^15
Conversion Between Lengths 6-The remainder is in A. If the signs of the divisor and dividend
• Positive number pack with leading zeros were the
• +18 = 00010010 same, then the quotient is in Q; other wise, the correct quotient is
• +18 = 00000000 00010010 the twos complement of Q.
• Negative numbers pack with leading ones SAP Overview
• -18 = 10010010 • Simple As Possible • Describe the simplest computer
• -18 = 11111111 10010010 workings • 1st step evolution to advanced computer
• i.e. pack with MSB (sign bit)
development • Bus organized Computer
Addition and Subtraction
• Normal binary addition SAP-1 Characteristics
• Monitor sign bit for overflow Hardwire Architecture
— Both number positive (no overflow) (e.g. 7+4) • Two 8-bit general registers (A, B) • One 8-bit output
— Positive number with magnitude larger than negative number register • 8-bit ALU (addition, subtraction) • 4-bit
(overflow, discard carry) (e.g. 15-6) instructions and 4-bits operands (cccc oooo)
— Negative number with magnitude larger than positive number • cccc = OP CODE • oooo = OPERAND • 16x8 address RAM
(no overflow) (e.g. 16-24) for mixed program and data • 12 control signals
— Both numbers negative (overflow, discard carry) (e.g-5-9)
Program Counter
• Take twos compliment of substahend and add to
minuend • OUTPUT: 0000 to 1111 (0 to F) • CLK: Clock cycle • CLR:
— i.e. a - b = a + (-b) reset output to 0000 • Cp: (PC)  (PC)+1 • Ep: (PC)  bus W
• So we only need addition and complement circuits Memory Address Register (MAR)
Multiplication • INPUT: 4 bits • OUTPUT: 8 bits • CLK: Clock cycle • Lm: –
• Complex 0 : (MAR)  bus W
• Work out partial product for each digit Random Access Memory (RAM)
• Take care with place value (column)
• Store instruction & data • INPUT: 8 bits from MAR •
• Add partial products
Multiplication Example OUTPUT: 8 bits to bus W • CE: – 0 : (RAM)  bus W
• 1011 Multiplicand (11 dec) Instruction Register (IR)
• x 1101 Multiplier (13 dec) • Read an instruction from RAM • INPUT: 8 bits from RAM
• 1011 Partial products • OUTPUT: – 4 bits to bus W – 4 bits to CU • LI : – 0 : (IR) 
• 0000 Note: if multiplier bit is 1 copy 8-bit input • EI : – 0 : (IR) 4-bit bus W
• 1011 multiplicand (place value) CU/Sequencer
• 1011 otherwise zero
• Control all execution flow • INPUT: 4 bits from IR •
• 10001111 Product (143 dec)
• Note: need double length result OUTPUT: – 12 bits to be distributed to all components
Multiplying Negative Numbers (microinstruction) – CPEPL’MCE’ L’IE’IL’AEA SUEUL’BL’O
• Solution 1 Accumulator (ACC)
—Convert to positive if required • Register buffer for storing temporary computation result
—Multiply as above • INPUT : 8-bit from bus W • OUTPUT : – 8-bit to bus W –
—If signs were different, negate answer 8-bit to ALU • L’A : – 0 : ACC  bus W • EA : – 1 : ACC  bus
—E.g. 9X3 W
• Solution 2
ALU
—Booth’s algorithm
Division • Adder & Subtractor Only
• More complex than multiplication • INPUT : – 8-bit from ACC – 8-bit from B register • Output
• Negative numbers are really bad! : – 8-bit to bus W • SU : – 1 : subtract – 0 : add • EU : – 1 :
• Based on long division ALU  bus W
Steps for Signed Binary Division B Register
1-Load the divisor into the M register and the dividend into the A, • Buffer for arithmetic operation • INPUT : 8-bit from bus
Q registers.
W • Output : 8-bit to ALU • L’B : – 0 : B  bus W
The dividend must be expressed as a 2n-bit twos complement
number. Thus, Output Register
for example, the 4-bit 0111 becomes 00000111, and 1001 • Output port – The processed data can be accessed by
become 11111001. output device via this register • INPUT : 8-bit from ACC via
2-Shift A, Q left 1 bit position. bus W • OUTPUT : 8-bit to output device • L’O : – 0 :
3-If M and A have the same signs, perform A=A-M; other wise, Output Register  bus W
A=A+M. Binary Display
4-The preceding operation is successful if the sign A is the same
• An output device that consists of 8 LEDs • can be
before and
after the operation.
changed with any other output devices
a. If the operation is successful or A=0, then set Q0=1.
b. If the operation is unsuccessful and A≠0, then set Q0=0 and
restore the
previous value of A.
5-Repeat steps 2 through 4 as many times as there are bit
positions in Q.

Instruction Cycle
• Fetch Cycle – T1 (Address State) – T2 (Increment State) –
T3 (Memory State) • Execution Cycle – Three step (T4, T5,
T6), but the task of each steps depends on the instruction
Exectution Cycle (LDA Instruction)
• For LDA instruction, only T4 and T5 states that will be
active – T4 : memory address is sent from IR to MAR – T5 :
data from memory is fetched and send to ACC – T6 : do
nothing ! = T0
Execution Cycle • What about the execution cycle for
ADD / SUB / OUT instruction ?
SAP-1 Programming • Problem : – Write a program using
SAP-1 computer that computes the following operation :
16+20+24+28-32
SAP-1 Programming (2) • Solution : –Assign the data
memory with this data: 
R9=00010000(16),RA=00010100(20),
RB=00011000(24),RC=00011100(28), RD=00100000 (32) –
The codes: 1. LDA R9 2. ADD RA 3. ADD RB 4. ADD RC 5.
SUB RD 6. OUT 7. HL
SAP 2 Block Architecture • Evolution towards
modern computers because it includes JUMP
instruction.
Input Port
• Port 1 and Port 2
• Port 1 – Hexadecimal keyboard encoder –
Sends ready signal to bit 0 of port 2 (indicates
that data in port 1 is valid)
• Port 2 –Serial In
Program Counter
• 16 bit address • Thus can count from • PC =
0000 0000 0000 0000 • PC = 1111 1111 1111
1111 (FFFF H)
MAR and Memory
• 16-bit address to MAR • MAR output to RAM
• Memory Capacity – 2K ROM (0000H to
07FFFH) Monitor Program – 62K RAM (0800H to
FFFFH)
Memory Data Register (MDR)
• 8-bit Register • Output setup RAM • Receives
data from the bus before write operation • Data
to the bus after read operation.
Instruction Register (IR)
• 8-bit op code • Can accommodate 256
instructions • Only 42 instruction
Controller Sequencer
• As usual – Generates the control word
(microinstructions) – Has more hardware (larger
number of instructions) – Control word is bigger
(CON)
Accumulator • Same as SAP-1
ALU and Flags
• ALU – Includes both arithmetic and logical
operations. • Flags – Represent the status of
the arithmetic and logical operation. – Flip flops
are used: • Zero Flag (Z) • Sign Flag (S)
Temp, B and C Registers
• Temporary register (TEMP) • Register B and C
are used to move data during program run and
accessible to programmers.
Outport Ports • Two output ports (3 and 4) •
Port 3: – Drives Hexadecimal display • Port 4: –
Sends ACKNOWLEDGE signals used to
hexadecimal encoder. (Handshaking) • Serial
Out: – Serial Transmission of data
Instructions
• LDA and STA • For example: – LDA 2000H –
STA 8000H
MVI • MVI
- Move Immediate • For example: • MVI A, 37H
• Other instructions are: – MVI B, byte – MVI C,
byte
Register Instructions
• MOV – MOV A, B – MOV A,C – MOV B, A –
MOV B, C – MOV C,A
Register Instruction
• ADD and SUB • For example: – ADD B – ADD
C – SUB B – SUB C
Register Instruction
• INR and DCR • INR A/ DCR A • INR B/ DCR B •
INR C/ DCR C
Jump And Call Instruction
• JMP • For example: – JMP 3000 H • JM (Jump
if Minus) • JZ (Jump if Zero) • JNZ (Jump if not
zero)
Jump And Call Instruction • CALL – Call is used
to call the subroutine • RET – Return back from
subroutine – Program counter contents are
stored in the last two location of memory
(FFFEH and FFFFF)
Logic Instruction
• CMA-Complement the accumulator • ANA-
And the accumulator with specified register. For
example: ANA B • ORA- OR the accumulator
with specified register. For example: ORA B •
XRA- XOR the accumulator with specified
register. For example XRA B
Logic Instruction
• ANI: And Immediate • For example: • ANI C7H
(AND accumulator with immediate data C7H) •
ORI: OR immediate • For example: ORI C7H •
XRI: XOR immediate • For example: XRI C7H
Other Instruction • OUT byte • For example:
OUT 03 H; accumulator to designated port. •
HLT • IN (Input: Enter the data from designated
input port to accumulator) • For example: IN 01
H • NOP • RAL (Rotate the accumulator left) •
RAR (Rotate the accumulator right)
SAP 3 • 8 bit microcomputer • Upward
compatible with 8085
MOV and MVI
• MOV reg1, reg2 • Where reg1 = A, B, C, D, E,
H, L reg2 = A, B, C, D, E, H, L • For example: –
MOV L,A – MOV E,H • MVI reg, byte • Where
reg1 = A, B, C, D, E, H, L • For example: – MVI D,
0EH – MVI L, FFH
ADD Instructions
• ADD reg Where reg = A, B, C, D, E, H, L • ADC
reg Where reg = A, B, C, D, E, H, L
SUB Instructions
• SUB reg Where reg = A, B, C, D, E, H, L • SBB
reg Where reg = A, B, C, D, E, H, L
Increment, Decrements and Rotates
• INR reg Where reg = A, B, C, D, E, H, L • DCR
reg Where reg = A, B, C, D, E, H, L • RAL (with
carry) • RAR (with carry) • RLC (without carry) •
RRC (without carry)
Logical Instructions
• ANA reg • ORA reg • XRA reg Where reg = A,
B, C, D, E, H, L • CMP reg Where reg = A, B, C, D,
E, H, L
Arithmetic and Logic Immediates • ANI byte •
ORI byte • XRI byte • ADI byte • ACI byte • SUI
byte • SBI byte • CPI byte
JUMP Instructions
• JMP address (unconditional jump) • JM
address (Jump if minus) • JZ address (Jump if
zero) • JNZ address (Jump if not zero) • JP
address • JC address • JNC address • JPE
address • JPO address
Extended Register Instructions
• Load extended immediate LXI B, dble LXI D,
dble LXI H, dble Where: B stands for BC D stands
for DE H stands for HL dble stands for double
byte
Extended Register Instructions
• DAD Instructions DAD B DAD D DAD H Where:
B stands for BC D stands for DE H stands for HL
Extended Register Instructions
• INX and DCX Instructions INX B INX D INX H
Where: B stands for BC D stands for DE H stands
for HL
Indirect Instructions
• HL register pair acts like a data pointer. • The
contents of HL register pair are used as the
address for data in memory. • MOV reg, M •
MOV M, reg • MVI M, byte • ADD M • ADC M •
SUB M • SBB M • INR M • DCR M • ANA M •
ORA M • XRA M • CMP M
Stack Instructions
• The Stack • Stack Pointer • PUSH B, D, H, PSW
(PSW is program status word, AF) • POP B, D, H,
PSW • CALL, RET (return) • CNZ address….RNZ •
CZ address…CNZ • CNC address….RNC • CC
address….RC • CPO address….RPO • CPE
address….RPE • CP address….RP • CM
address….RM