5 4 3 2 1

D D

C C
EE:M.KASHI,S.VANGENT

B B

Intel® Curie™ Module Design Document

This Intel® Curie™ module design document is licensed by Intel

under the terms of the Creative Commons Attribution
Share-Alike License (ver. 3), subject to the following terms and
conditions. The Intel Curie module design document IS
A A
PROVIDED "AS IS" AND "WITH ALL FAULTS." Intel
DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR
IMPLIED REGARDING THE INTEL CURIE MODULE DESIGN
OR THIS INTEL CURIE MODULE DESIGN DOCUMENT
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE. Intel may make changes to the
specifications, schematics, and product descriptions at any
INTEL New Devices Group
time, without notice. The customer must not rely on the absence
or characteristics of any features or instructions marked
ARDUINO 101
EE:M.KASHI,S.VANGENT Size CAGE Code DWG NO Rev
"reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them. Custom SCHEM FOR TA=H94227 1
ENJOY! Monday, January 25, 2016 Scale Sheet
1 of 4
5 4 3 2 1
 5 4 3 2 1

Power Input SEL

USB Power Input
TRIG_TRUE_D
USB_5P00_PWR V_5P00SRC_VDD1 DC_IN_5V_20V DC_IN_5V_20V

AU-Y1007-2-R USB USB_5P00_PWR CURIE_VBUS U13

A3 A1
J17 22 R12 VIN1 VOUT1
B3 B1 R81
1 VIN2 VOUT2 R83
VBUS 22 R32 3K 1%
2 C3 C2 1.5K 1% TRIG_TRUE_D
D DAT- USBDN_CONN 3 ONB ISET D
22 R31 U202
5 3 A2 C1
S1 DAT+ USBDP_CONN 3 GND1 OC_FLAG
6 4 C18 B2 1 5
S2 GND GND2 VDD C_DLY

1
R74 C39 R57 2
GND1

CLAMP
ESD10
4.7uF FPF2496 698 0.1uF 10K 10UF 3 4
GND2 DOUT

ESD11
28V 1% 6.3V C49
C42 10V R3119N050A

1
4.7uF C55
28V 2 SH10 R82 C54 R75 0.1uF

2
Short_pad R73 10K 1% 0.1uF 1000 25V
402 25V 1%
1%

2
CURRENT LIMITS RESISTOR VALUES
2100=500mA; 698 = 1.5A; 1100 = 1A
Short for 1.5A
Trip set to 5.75V

Barrel Power Input

TRIG_TRUE_D
20V tolerant
7-17VDC IN DC_IN_JACK DC_IN_5V_20V DC_IN_5V_20V_FIL V_5P00SRC_VDD1

V_5P00SRC_VDD1 V_3P3SRC_VDD1
C RSX501L-20TE25 C
2DC-0005D200 RSX501L-20TE25 LM1117DTX-3.3 NOPB
D17 300Ohm_100M D18 TPS62153RGT
J16 L13 U10 L10 U17
1 1 2 11 1 1 2 3 2
DC+ 12 PVIN1 SW1 2 2.2uH IN OUT
10 PVIN2 SW2 3
AVIN SW3
GND1

GND2

13 14 1
ENA VOS 4 GND
PG
C36 C50 R70
2

0.1uF 4.7uF C12 C16 R77 10K C14 C11 10UF

25V 28V 4.7uF 4.7uF 10K 6.3V 4.7uF C13
28V 28V 5 22uF 10V 10V
8 FB 6
DEF AGND 15
9 PGND1 16
SS/TR PGND2
NS_A93550-116

7 17
R71 FSW THERM
10K C15

0.033uF

B B
DC_IN_5V_20V

V_3P3SRC_VDD1 V_5P00SRC_VDD1 GENW BOARD SPECIFIC

J10
1
3,4 IO14_NEW N/A
2
3 IOREF
2,3,4,5 RST_SKETCH RESET
4 VDD_PLAT_3P3 VDD_PLAT_3P3
5 3V3 Com D14 GREEN
5V0 R15
6
GND1 330 U16
7
GND2 TXLED 3 D13 GREEN
8 1 5
VIN 2 NC VCC 1K R14
3,4,5 ATPSCK/IO2_3V_IO13 A
8 PIN SOCKET 3 4 MARK "L"
FaultD15 SML-P11UTT86 GND Y
R16
PTS645-S-M-43-SMTR92-LFS 330 SN74AUP1G34DBVR
R65
RXLED 3
SW12 100 R23 200K
3 1
RST_SKETCH 2,3,4,5
RESET SKETCH 4 2
C41 Power
33pF R10
D10
25V

GREEN
330
A PTS645-S-M-43-SMTR92-LFS A

SW10 100 R13

1 3

INTEL
M_RESET 3
Master reset-
2 4
C19 New Devices Group
33pF
25V
ARDUINO 101
EE:M.KASHI,S.VANGENT Size CAGE Code DWG NO Rev
Custom SCHEM FOR TA=H94227 1
Monday, January 25, 2016 Scale Sheet
2 of 4
5 4 3 2 1
 5 4 3 2 1

I/O Antenna
Power and reset U12B VDD_PLAT_3P3
G22 J18
COMP_AREF E21 1 4
AON_IO_VCC H23 3
ADC_3P3_VCC H22 22 R35 2
CMP_3P3_VCC K2 NS_A93552-004
BUCK_VSEL C20 C21 C22 R18
VDD_PLAT_3P3 J2 0R MHF4
GPIO/AIN_10 AD10/SS2_3V_AD0 4,5
H21 10UF 10UF 0.1uF NS_G42632-002
GPIO/AIN_11 AD11/SS3_3V_AD1 4,5
U12D H2
D GPIO/AIN_12 AD12/SS4_3V_AD2 4,5 D
K23 L2
ATP_TRST_B DBG_AP_JTAG_TRST_N 3 GPIO/AIN_13 AD13/SS5_3V_AD3 4,5 1.2pF
M23 C24
ATP_TDO DBG_AP_JTAG_TDO 3 GPIO/AIN_14 AD14/SS6_3V_AD4 4,5 0R R19 RLC10
M21 K21
ATP_TDI DBG_AP_JTAG_TDI 3 UART1_RTS/AN09 AD09/SS1_3V_AD5 4,5 3 BT_ANT_50
L24
ATP_TMS DBG_AP_JTAG_TMS 3
L23 H1 Internal ANT
ATP_TCK DBG_AP_JTAG_TCK 3 PWM0_OUT PWM0/SS10_3V_IO3 3,4,5
G2 C38 C37 RLC11
PWM1_OUT PWM1/SS11_3V_IO5 3,4,5
G1 NP 4.7nH NP
PWM2_OUT PWM2/SS12_3V_IO6 4,5
F2
R30 PWM3_OUT PWM3/SS13_3V_IO9 4,5
10K

H24 10pF
VDD_BLE_SEN G23 RLC12
BLE_DEC2 BT_ANT_50 3
D23
MRESET_B M_RESET 2 BT_AOUT_50
B4 F24 C47 C46 VDD_PLAT_3P3
ATP_RST_B E23 BLE_RF NP NP
POR_B B23 JTAG
E3 BLE_SDA F23 J15
PLT_CLK_0 MISO1/IO9_3V_IO8 3,4,5 BLE_SCL 1 2
VCC TMS DBG_AP_JTAG_TMS 3
E24
BLE_SWDIO NOR_SWD_SDA 3
CURIE_V3 D24 3 4
BLE_SW_CLK NOR_SWD_SCL 3 GND1 TCLK DBG_AP_JTAG_TCK 3
B24
BT_GPIO 5 6
GND2 TDO DBG_AP_JTAG_TDO 3
CURIE_V3
CURIE_VBUS 7 8
RTCK/KEY TDI DBG_AP_JTAG_TDI 3
U12C
0R R59
K4 U12F 9 10
VDD_USB GND3 RESET DBG_AP_JTAG_TRST_N 3
USB DIFF SIGNALS N24
C I2C0_SS_SCL SCL0_SS_3V_AD5 4,5 C
J23 N23 20021111-00010T4LF
USB_DM USBDN_CONN 2,3 I2C0_SS_SDA SDA0_SS_3V_AD4 4,5
J24
USB_DP USBDP_CONN 2,3
F1
K24 I2C1_SS_SCL E2
VIN_1 N21 C17 I2C1_SS_SDA
VIN_2 4.7uF M24
28V I2C0_SCL P23 V_3P3SRC_VDD1 VDD_PLAT_3P3
N22 VSYS PV_BATT I2C0_SDA
BATT_TEMP 0R R58
P21 E1
SW_FG_VBATT I2C1_SCL D2 A93552-004
M1 I2C1_SDA VSYS
PV_BATT M22 F4
CHG_STATUS ATP_SPI_S_MOSI ATPMOSI/IO3_3V_IO11 3,4,5 0R R63
L22 G3
BATT_ISET ATP_SPI_S_MISO ATPMISO/IO1_3V_IO12 3,4,5
L4 E4 A93552-004
VSYS ATP_SPI_S_SCK ATPSCK/IO2_3V_IO13 2,3,4,5
J1 F3
AVD_OPM_2P6 ATP_SPI_S_CS ATPSS/IO0_3V_IO10 3,4,5
L21 C25 C26 C23 C24
AGND P1 4.7uF J21 Test Points
GND1 UART1_TX TXD1/SS8_3V_IO1 4,5
A2 0.1uF 10UF 0.1uF K22 1 TPB10
GND2 UART1_RX RXD1/SS9_3V_IO0 4,5 3 NOR_SWD_SDA
P22 10V J22
GND3 UART1_CTS ATPCTS/IO9_3V_IO14 2,4
C23 1 TPB11
GND4 3 NOR_SWD_SCL
G24
GND5 G21
GND6 A24 R24 A21
GND7 P24 NP 6AXIS_SDA A22 Test JTAG
GND8 6AXIS_SCL A23 1
6AXIS_INT2 3 DBG_AP_JTAG_TMS TPB12
CURIE_V3
A3 1 TPB13
B I2S_RXD PWM1/SS11_3V_IO5 3,4,5 3 DBG_AP_JTAG_TCK B
B2
I2S_RSCK MISO1/IO9_3V_IO8 3,4,5
B1 1
I2S_RWS PWM0/SS10_3V_IO3 3,4,5 3 DBG_AP_JTAG_TDO TPB14
C2
I2S_TSCK I2S_TSCK/IO18_3V_IO2 4,5
VSYS C1 1 TPB15
I2S_TWS I2S_TWS/IO19_3V_IO4 4,5 3 DBG_AP_JTAG_TDI
D1
I2S_TXD I2S_TXD/IO20_3V_IO7 4,5
U12A 3V Buck not used 1 TPB16
3 DBG_AP_JTAG_TRST_N
P2 CURIE_V3
ESR1_VBATT N2 1
VDD_PLAT_3P3 2,3 USBDN_CONN TPB17
1
2,3 USBDP_CONN TPB18
N1 U12E
ESR1_LX C45 C31 C32 D3
SPI0_M_MOSI SP0_MOSI_MEM 4,5 USB_5P00_PWR
D4
SPI0_M_MISO SP0_MISO_MEM 4,5
0.1uF 4.7uF 0.1uF C4
SPI0_M_SCK SP0_CLK_MEM 4,5
B3 1 TPB19
SPI0_M_CS0 SP0_CS0_MEM 4,5
A4
SPI0_M_CS1 SP0_WP_MEM~ 4,5
C3 DC_IN_JACK
SPI0_M_CS2 RXLED 2
VDD_PLAT_1P8
N4 E22 1 TPB20
ESR2_VBATT SPI1_M_MOSI ATPMOSI/IO3_3V_IO11 3,4,5
M2 B22
VDD_PLAT_1P8 SPI1_M_MISO ATPMISO/IO1_3V_IO12 3,4,5
1.8V Buck not used C21 VDD_PLAT_3P3
SPI1_M_SCK ATPSCK/IO2_3V_IO13 2,3,4,5
M4 D22
ESR2_LX SPI1_M_CS0 ATPSS/IO0_3V_IO10 3,4,5
C33 C28 D21 1 TPB21
SPI1_M_CS1 TXLED 2
B21
4.7uF 0.1uF SPI1_M_CS2 C22 1
SPI1_M_CS3 TPB22
L1
LDO1P8_VOUT M3 1
SPI0_SS_MOSI TPB23
J3
K1 SPI0_SS_MISO J4
A BUCK_VOUT SPI0_SS_SCK H4 A
SPI0_SS_CS0 H3
P3 V_1P8_ESR3 SPI0_SS_CS1 K3
VDD_HOST_1P8 SPI0_SS_CS2 G4

INTEL
SPI0_SS_CS3
ESR3_LX
P4 2
22uH L12
1
F22
RST_SKETCH_3V 2,4,5
New Devices Group
CURIE_V3 C35 C48 C29 C30 ATP_INT0 N3
ATP_INT1
0.1uF 0.1uF 4.7uF 0.1uF ATP_INT2
ATP_INT3
L3
F21 ARDUINO 101
EE:M.KASHI,S.VANGENT Size CAGE Code DWG NO Rev
CURIE_V3
Custom SCHEM FOR TA=H94227 A
Monday, January 25, 2016 Scale Sheet
3 of 4
5 4 3 2 1
 5 4 3 2 1

VDD_PLAT_3P3
VDD_PLAT_3P3 V_3P5_VREFA V_5P00SRC_VDD1
U201
1 8
10K R33 3,5 SP0_CS0_MEM CS VCC
1.8K R34
2 7
3,5 SP0_MISO_MEM MISO HOLD
3
3,5 SP0_WP_MEM~ WP
C43 C44
0.1uF C51 0.1uF
0.1uF 5
D 3,5 SP0_MOSI_MEM MOSI D
6 4
3,5 SP0_CLK_MEM SCK VSS
V_3P5_VREFA U15 LSF0108 V_5P00SRC_VDD1 W25Q16DVSSIG
200K R27 R62
1 20 10K
2 GND EN 19
3,5 SCL0_SS_3V_AD5 VREF_A VREF_B
3,5 SDA0_SS_3V_AD4 3 18
4 A1 B1 17
5 A2 B2 16
3,5 AD09/SS1_3V_AD5 A3 B3 AD5_SCL 3,4,5
3,5 AD14/SS6_3V_AD4 6 15 AD4_SDA 3,4,5
7 A4 B4 14
3,5 AD13/SS5_3V_AD3 A5 B5 AD3 3,4,5
3,5 AD12/SS4_3V_AD2 8 13 AD2 3,4,5 J14
9 A6 B6 12 6
3,5 AD11/SS3_3V_AD1 A7 B7 AD1 3,4,5 3,4,5 AD5_SCL AD5/SCL
3,5 AD10/SS2_3V_AD0 10 11 AD0 3,4,5 5
A8 B8 3,4,5 AD4_SDA AD4/SDA
4
3,4,5 AD3 AD3
3
3,4,5 AD2 AD2
2
3,4,5 AD1 AD1
1
3,4,5 AD0 AD0
6 PIN SOCKET

C C

C52 V_5P00SRC_VDD1
0.1uF J12
1 2
3,4,5 IO12/MISO MISO 5V0
3 4
2,3,4,5 IO13/SCK SCK MOSI IO11/MOSI 3,4,5
5 6
2,3,4,5 RST_SKETCH RESET GND
V_3P5_VREFA U14 LSF0108 V_5P00SRC_VDD1
200K R28 2X3 PIN HEADER
1 20
2 GND EN 19
3 VREF_A VREF_B 18 AREF
2,3,5 RST_SKETCH_3V A1 B1 RST_SKETCH 2,3,4,5
4 17 J11
2,3 ATPCTS/IO9_3V_IO14 A2 B2 IO14_NEW 2,3
5 16 10
2,3,5 ATPSCK/IO2_3V_IO13 A3 B3 IO13/SCK 2,3,4,5 3,4,5 AD5_SCL AD5/SCL
6 15 9
3,5 ATPMISO/IO1_3V_IO12 A4 B4 IO12/MISO 3,4,5 3,4,5 AD4_SDA AD4/SDA
7 14 8
3,5 ATPMOSI/IO3_3V_IO11 A5 B5 IO11/MOSI 3,4,5 AREF
8 13 7
3,5 ATPSS/IO0_3V_IO10 A6 B6 IO10/SS 3,4,5 GND
9 12 6
3,5 PWM3/SS13_3V_IO9 A7 B7 IO9/PWM3 3,4,5 2,3,4,5 IO13/SCK SCK
10 11 5
3,5 MISO1/IO9_3V_IO8 A8 B8 IO8 3,4,5 3,4,5 IO12/MISO MISO
4
3,4,5 IO11/MOSI MOSI/PWM
3
3,4,5 IO10/SS SS/PWM
2
3,4,5 IO9/PWM3 IO9/PWM
1
3,4,5 IO8 IO8
10 PIN SOCKET
B B

Intel® Curie™ Design Document

C53 This Intel® Curie™ design document is licensed by Intel under the
0.1uF terms of the Creative Commons Attribution Share-Alike License
(ver. 3), subject to the following terms and conditions. The Intel®
Curie™ design document IS PROVIDED "AS IS" AND "WITH
ALL FAULTS." Intel DISCLAIMS ALL OTHER WARRANTIES,
EXPRESS OR IMPLIED REGARDING THE CURIE DESIGN OR
V_3P5_VREFA U11 LSF0108 V_5P00SRC_VDD1 THIS CURIE DESIGN DOCUMENT INCLUDING, BUT NOT
200K R29 LIMITED TO, ANY IMPLIED WARRANTIES OF
1 20 MERCHANTABILITY OR FITNESS FOR A PARTICULAR
2 GND EN 19 J13 PURPOSE. Intel® may make changes to the specifications,
3 VREF_A VREF_B 18 8 schematics and product descriptions at any time, without notice.
3,5 I2S_TXD/IO20_3V_IO7 A1 B1 IO7 3,4,5 3,4,5 IO7 IO7 The Customer must not rely on the absence or characteristics of
3,5 PWM2/SS12_3V_IO6 4 17 IO6/PWM2 3,4,5 3,4,5 IO6/PWM2 7 any features or instructions marked "reserved" or "undefined."
5 A2 B2 16 6 IO6/PWM
3,5 PWM1/SS11_3V_IO5 A3 B3 IO5/PWM1 3,4,5 3,4,5 IO5/PWM1 IO5/PWM Intel® reserves these for future definition and shall have no
3,5 I2S_TWS/IO19_3V_IO4 6 15 IO4 3,4,5 3,4,5 IO4 5 responsibility whatsoever for conflicts or incompatibilities arising
7 A4 B4 14 4 IO4 from future changes to them.
3,5 PWM0/SS10_3V_IO3 A5 B5 IO3/PWM0 3,4,5 3,4,5 IO3/PWM0 IO3/PWM
3,5 I2S_TSCK/IO18_3V_IO2 8 13 IO2 3,4,5 3,4,5 IO2 3 ENJOY!
9 A6 B6 12 2 IO2
3,5 TXD1/SS8_3V_IO1 A7 B7 IO1/TXD 3,4,5 3,4,5 IO1/TXD IO1/TXD
3,5 RXD1/SS9_3V_IO0 10 11 IO0/RXD 3,4,5 3,4,5 IO0/RXD 1
A8 B8 IO0/RXD
A 8 PIN SOCKET A

INTEL New Devices Group

ARDUINO 101
EE:M.KASHI,S.VANGENT Size CAGE Code DWG NO Rev
Custom SCHEM FOR TA=H94227 1
Monday, January 25, 2016 Scale Sheet
4 of 4
5 4 3 2 1