Rfid Readers Beam - Forming Digital Assisted RF and Taiwan

ISSCC 2007 trends
RFID reader, Beam-forming,

Digital assisted RF & Taiwan!
Ali Fotowat, PhD.
Managing Director
KavoshCom Asia R&D
afa@KavoshCom.Com
April 9, 2007
KavoshCom Asia R&D 1 April 9, 2007

Get rid of L’s
Small scalable and no L LNA’s
23.3 IMEC and Vrije Univ, DC-6 GHz, 90 nm, smaller
than a pad, 17 dB gain, less than 3.5 dB NF, ESD
protection, S11 better than -10 dB, less than 10mW
@ 1.2 V , 50x35 m2
23.4 Linkoeping U of Sweden, DC-6 GHz, 130 nm, 25
mW @ 1.4 Volts, 170x100 m2

But transformers still remain
Transfomer for broad-band matching and feedback
23.1 NXP, 2-8 GHz LNA/Mixer/IF, 23 dB gain, NF
2.5 dB, 65 nm, 1.2 v, 15/8/9.3 mA, 120x130u
Trans

…and more transformers
Use transfomers for broad-band matching and
also notch filters
23.2 U of Padova, Infinion, 3-5 GHz LNA, 17 dB gain,
NF 3.5 dB, 130 nm, use middle of the cascode for
a 5.1 GHz notch

Transformer for variable tuning!
Broad-band magnetic tuning with transformers!
4.8 U of Pavia, 3.2-7.6 GHz Quad VCO based on magnetic tuning
But wait is it magnetic tuning or variable impedance with gm?

10.4 Delft, IBM, 23-29 GHz VCO uses a tapped transformer with
variable negative resistance for tuning
Get rid of external front-end filters
Concept of a high Q tunable front-end filter!
4.4 BroadCom, H. Darabi, Achieve 21 dB rejection of
blockers by tunable filter and active cancellation
when needed!

Circuit tech for nm low volt range
Lower headroom, higher speed, smaller size!
17.7 Univ of Twente, Voltage sense/latch Amp, 90nm,
1.2 volts, 18 pS set-up and hold
17.8 Vienna UofT, Comparator, 120 nm, 0.5 volt, 600
MHz, 1.5 volt, 6 GHz

Circuit tech (Measuren on chip)
Does it give you new ideas for VCO design?
30.5 Arizona S. U., The conventional delayed self
mixing method for phase noise measurement is
implemented on chip.

DLL/PLL/ClockGen/Divider/Synth
17.3 Pohang U, 40-800 MHz DLL in 130nm
17.4 PA Semi, A no L, 2 supply 0.2-4GHz PLL clock multiplier in
65nm
17.5 Samsung, A no L, 1.2 mW 0.02mm2 I controlled 2GHz PLL
17.6 IBM, A no L, 1V 18 GHz clock gen in 65nm
23.6 UCLA Razavi, Heterodyne phase locking divider
30.4 National Taiwan U, 40GHz phase locking divide by 2 & VCO
23.8 Nationa Taiwan U, Jri Lee, 75 GHz PLL in 90 nm
30.2 IBM, 70 GHz LC VCO in 65nm
32.5 U of Washington, 2.1 GHz Quad VCO with BAW resonator
32.7 ST Micro, 2 GHz SiGe BiCMOS with BAW resonator
17.1 UCSD, 2.4 GHz frac-N with internal noise cancellation
17.2 Columbia U, 2.5 GHz 0.65 volt, frac-N in 90nm

DLL
17.3 Pohang U, 40 phases are generated based on a 5X8 delay
matrix orchestra!


PLL/Clock Gen
90-65 nm means low voltage and low parasitics. Why bother
with an LC resonator to get high-speed? Also note the
reduced active areas and low powers.
17.4 PA Semi, Uses two Vdd’s and a no L singles stage VCO
17.5 Samsung, Uses low voltage structures for a delay ring CCO
17.6 IBM, An interpolating inverter ring oscillator uses multiple
phases and 4 inverters in each composite inverter, plus a
resistor phase shifter MOS device to make sure that in all
process corners the large lock range of 2-30 GHz is achieved.


Phase locking dividers
23.6 UCLA Razavi, Wideband divide by N is achieved by using N
mixers. In this case from 64GHz to 70 GHz is divided by 2. The
achieved BW is less than what would be expected from this
circuit.
30.4 National Taiwan U, 40GHz phase locking regenerative divider
offers a divide by 2 from 38 to 50 GHz. It is inherently frequency
selective and requires high VCO power at frequency extremes. The
VCO combines cross-coupled LC with Colpitts like capacitive
feedback from the source.

PLL
23.8 Nationa Taiwan U, Jri Lee, 75 GHz PLL in 90 nm. A
summation of GHz ready ideas!
Distributed resonator in the high frequency.
A quad phase detector and a separated frequency detector.
Injection locked divide by two, followed by Miller, followed by
Class AB.

VCO
30.2 IBM, 70 GHz LC VCO in 65nm 6GHz tuning range
32.5 U of Washington, 2.1 GHz Quad VCO with ext BAW resonator
32.7 ST Micro, 2 GHz SiGe BiCMOS with chip mounted BAW
-112dBc/Hz @ 10MHz -143dBc/Hz @ 1MHz -110dBc/Hz @ 1MHz

Fractional N Synthesizers
17.1 UCSD, Like Perrott’s technique but with 35 S settling
time instead of 1 Sec. Instead of subtracting the average error
term the original error is subtracted depending on matched
gains.
17.2 Columbia U, Uses
all known techniques
for discrete tuning. 
switching noise is
avoided by getting 4 bits
truncation from a 24 bit
MASH 111!!

Stazewski’s Digital RF Continues
Coventional loop
Uses a an analog block for PFD and filter. The loops
blurs the repetitive N and N+1 division.
Staszewski
Says use a Time to Digital Converter instead and all will be digital.

What is a Time to Digital Converter?
It is simply counting the time difference with a
high frequency clock and dividing by the period
(Rediscovered again!!)

How do you make the
counting high speed clock?
Staszewski uses a 48 element
(20 pS each) delay line and
counts the leading edges. It is
the equivalent of an XOR
and an integrator.
Then he normalizes it with

the period.
But won’t he be limited by

the variation of the inverter
delays with scaling??

A new all digital approach
19.9 U of Michigan, M. Ferris, Michael Flynn,
Allow the comparison frequency to increase.
Use only one flip-flop and
use a new loop to further
change the N/N+1 divide
ratio.

Use only one flip-flop and
use a new loop to further
ratio.
Add an integrator for proper
Low-pass/All pass loops

Use a new loop to further
ratio.
Add an integrator for proper
Low-pass/All pass loops.
Use an additional circuit for
fast data modulation and add
to VCO input

PA’s and Polar Modulation
Polar Modulation methods
4.1 Stanford U, Kavousian/Wooley, Save power by turning on the
number of needed 64 blocks, allows power efficiency as well as
the linearity needed for 64QAM OFDM.

Polar Modulation methods
4.3 Arizona S. U., Use a switched mode Amp for power efficiency.
Use Modulation to blur switching noise. The resulting low
pass response affects the amplitude modulation, hence pre-
emphasis is used.

Predistortion to remove 3rd and 5th order intermod
Product
19.8 Sony, Uses a 5th
order polynomial for
Pre-distortion.
Look-up tables are
needed for
compensation vs. T
Vdd, freq and power.
This is used for
handsets

More PA control circuitry
4.2 U of Catania, For VSWR protection use a MOS based rectifier
subtractor!!
19.7 Hitachi/Renesas, Transmitter loop BW control adjusts for
VCO sensitivty vs. frequency. Also interesting simulations and
provisions for eliminating zero pass-through in polar PA’s

Digital Assisted RF
Expect many new circuits like this in future
4.5 U of Erlangen, Calibrate the mixer for iip2 minimization. The
main issue of searching for a min is solved by 2 counters.

The 60 GHz experimentation club
No new killer circuit ideas other than speed and the possibilities
opened by the availability of microstrips.
10.1 UCLA, Razavi, LNA/Mixer receiver at 50GHz
10.2 UC Berkeley, Emami, 60 GHz Rx, uses a doubler for LO,
Noise figure and gain are almost the same (11 dB)!
10.3 National Taiwan U, A 60 GHz TRx, multiple ports for BB
10.5 National Taiwan U, 60 GHz synthesizer. Lots of overlap with
Jri Lee’s 23.8
10.6 Ruhr U, 90 GHz injection locked divider. Very similar to 30.4
without the broad-banding idea.
10.7 UC Berkeley, Heydari, Testing some 104 GHz blocks in 90nm

Beam forming and radar
Think of this as narrow band beam forming
6.7 USC, Krishnaswamy, H. Hashemi, 24GHz in 130 nm shows
beam steering Tx and Rx with on air combining. The key is the
variable phase ring oscillator
2.35mm X 2.15mm

Think of this as narrow band beam forming
6.7 USC, Krishnaswamy, H. Hashemi, 24GHz in 130 nm shows
beam steering Tx and Rx with on air combining. The key is the
variable phase ring oscillator
2.35mm X 2.15mm

But wide-band beam forming is different…
23.5 USC, Chu, Roderick, H. Hashemi, UWB impulse radio
needs true time delay for beam forming and improved SNR.
The circuit has 188 spiral inductors!
3.2mm X 3.1mm
Ch1
Ch2
Ch3
Output
Ch4

Can do double beam too…
10.8 CalTech, Natarajan, Floyd, Ali Hajimiri, Combination of
discrete serial phase shifter and bidirectional variable phase
shifter and two ends reduce phase shift needs and allow double
beam at 60 GHz in 0.12 m SiGe
2.5mm X 1.85mm

Now think of combining these radars with the previous…
23.7 Infineon, Vienna U of Tech, 79 GHz Spread Spec Tx for
Automotive radar uses 1023 PRNS, 125m range & 12cm Res.
6.8 Arizona State U, 19 GHz FMCW Radar (512 MHz chirp) Tx
from a noise shaped 0.5 MHz Dev. over a 18.5 MHz reference.

Small RFID readers…
11.5 Intel, Catena, Single chip 0.18 m SiGe BiCMOS, 900 MHz
21 mm2, 1.5 W with 20dBm Tx, -85 dBm sensitivity, 0 dBm
blocker, external AC coupling caps, 3 AC coupling BW (CW
Tx, Modulation Tx, Tag response). Double Conv. in class 0
11.6 Samsung, Single chip 0.18 m CMOS for ISO 18000-6B and
EPC Gen 1 & 2, 23.8 mm2, 0.16 W, -9dBm to 4dBm Tx, -70
dBm sensitivity, multiple DC cancellations loops, use of CMOS
switching mixer and Op-Amp RC filters for linearity, external
30 dBm PA,
11.7 Broadcom, A. Safarian, Amin Shameli, Limit the signal and
subtract the carrier out, match by using two before/after RSSI’s.
Unknown phase shift is calculated by a frequency hopping
scheme.

11.5 Intel, Catena, Single chip 0.18 m SiGe BiCMOS,
900 MHz 21 mm2, 1.5 W with 20dBm Tx, -85 dBm sensitivity,
0 dBm blocker, external AC coupling caps, 3 AC coupling BW
(CW Tx, Modulation Tx, Tag response). Double Conv. in class 0

11.5 Intel, Catena, Single chip 0.18 m SiGe BiCMOS,
900 MHz 21 mm2, 1.5 W with 20dBm Tx, -85 dBm sensitivity,
0 dBm blocker,

11.6 Samsung, Single chip 0.18 m CMOS for ISO 18000-6B
and EPC Gen 1 & 2, 23.8 mm2, 0.16 W, -9dBm to 4dBm Tx,
-70 dBm sensitivity, multiple DC cancellations loops,
use of CMOS switching
mixer and Op-Amp RC
filters for linearity,
external 30 dBm PA

11.7 Broadcom, A. Safarian, Amin Shameli, Limit the signal
and subtract the carrier out, match by using two before/after
RSSI’s. Unknown phase shift is calculated by a frequency hopping
scheme.

RFID tags
EPC Gen2 and secure tags…
32.8 TI, EPC Gen2 chip in
0.13 m 0.55mm2, 192 bit
Memory, -14 dBm sensitivity,
using a custom Schottky,
1.45 regulated voltage,
1.8 v protection clamp,
Analog PRNG,
2.56 MHz clock
32.4 Semicon EnergyLab, Japan,
93.4mm2, with 8 bit CISC CPU,
on Glass substrate, 4K ROM, 512 bit
Ram, 0.54mW from 1.5 volts,
43 cm range @ 915 MHz with DES
Encryption
RFID tags
EPC Gen2 and secure tags…
32.8 TI, EPC Gen2 chip in
0.13 m 0.55mm2, 192 bit
Memory, -14 dBm sensitivity,
using a custom Schottky,
1.45 regulated voltage,
1.8 v protection clamp,
Analog PRNG,
2.56 MHz clock
32.4 Semicon EnergyLab, Japan,
93.4mm2, with 8 bit CISC CPU,
on Glass substrate, 4K ROM, 512 bit
Ram, 0.54mW from 1.5 volts,
43 cm range @ 915 MHz with DES
Encryption
TV chips
Slow, but moving! Reducing size & power… and less Ex. filters
11.1 Chrontel, 48-860 MHz Direct Conv. TV tuner, 25 mm2,
0.18mW @ 1.8 Vcc.
11.2 NXP, SiP TV with 0.81cm2 avoids up conversion, uses tracking
filters with on chip DC-DC converter for 30V Varactors, on
chip RF test generator for filter tuning and can receive all
Analog/Digital/Cable signals. Uses 750mW @ 3.3 Vcc.
11.3 MicroTune, A double conversion RF chip with external IF
filters can simultaneously meet all Analog/Digital/Cable specs.
1.5W from 5 and 3.3 volt supply.
11.4 Sharp, Two RF and BB chips use adaptive bias current for
mobile applications.

TV chips
Power reduction requires the analysis of interference statistics
0.5 SiGe BiCMOS 3.4X3.4 mm2 0.13 CMOS 4.3X4.3 mm2

87 mW or less from 2.9V 18mW from 1.2V core and 1.8V I/O

TV chips


TV chips


Software Radio
Still dreams…
19.6 IMEC, Craninckx, Compilation of ideas for SDR combined
with external MEMS structures.
32.1 IMEC, Ideas for power scaling in the RF and BB to adapt to
Sinad and RF power variation needs.

3G Systems
Kill out of band noise…
19.1 Analog Devices, Direct Conv. WCDMA Tx uses 4 GHz timing
to minimize the 2GHz Quad LO noise and transition errors that
produce out of band noise (-163 dBc/Hz @ 190 MHz offset)
19.2 ETH, Zurich, Similar to the above, but eliminates Quad LO
noise and transition errors by no output during transitions. (-156
dBc/Hz @ 190 MHz offset)
19.3 Nokia, Similar to the above, but a full mixed signal
implementation uses over-sampling and digital filters and digital
segmentation for power control (-143 dBc/Hz @ 190 MHz
offset)
19.4 Danube IC, Infineon, Single chip RF 2 band CDMA2000 TRx
in 0.13
19.5 Comlent Comm. Shanghai, Single chip RF 2 band TD-SCDMA
(Chinese 3G)
BT/WLAN Systems
Higher speed Blue Tooth and from 11b/g/a to 11n…
31.1 Broadcom, Marholev, Rofougaran…, An extended data rate
blue tooth chip in 0.13
31.2 Broadcom, Behzad, A double input double output 802.11n TRx
31.3 Infineon, U. of Erlangen, 802.11a/b/g in SOC,
31.4 Atheros, RF front end for WLAN integrates the TRx switch
with 20 dBm output. Tx low output impedance is matched to the
antenna through a network.

Broadband optical network Phy.
Electronics to Optics is quietly coming back…
2.1 Luxtera, 4x10Gb/s 0.13 um
2.2 Stanford U, 16Gb/s for interconnects in 90nm
2.3 National Taiwan U, Jri Lee, 20Gb/s Burst mode CDR
2.4 National Taiwan U, 33.6-33.8Gb/s Burst mode CDR in 90 nm
2.5 I&C U, ETRI, Hoseo U, Korea, Burst mode TIA with AGC for 1.25Gb/s EPON
2.6 National Chiao Tung U, ITRI, Taiwan, 3Gb/s Diff TIA
2.7 National Taiwan U, 40Gb/s TIA-AGC in 90 nm
2.8 Yonsei U, Ewha U, KETI, Korea, 2.5Gb/s limiting Amp in 0.18u
2.9 Silicon Labs, PLL for Sonet clock synthesis
24.1 TI, 12.5Gb/s SerDes in 65nm
24.2 Sony, Mixed Signal Systems, 10Gb/s TRx core in 90nm
30.7 Tech U Munich, Standford, Infineon, 10GHz amp with ESD
24.3 Rambus, 6.25Gb/s chip to chip in 90nm
24.4 Fujitsu, 4 chan 3.1/10.3Gb/s TRx
24.5 National Taiwan U, Jri Lee, A 20Gb/s transmitter
24.6 IBM, 16Gb/s transmitter in 65nm
30.8 Tech U of Denmark, 10Gb/s laser driver

RFID Reader
GPS/Galileo
All in one mobile phone solutions are coming but RF
design is getting even tougher!! Is there a room for us?
What do we do next in MiMOS?
Technology push analysis
Analysis of the ISSCC, CICC and VLSI Symp.
Market pull analysis
What do we do that serves our needs?
What can be sold as IP internationally?
Definition of 5-6 strategic directions
Helping start local companies in
these areas.

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ISSCC 2007 trends

RFID reader, Beam-forming,

KavoshCom Asia R&D 1 April 9, 2007

KavoshCom Asia R&D 2 April 9, 2007

KavoshCom Asia R&D 3 April 9, 2007

KavoshCom Asia R&D 4 April 9, 2007

But wait is it magnetic tuning or variable impedance with gm?

KavoshCom Asia R&D 6 April 9, 2007

KavoshCom Asia R&D 7 April 9, 2007

KavoshCom Asia R&D 8 April 9, 2007

KavoshCom Asia R&D 9 April 9, 2007

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KavoshCom Asia R&D 15 April 9, 2007

-112dBc/Hz @ 10MHz -143dBc/Hz @ 1MHz -110dBc/Hz @ 1MHz

KavoshCom Asia R&D 17 April 9, 2007

KavoshCom Asia R&D 18 April 9, 2007

KavoshCom Asia R&D 19 April 9, 2007

Then he normalizes it with

But won’t he be limited by

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0.5 SiGe BiCMOS 3.4X3.4 mm2 0.13 CMOS 4.3X4.3 mm2

KavoshCom Asia R&D 43 April 9, 2007

0.5 SiGe BiCMOS 3.4X3.4 mm2 0.13 CMOS 4.3X4.3 mm2

KavoshCom Asia R&D 44 April 9, 2007

0.5 SiGe BiCMOS 3.4X3.4 mm2 0.13 CMOS 4.3X4.3 mm2

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