8 fege |2)2) 3) 413 e278 (Fron ayia 116] 17] 18 [19/20 28 x LO |F \D\x W = > DAppI \F\D \S |xX\m)S |e os & SD £\s |D\s|sis|x|m|e 8 . [ = DADE Els| [sl ax\m{w ss = DSuUB LID|s|s|x|mw 5 | see PNG F\sisiol si slam Bs - L012) | esis iF ip ix MW IAD | |+ The ftsst DADDE onwst wait until LD gets fo the We stage to obtain the Value. of RE- © SP must wait unt +1 the fisst DADDI Computes dhe value of R41 curd reaches ihe Lo stage (mo foswosdirg) : + DSuB must wait until. the second DADDL - computes the value ce R2, and seaches the WB stage: + BNEZ must welt util DSUB Corvputes the value of RU and seaches the WR stage . * LD from next ttesation is’ ve-fetched after Hhe beanh is vesdved as taken. Loop execctes 99 Iterations ( 3496/ %, . ltesations Ob 98. Total umber of cycle fos while. Loop Is (48 +IS D418 = 1488 cycles.Pooblem 4 C)r Inet [1712/44 Is |o@| TS] [rwoypltfle [13 | Ie Lo fe fol felia} Ppa Ip \< lw om | E SID 1X lalw oe | > Ip D(x ml wlw pe tt FID IX Aw BNEX FID |S |x fray} Lp(2) FIS|EIDI% vo * |_} + « The fist ADDL still vnust wart until (D gets fp the WB stage to oblatn the valve of A4, but mow shall is implemented in Ex stage »and value is frovended divoctly to Ex slatge. + SD now waits Untill the fissl ADDL cornpules and forwards the value fsom Ex fo mem, 2 PSU B mow gets the value of R2. faswaxds by gecond APPL anc does rt need fo waits Total Cydes ic (9Bx%9)4 12 = B44 cyeles.Pooble m 2, (+ A cimple 4 stage pipe line with pescentage - listeve | Types Veo) 7» | Loops i V2) 4 Non- - — |84% “i O byanch R — i «2 fiefs i fiz Be Poanchall Cals aml | |] my as fo U I Jumps ca fi BE) Branched Lo ante Svvoe4 1 (2 TI) nchel] Conate-coral ly, ¢ qu, [t+ @& 2 kt (PEW ean we 13% x ; (PRL) Beandell Conditional No | #o% |i! in) 1 il k+l Pe) —| OO EEO eeVOOOO Problem 3 a): Given Oviginal clock cycle = IF — 1ns, ED — dns, €x —? {ns , MEM > 2ns- WR —> ASns and pipeline segisler delay o-4ns Ovt of given Stage. 5 MEM. has late execvtion Five of 2ns . Clock cycle 1 Hime = time taken by MEPA-4 pipeline vogisles delery , ins ( fo non- pipetinect) =2 +04 = Ded ns b)s We know CPE= Tleal CPL + stall cycle “ CPL is assumed as 4, As these is a stall ewry 4 instovetions, So, sball cycle pes Instovetton = 1 = oy 7 > oom CUE. 1 Os: lou C) Speedup = Execution time fos non - rion ~ pipelined, Executibn tine fos “pifelined Execution time - I xcCPl xc cle CPL =1Speed up = Ex Ixl Tx '2 v24 > | 2-628 Speed ep= 2-67 tines.